ENVELOPE DETECTOR CIRCUIT, CORRESPONDING RECEIVER CIRCUIT AND GALVANIC ISOLATOR DEVICE

Abstract

A rectifier stage includes a differential input transistor pair coupled between a reference voltage node and an intermediate node, and a load circuit coupled between the intermediate node and a supply voltage node. The differential input transistor pair receives a radio-frequency amplitude modulated signal. A rectified signal indicative of an envelope of the radio-frequency amplitude modulated signal is produced at the intermediate node. An amplifier stage coupled to the intermediate node produces an amplified rectified signal at an output node that is indicative of the envelope of the radio-frequency amplitude modulated signal. The rectifier stage includes a resistive element coupled between the intermediate node and the supply voltage node in parallel to the load circuit.

Claims

1. A circuit, comprising: a rectifier stage including: a differential input transistor pair coupled between a reference voltage node and an intermediate node, the differential input transistor pair being configured to receive a radio-frequency amplitude modulated signal; a load circuit coupled between the intermediate node and a supply voltage node; and a first resistive element coupled between said intermediate node and said supply voltage node in parallel with said load circuit; wherein a rectified signal indicative of an envelope of said radio-frequency amplitude modulated signal is produced at said intermediate node; and an amplifier stage coupled to receive said rectified signal from said intermediate node and configured to produce an amplified rectified signal at an output node.

2. The circuit of claim 1, wherein said load circuit is an active load circuit including a load transistor and a low-pass circuit.

3. The circuit of claim 2, wherein said load transistor has a current path coupled between said intermediate node and said supply voltage node, and where said low-pass circuit comprises: a second resistive element coupled between said intermediate node and a control terminal of said load transistor, and a capacitive element coupled between said control terminal of said load transistor and said supply voltage node.

4. The circuit of claim 3, wherein said first resistive element has a resistance value in a range of 25 kΩ to 50 kΩ, and wherein said second resistive element has a resistance value in a range of 1 MΩ to 3 MΩ.

5. The circuit of claim 1, wherein said differential input transistor pair comprises a first input transistor and a second input transistor having current paths arranged in parallel between said reference voltage node and said intermediate node, and wherein control terminals of said first input transistor and said second input transistor are configured to receive said radio-frequency amplitude modulated signal.

6. The circuit of claim 1, wherein said amplifier stage comprises an output transistor and an output load coupled between a conductive terminal of said output transistor and said reference voltage node, and wherein said output node is intermediate said conductive terminal of said output transistor and said output load.

7. The circuit of claim 6, wherein said amplifier stage further comprises: a current-matching transistor having a current path arranged between said supply voltage node and a current control node, and a control terminal coupled to said intermediate node; a bias source coupled between said current control node and said reference voltage node to sink a current from said current control node; and a current-mirroring transistor having a current path arranged between said supply voltage node and said current control node, a control terminal and a drain or collector terminal coupled to said control terminal; wherein the control terminal of said current-mirroring transistor is coupled to a control terminal of said output transistor.

8. The circuit of claim 7, further comprising a current-matching resistive element coupled between said supply voltage node and said current control node.

9. The circuit of claim 8, wherein said current-matching resistive element has a resistance value in a range of 25 kΩ to 50 kΩ.

10. The circuit of claim 6, wherein said output transistor is arranged in one of a common source or common emitter configuration, with said conductive terminal comprising one of a drain or collector, respectively.

11. The circuit of claim 1, further comprising a comparator circuit configured to compare said amplified rectified signal to a threshold signal to generate a pulse-width modulated output signal indicative of the envelope of said radio-frequency amplitude modulated signal.

12. The circuit of claim 10, further comprising: a radio-frequency antenna configured to receive said radio-frequency amplitude modulated signal; and a PWM demodulator circuit configured to demodulate said pulse-width modulated output signal to generate an output digital data signal.

13. The circuit of claim 10, further comprising: a transmitter circuit configured to transmit said radio-frequency amplitude modulated signal; and wherein the transmitter circuit is isolated by a galvanic isolation barrier from a receiver circuit that includes said rectifier stage, said amplifier stage and comparator circuit.

14. The circuit of claim 13, wherein the transmitter circuit and the receiver circuit are provided as separate chips arranged on respective electrically-isolated die pads, and wherein said galvanic isolation barrier is provided by a molded package on the separate chips.

15. A circuit, comprising: a rectifier stage including: a differential input transistor pair coupled between a reference voltage node and a first intermediate node, the differential input transistor pair being configured to receive a radio-frequency amplitude modulated signal; an active load circuit comprising: a load transistor having a current path coupled between said first intermediate node and said supply voltage node; and a low-pass circuit comprising a series circuit formed by a resistor and capacitor coupled in series between said first intermediate node and said supply voltage node, wherein a second intermediate node of said series circuit is connected to a control terminal of said load transistor; and a resistive element coupled between said intermediate node and said supply voltage node in parallel with said load circuit; wherein a rectified signal indicative of an envelope of said radio-frequency amplitude modulated signal is produced at said intermediate node; and an amplifier stage coupled to receive said rectified signal from said intermediate node and configured to produce an amplified rectified signal at an output node.

16. The circuit of claim 15, wherein said resistor of the series circuit is connected between the first and second intermediate nodes, and wherein said capacitor of the series circuit is connected between the second intermediate node and the supply voltage node.

17. The circuit of claim 15, wherein said resistive element has a resistance value in a range of 25 kΩ to 50 kΩ, and wherein resistor of the series circuit has a resistance value in a range of 1 MΩ to 3 MΩ.

18. The circuit of claim 15, wherein said differential input transistor pair comprises a first input transistor and a second input transistor having current paths arranged in parallel between said reference voltage node and said intermediate node, and wherein control terminals of said first input transistor and said second input transistor are configured to receive said radio-frequency amplitude modulated signal.

19. The circuit of claim 15, further comprising a comparator circuit configured to compare said amplified rectified signal to a threshold signal to generate a pulse-width modulated output signal indicative of the envelope of said radio-frequency amplitude modulated signal.

20. A circuit, comprising: a rectifier stage including: a differential input transistor pair coupled between a reference voltage node and an intermediate node, the differential input transistor pair being configured to receive a radio-frequency amplitude modulated signal; a load circuit coupled between the intermediate node and a supply voltage node; and a resistive element coupled between said intermediate node and said supply voltage node in parallel with said load circuit; wherein a rectified signal indicative of an envelope of said radio-frequency amplitude modulated signal is produced at said intermediate node; and an amplifier stage comprising: a current-matching transistor having a current path arranged between said supply voltage node and a current control node, and a control terminal coupled to said intermediate node; a bias source coupled between said current control node and said reference voltage node to sink a current from said current control node; and a current-mirroring circuit having an input current path arranged between said supply voltage node and said current control node and having an output current path arranged between said supply voltage node and an output node where an amplified rectified signal is produced.

21. The circuit of claim 20, further comprising a current-matching resistive element coupled between said supply voltage node and said current control node.

22. The circuit of claim 21, wherein said resistive element has a resistance value in a range of 25 kΩ to 50 kΩ, and wherein said current-matching resistive element has a resistance value in a range of 25 kΩ to 50 kΩ.

23. The circuit of claim 20, wherein said differential input transistor pair comprises a first input transistor and a second input transistor having current paths arranged in parallel between said reference voltage node and said intermediate node, and wherein control terminals of said first input transistor and said second input transistor are configured to receive said radio-frequency amplitude modulated signal.

24. The circuit of claim 20, further comprising a comparator circuit configured to compare said amplified rectified signal to a threshold signal to generate a pulse-width modulated output signal indicative of the envelope of said radio-frequency amplitude modulated signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

[0023] FIG. 1 illustrates a conventional galvanically-isolated system;

[0024] FIG. 2 shows an isolated system comprising a first integrated circuit chip and a second integrated circuit chip;

[0025] FIG. 3 is a simplified circuit block diagram exemplary of an isolated data transfer channel of an isolated system;

[0026] FIG. 4 is exemplary of possible time behavior of electrical signals in the system of FIG. 3;

[0027] FIG. 5 shows a receiving front-end circuit;

[0028] FIG. 6 is a circuit diagram exemplary of a rectifier stage;

[0029] FIG. 7 is a circuit diagram exemplary of an envelope detector circuit; and

[0030] FIG. 8 is a circuit diagram exemplary of an envelope detector circuit according to one or more embodiments of the present description.

DETAILED DESCRIPTION

[0031] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0032] Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0033] The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0034] Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for brevity.

[0035] By way of introduction to the detailed description of exemplary embodiments, reference may first be made to FIG. 7, which is a circuit diagram exemplary of a two-stage envelope detector circuit 70 suitable for use in an amplitude-shift keying (ASK) detector.

[0036] As exemplified in FIG. 7, the envelope detector circuit 70 comprises an input stage 71 and an output stage 72.

[0037] The input stage 71 comprises an input differential pair comprising two transistors (e.g., n-channel MOS transistors) M.sub.1 and M.sub.2. The input radio-frequency signal Sm′ is applied between the (gate) control terminals of the two transistors M.sub.1 and M.sub.2 of the differential pair. The transistors M.sub.1, M.sub.2 have their source terminals coupled to a reference voltage node GND and their drain terminals coupled to a common intermediate node 710.

[0038] The input stage 71 comprises a load coupled between the common intermediate node 710 and a supply node which provides a supply voltage V.sub.CC. For instance, as exemplified in FIG. 7, the load comprises an active (e.g., self-biased) load including a transistor M.sub.3 and a low-pass filter R.sub.F, C.sub.F. The transistor M.sub.3 (e.g., a p-channel MOS transistor) has its current path arranged between the common intermediate node 710 and the supply node V.sub.CC. The low-pass filter comprises a resistive element (e.g., a resistor R.sub.F) coupled between the common intermediate node 710 and the (gate) control terminal of the transistor M.sub.3, and a capacitive element (e.g., a capacitor C.sub.F) coupled between the (gate) control terminal of the transistor M.sub.3 and the supply node V.sub.CC.

[0039] The output stage 72 comprises a common source or common emitter arrangement including a transistor M.sub.4 and a resistive load R.sub.L, the transistor M.sub.4 and the resistive load R.sub.L being coupled in series between the supply node V.sub.CC and the reference voltage node GND. The transistor M.sub.4 has a (gate) control terminal coupled to the common intermediate node 710 (acting as the output node of the first stage 71). An output node 720 intermediate the transistor M.sub.4 and the resistive load R.sub.L provides the envelope output signal ENV.sub.OUT. In particular, the transistor M.sub.4 is a p-channel MOS transistor having a source terminal coupled to the supply node V.sub.CC and a drain terminal coupled to the output node 720, and the resistive load R.sub.L is coupled between the drain terminal of transistor M.sub.4 and the reference voltage node GND.

[0040] Therefore, in an envelope detector circuit 70 as exemplified in FIG. 7, the (on-off) modulated differential input signal S.sub.RF is first rectified and then amplified to produce an envelope signal ENV.sub.OUT. The output node 720 of the envelope detector circuit 70 is coupled to a comparator circuit (not visible in the Figures) so that the envelope signal ENV.sub.OUT is converted into a single-ended rail-to-rail PWM data signal PWM.sub.OUT.

[0041] It is noted that a circuit as exemplified in FIG. 7 can be fully integrated in a silicon die (only) for use in high data rate communications. The small-signal loop gain T and the loop gain-bandwidth product f.sub.GBW can be computed according to the equations below:

[00001]$T=\frac{g_{m3}.Math.r_{o1}}{1+{\mathrm{sR}}_F{C}_F}$$f_{GBW}=\frac{g_{m3}.Math.r_{o1}}{2{\pi R}_F{C}_F}$

[0042] Assuming, by way of example, a high data rate equal to f.sub.BR=100 Mb/s, then f.sub.GBW=f.sub.BR/25=4 MHz, and assuming also R.sub.F=10 kΩ this leads to C.sub.F=120 pF which is a high value, but still feasible to integrate into a silicon die.

[0043] Assuming instead, again by way of example only, a low data rate equal to f.sub.BR=400 kb/s, then f.sub.GBW=f.sub.BR/25=16 kHz, and assuming also R.sub.F=75 kΩ this leads to C.sub.F=4 nF which is a capacitance value too high to integrate into a silicon die.

[0044] Therefore, at low data rates an envelope detector circuit as exemplified in FIG. 7 requires an external component (e.g., an external capacitor C.sub.F).

[0045] One or more embodiments relate to an improved envelope detector circuit suitable for use (also) at low data rates, as exemplified in FIG. 8, which is a circuit diagram exemplary of a three-stage envelope detector circuit 80 suitable for use in an amplitude-shift keying (ASK) detector.

[0046] As exemplified in FIG. 8, the envelope detector circuit 80 comprises an input stage 81, an intermediate stage 82 and an output stage 83.

[0047] The input stage 81 comprises an input differential pair comprising two transistors (e.g., n-channel MOS transistors) M.sub.1 and M.sub.2. The input radio-frequency signal S.sub.RF is applied between the (gate or base) control terminals of the two transistors M.sub.1 and M.sub.2 of the differential pair. The transistors M.sub.1, M.sub.2 have their source or emitter terminals coupled to a reference voltage node GND and their drain or collector terminals coupled to a common intermediate node 810. The input stage 81 further comprises a load coupled between the common intermediate node 810 and a supply node providing a supply voltage V.sub.CC. For instance, as exemplified in FIG. 8, the load comprises an active (e.g., self-biased) load including a transistor M.sub.3 and a low-pass filter R.sub.F, C.sub.F. The transistor M.sub.3 (e.g., a p-channel MOS transistor) has its current path arranged between the common intermediate node 810 and the supply node V.sub.CC. The low-pass filter comprises a resistive element (e.g., a resistor R.sub.F) coupled between the common intermediate node 810 and the (gate or base) control terminal of the transistor M.sub.3, and a capacitive element (e.g., a capacitor C.sub.F) coupled between the (gate or base) control terminal of the transistor M.sub.3 and the supply node V.sub.CC.

[0048] As exemplified in FIG. 8, the input stage 81 further comprises a resistive element R.sub.L1 coupled in parallel to the active load, e.g., coupled between the common intermediate node 810 and the supply node V.sub.CC. Arranging a further resistive element R.sub.L1 in the input stage 81 provides a further degree of freedom in the design of the envelope detector circuit 80, so that the resistive element R.sub.F can be set (e.g., dimensioned) to reduce the loop gain-bandwidth product f.sub.GBW, which in turn facilitates implementing the capacitive element C.sub.F as an integrated component, while R.sub.L1 can be set (e.g., dimensioned) so as to determine the gain and output pole frequency of the input stage 81, thus mitigating (e.g., avoiding) edge distortions on the output PWM signal.

[0049] The intermediate stage 82 comprises a current matching circuit arrangement. As exemplified in FIG. 8, the intermediate stage 82 comprises a transistor M.sub.4 (e.g., a p-channel MOS transistor) having a current path arranged between the supply node V.sub.CC and a bias source 822, and a control (gate or base) terminal coupled to the intermediate node 810 of the input stage 81. A current 14 flows through the transistor M.sub.4. For instance, the transistor M.sub.4 has a source or emitter terminal coupled to the supply node V.sub.CC and a drain or collector terminal coupled to a further intermediate node 820, and the bias source 822 comprises a current generator arranged between the intermediate node 820 and the reference voltage node GND to sink a bias current I.sub.b from the intermediate node 820 towards the reference voltage node GND.

[0050] Additionally, the intermediate stage 82 comprises a resistive element R.sub.L2 coupled in parallel to the current path of transistor M.sub.4, e.g., coupled between the intermediate node 820 and the supply node V.sub.CC. Arranging a resistive element R.sub.L2 in the intermediate stage 82 facilitates restoring the matching conditions between the first stage 81 (transistor M.sub.3 and resistance R.sub.L1) and the second stage 82 (transistor M.sub.4 and resistance R.sub.L2), thus improving the accuracy in the bias current I.sub.5 of the output stage 83.

[0051] The output stage 83 comprises an amplifier stage, e.g., a folded amplifier stage. As exemplified in FIG. 8, the output stage 83 comprises a current mirror arrangement comprising a first transistor M.sub.5 (e.g., a p-channel MOS transistor) and a second transistor M.sub.6 (e.g., a p-channel MOS transistor). The first transistor M.sub.5 has a current path arranged between the supply node V.sub.CC and the intermediate node 820, through which a current I.sub.5=I.sub.b−I.sub.4 flows. The second transistor M.sub.6 is arranged in series to an output load R.sub.L3 (e.g., a resistive load) between the supply node V.sub.CC and the reference voltage node GND, so that a copy of current I.sub.5 flows through M.sub.6 and R.sub.L3, thereby providing a single-ended output signal ENV.sub.OUT at the node 830 intermediate the transistor M.sub.6 and the load R.sub.L3.

[0052] The folded amplifier comprising transistors M.sub.5 and M.sub.6 allows increasing the resistance value of the load R.sub.L3 and therefore the value of the second stage gain, insofar as the unipolar output signal ENV.sub.OUT becomes a positive voltage. Thus, the output bias voltage can be set to a value close to V.sub.CC. Purely by way of non-limiting example, with V.sub.CC=3.5 V the resistance R.sub.L3 is twice as big as the output load of a traditional configuration (e.g., R.sub.L in FIG. 7), thereby providing an additional gain of about 6 dB.

[0053] The output node 830 of the envelope detector circuit 80 is coupled to a comparator circuit (not visible in the Figures) so that the envelope signal ENV.sub.OUT is converted into a single-ended rail-to-rail PWM data signal PWM.sub.OUT.

[0054] It is noted that one or more embodiments as exemplified in FIG. 8 can be fully integrated in a silicon die (also) for use in low data rate communications. The small-signal loop gain T and the loop gain-bandwidth product f.sub.GBW can be computed according to the equations below:

[00002]$T=\frac{g_{m3}.Math.\left(r_{o1}//R_{L1}\right)}{1+{\mathrm{sR}}_F{C}_F}\approx \frac{g_{m3}.Math.R_{L1}}{1+{\mathrm{sR}}_F{C}_F}{f}_{\mathrm{GBW}}=\frac{g_{m3}.Math.R_{L1}}{2\pi R_F{C}_F}$

[0055] Assuming, by way of example, a low data rate equal to f.sub.BR=400 kb/s, then f.sub.GBW=f.sub.BR/25=16 kHz, and assuming also R.sub.F=2 MΩ and R.sub.L1=75 kΩ this leads to C.sub.F=50 pF which is a capacitance value which can be integrated into a silicon die.

[0056] One or more embodiments may be applied in a package-scale galvanic isolator device (e.g., as illustrated in FIG. 2), where galvanic isolation can be implemented without using specific high voltage components, the inter-chip communication channel can be implemented by means of a wireless radio-frequency transmission, and appropriately choosing the distance between the two chips facilitates achieving high isolation rating (e.g., 10 to 12 kV for reinforced isolation) and/or higher common mode transient immunity, CMTI (e.g., higher than 100 kV).

[0057] However, those of skill in the art will understand that reference to a package-scale galvanic isolator device is made by way of example only, and that one or more embodiments may be generally applied to any kind of galvanic isolator device.

[0058] One or more embodiments have been disclosed herein with reference to specific implementations using complementary MOS technology. Those of skill in the art will understand that bipolar (BJT) technology can also be adopted as implementation technology for one or more embodiments, provided that it includes complementary transistors.

[0059] One or more embodiments may thus provide an envelope detector circuit which can be fully integrated in a single chip (also) for use at low data rates, e.g., without using passive discrete components to operate the circuit at low data rates. By way of example, such envelope detector circuits may operate at frequencies lower than 1 MHz (e.g., in certain applications such as gate driver for motor control).

[0060] One or more embodiments may additionally provide one or more of the following advantages: high immunity to common mode transients, low current consumption, high gain, and low cost.

[0061] As exemplified herein, a circuit (e.g., 80) comprises a rectifier stage (e.g., 81) including a differential input transistor pair (e.g., M.sub.1, M.sub.2) coupled between a reference voltage node (e.g., GND) and an intermediate node (e.g., 810), and a load (e.g., M.sub.3, R.sub.F, C.sub.F) coupled between the intermediate node and a supply voltage node (e.g., V.sub.CC). The differential input transistor pair is configured to receive a radio-frequency amplitude modulated signal (e.g., S.sub.RF+, S.sub.RF−). A rectified signal indicative of an envelope of the radio-frequency amplitude modulated signal is produced at the intermediate node. The circuit comprises an amplifier stage (e.g., 82; 83) coupled to the intermediate node to receive the rectified signal and configured to produce at an output node (e.g., 830) an amplified rectified signal (e.g., ENV.sub.OUT) indicative of the envelope of the radio-frequency amplitude modulated signal. The rectifier stage further comprises a first resistive element (e.g., Ru) coupled between the intermediate node and the supply voltage node in parallel to the load.

[0062] As exemplified herein, the load comprises an active load including a load transistor (e.g., M.sub.3) and a low-pass circuit arrangement (e.g., R.sub.F, C.sub.F).

[0063] As exemplified herein, the active load comprises the load transistor having a current path coupled between the intermediate node and the supply voltage node, a second resistive element (e.g., R.sub.F) coupled between the intermediate node and a control terminal of the load transistor, and a capacitive element (e.g., C.sub.F) coupled between the control terminal of the load transistor and the supply voltage node.

[0064] As exemplified herein, the first resistive element has a resistance value in the range of 25 kΩ to 50 kΩ, and the second resistive element has a resistance value in the range of 1 MΩ to 3 MΩ. For instance, the first resistive element is sized to correctly polarize the transistors M.sub.1, M.sub.2 and together with the biasing current (e.g., 2*I.sub.d1,2 where Id is the current flowing through one of the transistors M.sub.1, M.sub.2) defines the gain of the first stage. For instance, an amplitude gain in the range of 2 to 3 is obtained.

[0065] As exemplified herein, the capacitive element has a capacitance value in the range of 50 pF to 150 pF.

[0066] As exemplified herein, the differential input transistor pair comprises a first input transistor (e.g., M.sub.1) and a second input transistor (e.g., M.sub.2) having the current paths therethrough arranged in parallel between the reference voltage node and the intermediate node, and the control terminals of the first input transistor and the second input transistor are configured to receive the radio-frequency amplitude modulated signal therebetween.

[0067] As exemplified herein, the amplifier stage comprises an output transistor (e.g., M.sub.6) arranged in a common source or common emitter configuration and an output load (e.g., R.sub.L3) coupled between a drain or collector terminal of the output transistor and the reference voltage node, and the output node is intermediate the drain or collector terminal of the output transistor and the output load.

[0068] As exemplified herein, the amplifier stage comprises: [0069] a current-matching transistor (e.g., M.sub.4) having a current path arranged between the supply voltage node and a current control node (e.g., 820), and a control terminal coupled to the intermediate node; [0070] a bias source (e.g., 822) coupled between the current control node and the reference voltage node to sink a current (e.g., I.sub.b) from the current control node, and [0071] a current-mirroring transistor (e.g., M.sub.5) having a current path arranged between the supply voltage node and the current control node) and having a drain or collector terminal coupled to its control terminal.

[0072] As exemplified herein, the control terminal of the current-mirroring transistor is coupled to a control terminal of the output transistor.

[0073] As exemplified herein, the circuit comprises a current-matching resistive element (e.g., R.sub.L2) coupled between the supply voltage node and the current control node.

[0074] As exemplified herein, the current-matching resistive element has a resistance value in the range of 25 kΩ to 50 kΩ. For instance, the current-matching resistive element is sized to correctly polarize the transistor M.sub.4 and together with the biasing current I.sub.b it defines the gain of the second stage.

[0075] As exemplified herein, the circuit comprises a comparator circuit configured to compare the amplified rectified signal to a threshold signal to generate a pulse-width modulated output signal (e.g., PWM.sub.OUT) indicative of the envelope of the radio-frequency amplitude modulated signal.

[0076] As exemplified herein, a receiver circuit (e.g., 200.sub.2) comprises: [0077] a radio-frequency antenna (e.g., 204.sub.2) configured to receive a radio-frequency amplitude modulated signal (e.g., S.sub.RF); [0078] an envelope detector circuit according to one or more embodiments configured to receive the radio-frequency amplitude modulated signal from the antenna and to generate the pulse-width modulated output signal indicative of the envelope of the radio-frequency amplitude modulated signal received; and [0079] a PWM demodulator circuit (e.g., 302.sub.2) configured to demodulate the pulse-width modulated output signal to generate an output digital data signal (e.g., OUT).

[0080] As exemplified herein, an isolator device (e.g., 20) comprises a transmitter circuit (e.g., 200.sub.1) configured to transmit a radio-frequency amplitude modulated signal, and a receiver circuit according to one or more embodiments, and the transmitter circuit and the receiver circuit are isolated by a galvanic isolation barrier (e.g., 306).

[0081] As exemplified herein, the transmitter circuit and the receiver circuit are provided as separate chips arranged on respective electrically-isolated die pads (e.g., 202.sub.1, 202.sub.2), and the isolator device further comprises a molded package (e.g., 203) providing the galvanic isolation barrier.

[0082] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

[0083] The claims are an integral part of the technical teaching provided herein in respect of the embodiments.

[0084] The extent of protection is determined by the annexed claims.