Method and system for optimizing short term stability of a clock pulse

Abstract

A system for optimizing short-term stability of a clock source clock pulse synchronized with a long-term stable reference-clock transmits clock numbers of a first reference clock to the clock source, between an initialization time and several times within a data-packet network. The clock pulse is adjusted by controlling a difference between clock numbers of the first reference clock received in the clock source and clock numbers of the first reference clock between the initialization time and the reception times of the clock numbers of the first reference clock. Clock numbers of a second reference clock are transmitted to the clock source with the clock number of at least one second reference-clock source at individual times. The maximum difference between the first and the second reference clock is known. The difference between the clock pulse of the clock source and each second reference clock is limited to an adjustable threshold value.

Claims

1. A method comprising: transmitting clock-cycle numbers of a first reference clock signal of a first reference-clock source to a clock source between an initialization time and several times within a data-packet network, wherein the clock source is synchronized with a first long-term stable reference-clock source; adjusting a clock pulse of the clock source by controlling a difference between clock-cycle numbers of the first reference clock signal received in the clock source and clock-cycle numbers of the first reference clock signal between the initialization time and the respective reception times of the clock-cycle numbers of the first reference clock signal, wherein the frequency of a frequency oscillator integrated in a phase control is used for matching the received clock-cycle numbers of the first reference clock signal; transmitting clock-cycle numbers of at least one second reference clock signal of a data packet, which receives the clock-cycle number from at least one second, free-running reference-clock source at individual times to the clock source; and limiting the difference between the clock pulse of the clock source and each second reference clock signal to a first adjustable threshold value.

2. The method according to claim 1, wherein the clock pulse of the clock source in a superposed frequency control is controlled in such a manner that the difference between the clock pulse of the clock source and the second reference clock signal is less than the first adjustable threshold value.

3. The method according to claim 1, wherein the difference between the frequency with which the difference between the clock pulse of the clock source and the first reference clock signal is controlled within a phase-locked loop and the second reference clock signal is limited to a second adjustable threshold value.

4. The method according to claim 1, wherein the clock-cycle numbers of the second reference clock signal of the respective at least one second reference-clock source are each transmitted at periodic times, and a second reference clock signal of the respective at least one second reference-clock source is determined from the received clock-cycle numbers of the second reference clock signal of the respective second reference-clock source in the clock source.

5. The method according to claim 1, wherein the second reference clock signal of a single, second reference-clock source is determined in the clock source.

6. The method according to claim 1, wherein the second reference clock signal is determined by averaging the second reference clock signals in the clock source generated respectively from the at least one second reference-clock source.

7. The method according to claim 6, wherein the at least one second reference-clock source comprises a temperature-compensated quartz oscillator.

8. The method according to claim 1, wherein, in the case of a failure of the data-packet network, the second reference clock signal is determined continuously from the received clock-cycle numbers of the second reference clock signal by means of regression, and the clock pulse of the clock source is determined within a frequency control with the determined second reference clock signal as the target frequency value.

9. The method according to claim 1, wherein, in the case of a failure of the data-packet network, the first reference clock signal is determined by means of regression from the clock-cycle numbers of the first reference clock signal received until the failure, and the clock pulse of the clock source is determined within a frequency control with the determined first reference clock signal as the target frequency value.

10. The method according to claim 1, wherein the rate with which the clock-cycle numbers of the first reference clock signal are transmitted to the clock source is increased, as soon as the difference between the clock pulse of the clock source and the second reference clock signal exceeds a third adjustable threshold value.

11. The method according to claim 1, wherein the maximum difference between the first and the second reference clock signals of the clock source is known or specified.

12. A system comprising: a first processing device configured to determine clock-cycle numbers of a first reference clock signal of a first reference-clock source between an initialization time and several times, wherein the first processing device is further configured to transmit, via a data-packet network, the clock-cycle numbers of the first reference clock signal to a third processing device; a second processing device configured to determine clock-cycle numbers of a second reference clock signal between the initialization time and the respective several times, wherein the second processing device is further configured to transmit, via a second network, the clock-cycle numbers of the second reference clock signal determined respectively from each second reference-clock source to the third processing device, wherein the third processing device is configured to determine a clock pulse based on the received clock-cycle numbers of the first reference clock signal and the received clock-cycle numbers of the second reference clock signal, wherein the clock source is synchronized with a first long-term stable reference-clock source, and wherein the frequency of a frequency oscillator integrated in a phase control is used for matching the received clock-cycle numbers of the first reference clock signal.

13. The system according to claim 12, wherein the second reference-clock source comprises a temperature-compensated quartz oscillator.

14. The system according to claim 12, wherein the second network is a local high-speed network.

15. The system according to claim 12, wherein a maximum difference between the first reference clock signal and the second reference clock signal of the clock source is known or specified.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Various example embodiments of the present invention are explained in detail below with reference to the drawings. The figures of the drawings show:

(2) FIG. 1 illustrates a block-circuit diagram of a system for clock synchronization of several data-processing units by means of the Network-Time-Protocol;

(3) FIG. 2 illustrates a block-circuit diagram of a system for clock synchronization of a data-processing unit by means of the Network-Time-Protocol;

(4) FIG. 3 illustrates a time-flow diagram of the phase and the frequency in a phase-locked loop;

(5) FIG. 4 illustrates a block-circuit diagram of a system for optimizing short-term stability of a clock pulse, in accordance with example embodiments of the present invention;

(6) FIG. 5 illustrates a diagram illustrating the relative frequency change of a quartz oscillator dependent upon temperature and the intersection angle of the quartz, in accordance with example embodiments of the present invention;

(7) FIG. 6 illustrates a diagram illustrating the relative change in clock pulse in the case of an averaging of the clock pulses generated by several temperature-compensated quartz oscillators, in accordance with example embodiments of the present invention;

(8) FIG. 7 illustrates a time-flow diagram of the accumulated clock pulses from several clocks with respectively different frequency drift, in accordance with example embodiments of the present invention;

(9) FIG. 8A illustrates a flow chart depicting a first method for optimizing short-term stability of a clock pulse, in accordance with example embodiments of the present invention;

(10) FIG. 8B illustrates a flow chart depicting a second method for optimizing short-term stability of a clock pulse, in accordance with example embodiments of the present invention; and

(11) FIG. 8C illustrates a flow chart depicting a third method for optimizing short-term stability of a clock pulse, in accordance with example embodiments of the present invention.

DETAILED DESCRIPTION

(12) An example embodiment of a system for optimizing short-term stability of a clock pulse for a clock source in a process computer, for example in a head end of a radio station, is illustrated in FIG. 4.

(13) The head station (head end) 7 of a radio-broadcasting station, in which various video and audio datastreams are encrypted and combined to form a single digital, encrypted transport datastream, is typically realized by a process computer, that is, by a server with a sufficiently large computing power for the realization of signal-processing functions in real-time.

(14) The server of the head end 7 is clocked by an internal clock source 8, which provides a comparatively poor accuracy by comparison with a reference-clock sourcefor example the GPS-time or the UTC-time used by NTP-servers. With commercially available servers, this is typically within the order of magnitude of +/100 ppm. Such a poor accuracy of the clock source leads to a driftthat is, a clock variationof the clock pulses generated by the clock source, which leads to an inaccuracy of the clock time of the clock source by comparison with a reference-clock time of a reference-clock source in the order of magnitude of a few tens of milliseconds over a running time of one hour. Such an inaccuracy in the absolute clock time of the clock source is unacceptable for the real-time operation of a head end, because the data packets of the encrypted transport datastream, which are provided with a timestamp from the clock source, are buffered in the buffers of the individual transmitters either for too long and therefore cause an overflow of the buffers, or are buffered for too short a time and therefore cause a zero loading of the buffers. Both cases lead to an undesirable operational disturbance.

(15) In order to increase the accuracy of the internal clock source 8, the clock pulse of this clock source 8 is synchronized with the reference clock of a reference-clock source. As already mentioned above, the clock-cycle number of the reference-time source 2.sub.1 or respectively 2.sub.2 counted in the individual NTP-servers 1.sub.1 or respectively 1.sub.2 at a given calling time since an initialization time is transmitted for this purpose to the head end 7 via the data-packet orientated network 9, preferably via the Internet using the method of the Network-Time-Protocol (NTP) from several NTP-servers 1.sub.1 or respectively 1.sub.2, which are each coupled to a high-precision reference-time source 2.sub.1 or respectively 2.sub.2 (for the UTC reference time). With regard to the details of the method of the Network-Time-Protocol (NTP), reference is made to David L. Mills Internet Time Protocol: The Network Time Protocol, IEEE Transactions on Communications, Volume 39, Number 10, October 1991, pages 1482 to 1493, the entirety of which is incorporated herein by reference.

(16) The individual video and audio datastreams associated respectively with each of the programs, which are generated in one or more studios, are transmitted in different data formats (for example, Serial-Digital-Interface (SDI) for un-compressed digital video data, Asynchronous-Serial-Interface (ASI) for pre-compressed digital video data, and Audio-Engineering-Society-3 (AES3) for digital audio data) from the individual studios to the head end 7. These are then filled in associated input adapters 10.sub.1 or respectively 10.sub.2, which are positioned close to the head end 7 and coupled to clock sources 11.sub.1 or respectively 11.sub.2 with a comparatively high accuracy in the order of magnitude of +/1 ppm, into data packets, which are transmitted to the head end 7 via a local, high-speed network 12, preferably via an intranet.

(17) In a similar manner, the transport datastream generated by the head end 7 is transmitted with its individual data packets via a local high-speed network 13, preferably via the intranet, to an output adapter 14 positioned close to the head end 7 with a clock source 15 with a high-frequency stability in the order of magnitude of +/1 ppm, in which the data packets of the incoming transport datastream are converted from Internet Protocol (IP) data format into an appropriate data format (for example, Asynchronous Serial Interface (ASI)) for transmission to the individual transmitters.

(18) In the following section, in accordance with such embodiments for optimizing short-term stability of a clock pulse for a clock source in a process computer, for example in a head end of a radio station, a first example method is presented on the basis of the flow-chart in FIG. 8A with reference to the corresponding system illustrated in the block-circuit diagram of FIG. 4.

(19) In a first method step S10, in at least one first reference-clock source, preferably according to FIG. 4, within the NTP-servers 1.sub.1 or respectively 1.sub.2, the clock pulses of a clock generator 2.sub.1 or respectively 2.sub.2, the clock pulse of the UTC time, are counted from a defined or agreed initialization time, in each case in a counter not illustrated in FIG. 4. If the individual NTP-server 1.sub.1 or respectively 1.sub.2 receives a time request from an associated clock filter 3.sub.1 or respectively 3.sub.2 integrated in the head end 7 at a given time, the counter status of the counter associated with the respective NTP-server 1.sub.1 or respectively 1.sub.2 at this time is read out and transmitted in a data packet as a timestamp information for transmission via the data-packet orientated network 9.

(20) After the reception of each data packet with a timestamp information in the associated clock filter 3.sub.1 or respectively 3.sub.2, the associated clock filter 3.sub.1 or respectively 3.sub.2 determines the transmission time of each data packet, which contains, as timestamp information, a clock number of the associated first reference-clock source 1.sub.1 or respectively 1.sub.2 at the transmission time as a mean value of the reception time of the data packet containing a clock number and of the transmission time of the associated time request through the associated clock filter 3.sub.1 or respectively 3.sub.2. The average formation represents merely an approximation. More precise results for the transmission time are obtained by implementing several time requests to the associated reference-clock sources 1.sub.1 or respectively 1.sub.2 at relatively short time intervals from the associated clock filter 3.sub.1 or respectively 3.sub.2 and taking these into consideration in an appropriately selected averaging function.

(21) Additionally, by means of an NTP-algorithm, such as has already been mentioned, the most correct clock number of a first reference-clock source 1.sub.1 or respectively 1.sub.2 at the associated transmission time is selected from the clock-cycle numbers of the associated first reference-clock sources 1.sub.1 or respectively 1.sub.2 at the associated transmission times received in each case from the individual clock filters 3.sub.1 or respectively 3.sub.2. Additionally, in the clock filters 3.sub.1 or respectively 3.sub.2 or in the NTP-algorithm, the clock-cycle number of the associated first reference-clock source 1.sub.1 or respectively 1.sub.2 at the reception time of the data packet containing a clock-cycle number is determined in the head end 7 by determining the clock-cycle number of the associated first reference-clock source 1.sub.1 or respectively 1.sub.2 received in the head end 7 at the associated transmission time around the determinable clock-cycle number of the first reference clock between each transmission time of the data packet with the clock-cycle number in the respective NTP-server 1.sub.1 or respectively 1.sub.2 and the reception time of the data packet with the clock-cycle number in the head end 7.

(22) In the next method step S20, in at least one input adapter 12.sub.1 or respectively 12.sub.2, to which a second reference-clock source 11.sub.1 or respectively 11.sub.2 is allocated in each case, the clock cycles of the second reference clock generated by the second reference-clock source 11.sub.1 or respectively 11.sub.2 are counted in a counter, which is associated with the respective input adapter 12.sub.1 or respectively 12.sub.2 and not illustrated in FIG. 4. At cyclical times, the respectively counted clock-cycle numbers of the second reference clocks generated by the individual second reference-clock sources 11.sub.1 or respectively 11.sub.2 are transmitted to the head end 7 via a second network 12, preferably a fast, high-speed network. By analogy with method step S10, the transmission times of the individual data packets, which contain clock-cycle numbers of the individual second reference-clock sources 11.sub.1 or respectively 11.sub.2, are determined in the head end 7.

(23) In the next method step S30, within the framework of a phase control 6, the clock pulse of the clock source 8 is generated on the basis of the clock-cycle numbers of the selected first reference-clock source 1.sub.1 or respectively 1.sub.2 received in each case at the individual reception times and the clock-cycle number currently counted at the associated individual reception times of the data packets with clock-cycle numbers of the first reference clock respectively in the selected first reference-clock source 1.sub.1 or respectively 1.sub.2 by controlling the difference between the individual, received clock-cycle numbers of the selected first reference-clock source 1.sub.1 or respectively 1.sub.2 and the determined clock-cycle numbers of the selected first reference-clock source 1.sub.1 or respectively 1.sub.2 to zero at the reception times of the data packets containing the associated clock-cycle numbers.

(24) In the next method step S40, second reference clocks are determined from the received clock-cycle numbers from the second reference-clock source 11.sub.1 or respectively 11.sub.2 and the determined transmission times of the data packets which contain the respective clock-cycle numbers of each reference-clock source 11.sub.1 or respectively 11.sub.2. If the second reference clocks determined are not constant, linearized second reference clocks are determined in each case via a preferably linear regression of a relatively large number of received clock numbers. While only one reference-clock source is used in each case in the first variant of the invention, several reference-clock sources 11.sub.1 or respectively 11.sub.2 are used in a second variant of the invention. A second reference clock with a comparatively high frequency accuracy, which already comes very close to the correct second reference clock illustrated in FIG. 7, is achieved by means of an averaging of the individual, linearized or non-linearized second reference clocks.

(25) The frequency oscillators of the individual reference-clock sources 11.sub.1 or respectively 11.sub.2 are preferably temperature compensated. A dependency between the relative frequency dependency of a non-temperature compensated frequency oscillator upon the ambient temperature corresponding to FIG. 5 is therefore not present. On the contrary, the relevant frequency fluctuations of the individual temperature-compensated frequency oscillators dependent upon temperature are significantly less strongly pronounced and, according to FIG. 6, fluctuate significantly less on the basis of inaccuracies, manufacturing tolerances and compensation inaccuracies of the temperature compensation. An averaging of the individual second reference clocks, which are generated by temperature-compensated frequency oscillators, leads to a significantly reduced frequency inaccuracy of the accordingly averaged second reference clock.

(26) In the next method step S50, the clock pulse generated by the phase-locked loop 6 is matched with a clock-pulse corridor, which corresponds to the second reference clock determined in the preceding method step S40 subject to the addition or deduction of an appropriately adjustable first threshold value. If the clock pulse generated by the phase-locked loop 6 is disposed outside this clock-pulse corridor, the generated clock pulse is guided to the clock-pulse limit of the clock-pulse corridor by means of a superordinate frequency-locked loop, which is disposed nearest to the clock pulse generated.

(27) In a next method step S60 to be implemented optionally in the head end 7 in an equivalent manner to the determination of the second reference clock in method step S40, a first reference clock is determined by means of a preferably linear regression from the individual clock numbers of the first reference clock received in the head end 7 and the actually accumulated clock numbers of the first reference clock at the reception times of the individual data packets, which contain the clock-cycle numbers of the first reference clock.

(28) In the final method step S70, in the case of a failure of the data-packet orientated network 9, the clock pulse of the clock source 8 is generated as the target frequency value by means of a frequency control with the first reference clock determined up to the time of the failure of the data-packet orientated network 9 using a linear regression. A clock pulse of the clock source 8 with a relatively higher precision is achieved by using the second reference clock determined in method step S40 as the target frequency value of the frequency control, because the second reference clock can also be determined during the failure of the data-packet orientated network 9 in a head end 7. As soon as the correct operation of the data-packet orientated network 9 has been restored, it is possible to switch back from the frequency control to a phase control for the generation of the clock pulse of the clock source 8.

(29) In the following section, in accordance with such embodiments for optimizing short-term stability of a clock pulse for a clock source in a process computer, for example in a head end of a radio station, a second example method is presented on the basis of the flowchart in FIG. 8B with reference to the corresponding system illustrated in the block-circuit diagram of FIG. 4.

(30) The first method steps S100, S110 and S120 of the second embodiment correspond to the method steps S10, S20 and S40 of the first embodiment and will therefore not be explained in greater detail at this point.

(31) In the next method step S130, the clock pulse of the clock source 8 is determined in a phase-locked loop, in which the phase difference between the individual received clock numbers of the first reference clock and the clock numbers of the first reference clock determined in the head end 7 at the reception times of the individual data packets, which in each case contain clock numbers of the first reference clock, are corrected in the head end 7.

(32) In the final method step S140, which is implemented in parallel time with method step S130, the frequency of the voltage-controlled frequency oscillator in the phase control, with which the individual received clock numbers of the first reference clock in the determined clock numbers of the first reference clock at the reception times of the data packets with clock numbers of the first reference clock and therefore the clock pulse generated in the clock source 8 are controlled to the first reference clock, is limited, within the phase control, to a frequency corridor, which is adjusted through the determined second reference clock, subject to the addition or deduction of an adjustable second threshold value.

(33) Optionally, the method steps S60 and S70 provided in the first embodiment can be implemented following method step S140 in the second embodiment.

(34) In the following section, in accordance with such embodiments for optimizing short-term stability of a clock pulse for a clock source in a process computer, for example in a head end of a radio station, a third example method is presented on the basis of the flow chart in FIG. 8C with reference to the corresponding system illustrated in the block-circuit diagram of FIG. 4.

(35) The method steps S200, S210, S220, S230 of the third embodiment correspond to the method steps S10, S20, S30 and S40 of the first embodiment.

(36) In the final method step S240, the rate, with which the individual clock numbers of the first reference clock are called from the head end 7 by the individual NTP-servers 1.sub.1 or respectively 1.sub.2 and their associated first reference-clock sources 2.sub.1 or respectively 2.sub.2 is increased as soon as the difference between the generated clock pulse of the clock source 8 and the determined second reference clock exceeds an adjustable third threshold value.

(37) The invention is not restricted to the embodiments presented. All combinations of the features claimed in the claims, of the features disclosed in the description and the features illustrated in the drawings are also covered by the invention.