Electronic circuit arrangement for receiving low frequency electro-magnetic waves with an adjustable attenuator element

Abstract

An electronic circuit arrangement for receiving low-frequency electromagnetic waves is proposed, having an inductor (L) acting as an antenna for generating a received signal, having a first receiver (2), connected to the inductor (L), for decoding a first component of the received signal and having a second receiver (3), connected to the inductor (L), for decoding a second component of the received signal, wherein at least the second receiver (3) is connected to the inductor (L) via an attenuator element (4) having adjustable attenuation, wherein at least one adjustment signal generation circuit (5, 6) is provided for generating an adjustment signal corresponding to a voltage of the received signal which is fed to the attenuator element (4) for adjusting the attenuation.

Claims

1. A method for receiving and processing a wireless signal, the method comprising: receiving an encoded wireless signal at an antenna; decoding at least a first portion of the wireless signal at a first voltage range above a threshold level to generate a first component of the encoded wireless signal; attenuating at least a second portion of the wireless signal and generating an attenuated signal having a second voltage below the threshold level; decoding the attenuated signal to generate a second component of the encoded wireless signal; and switching between a standby mode and an operating mode based on the second component of the encoded wireless signal.

2. The method according to claim 1 wherein a symmetrical attenuation unit attenuates the at least second portion of the wireless signal and generates the attenuated signal.

3. The method according to claim 1 wherein the attenuation of the at least second portion of the wireless signal is performed in accordance with a plurality of voltage reduction steps within a hardware voltage divider in an attenuation unit.

4. The method according to claim 3 wherein the attenuation of the at least second portion of the wireless signal is differential.

5. The method according to claim 1 further comprising the step of rectifying the attenuated signal.

6. The method according to claim 1 further comprising the step of tapping the at least second portion of the wireless signal between capacitors within the antenna.

7. An electronic circuit comprising: an interface that receives a signal and outputs an encoded signal; a plurality of decoders coupled to receive the encoded signal, the plurality of decoders decodes the encoded signal in stages wherein at least a first portion of the encoded signal is decoded by a first stage of the plurality of decoders and a second portion of the encoded signal is decoded by a second stage of the plurality of decoders, the first and second stages of the plurality of decoders operating at different voltage levels; and an attenuator coupled to the interface, the attenuator adjusts a voltage level on one or more portions of the encoded signal relative to a voltage range.

8. The electronic circuit of claim 7 wherein the attenuator comprises a voltage divider that adjusts the voltage level on the one or more portions of the encoded signal.

9. The electronic circuit of claim 8 wherein the voltage divider is symmetrical relative to ground.

10. The electronic circuit of claim 8 wherein the voltage divider operates in a differential mode.

11. The electronic circuit of claim 7 wherein the interface receives an encoded wireless signal.

12. The electronic circuit of claim 7 further comprising a voltage sensor coupled to the interface, the voltage sensor detects a voltage level on the encoded signal.

13. The electronic circuit of claim 7 wherein the electronic circuit is located within an RFID chip.

14. The electronic circuit of claim 7 further comprising wake-up circuitry that activates the electronic circuit in response to the signal received at the interface being in a defined voltage range.

15. The electronic circuit of claim 7 further comprising wake-up circuitry that activates the electronic circuit in response to the signal having a specific bit sequence identified as a wake-up command.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention and its advantageous embodiments and further developments and their advantages are described in more detail in the following based on drawings. They show:

(2) FIG. 1 is a schematic circuit diagram of an exemplary embodiment of the electronic circuit according to the invention, and,

(3) FIG. 2 is an exemplary embodiment of the diodes of the electronic circuit from FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(4) FIG. 1 shows an exemplary embodiment of the electronic circuit 1 according to the invention that is designed for receiving low-frequency electromagnetic waves. The circuit 1 according to the invention is designed in an integrated construction, that is, as an integrated circuit, which is understood to mean that a plurality of electronic components and an associated wiring of the circuit 1 are implemented on a common substrate, also called a chip. Here, a fully integrated construction can be provided in which all electronic components of the circuit are disposed on exactly one substrate.

(5) Furthermore, the circuit 1 according to the invention is manufactured in CMOS technology, that is, a technology in which both PMOS transistors, also called p-channel metal oxide semiconductor transistors, as well as NMOS transistors, also called n-channel metal oxide semiconductor transistors, can be disposed on a common substrate.

(6) The circuit 1 according to the invention has an inductor L, acting as an antenna, that together with a capacitor C7 forms an oscillator circuit. The oscil-latior circuit can have a resonance frequency, in particular, in the range of 20 kHz to 250 kHz. Using the oscillator circuit, received electromagnetic waves can be converted into an electrical receive signal that is fed via electrical conductors directly to a first receiver 2. In the exemplary embodiment, the first receiver 2 is a passive transponder 2 that generates a response signal, depending on the input signal, that can be emitted via the inductor L. The transponder 2 can be a component of an RFID system, which provides an automatic identification, in particular, of people, as part of an access control process, for example, in a motor vehicle. In the exemplary embodiment, the RFID transponder 2 has a differential input for the received input.

(7) Furthermore, a second receiver 3 is provided that is implemented as a wake-up receiver 3. A wake-up receiver 3 is understood to be a receiver which, upon receipt of a predefined signal, switches an electronic component, for example a transmitter, from a standby mode into an operating mode. In this manner, the energy consumption of the electronic component is greatly reduced when it is not needed, that is, in particular, before receipt of the predefined signal. In this context, the predefined signal can be emitted from a so-called wake-up transmitter, where it should be received at great distances even if the transmitter has low power. Therefore, wake-up receivers 3 are typically designed for decoding receive signals that have a lower voltage than is typical in RFID transponders 2. At the same time, wake-up receivers 3 are as a rule less voltage-resistant than RFID transponders 2. For example, the voltage resistance of a wake-up receiver 3 can amount to a few hundred millivolts, whereas the voltage resistance of the RFID transponder 2 can amount to a few volts.

(8) To prevent damage to the wake-up receiver 3 by a receive signal voltage that is too high, an attenuator element 4 is provided with an adjustable attenuation. Here, an attenuator element 4 is understood to be an element which reduces, essentially independently of frequency, the voltage of the electrical receive signal that is fed to it, and so generates an attenuated receive signal that is fed to a differential input of the wake-up receiver 3. The attenuation of the attenuator element 4 specifies the level of the attenuation of the receive signal.

(9) In the exemplary embodiment, the attenuator element 4 has a symmetrical voltage divider circuit C3, C4, C5, C6, M1, M2, M3, M4 in which a first side of the inductor L is connected via a first capacitor C3, a second capacitor C4 and via a first component arrangement M3, M4 having two active electronic components M3, M4, to the ground potential, wherein a second side of the inductor L is connected via a third capacitor C5, a fourth capacitor C6 and via a second component arrangement M1, M2 having two further active electronic components M1, M2, to a ground potential. Here, the attenuated receive signal is tapped between the sides of the first capacitor C3 and the third capacitor C5 facing away from the inductor L.

(10) The voltage of the attenuated receive signal tapped between the first capacitor C3 and the second capacitor C4, as well as between the third capacitor C5 and the fourth capacitor C6, depends on the complex resistivity of the first component arrangement M3, M4 and the second component arrangement M1, M2. These complex resistivitities can be adjusted here by a first adjustment signal, which is generated by the first adjustment signal creation circuit 5, and by a second adjustment signal, which is generated by a second adjustment signal generation circuit 6, so that the voltage of the attenuated receive signal lies in a harmless range.

(11) Due to the symmetrical design, especially relative to ground, of the voltage divider C3, C4, C5, C6, M1, M2, M3, M4, which in particular can mean that the first capacitor C3 and the third capacitor C5, the second capacitor C4 and the fourth capacitor C6, as well as the first component arrangement M3, M4 and the second component arrangement M1, M2 each correspond to each other, it is possible, to lead the attenuated receive signal directly to the differential input of the second receiver 3.

(12) The active electronic components M1, M2, M3, M4 of the attenuator element 4 are implemented in this exemplary embodiment as MOS transistors M1, M2, M3, M4, in particular NMOS transistors M1, M2, M3, M4.

(13) In the exemplary embodiment, the first adjustment signal is fed to the active electronic component M3 of the first component arrangement M3, M4 and to the active electronic component M1 of the second component arrangement M1, M2.

(14) The jointly controlled active electronic components M1 and M3 form a pair of active electronic components M1, M3 for damping the receive signal in a first voltage range.

(15) In the exemplary embodiment, the second adjustment signal is fed to the active electronic component M4 of the first component arrangement M3, M4, and to the active electronic component M2 of the second component arrangement M1, M2.

(16) The jointly controlled active electronic components M2 and M4 form a second pair of active electronic components M1, M3 for additional damping of the receive signal in a second, higher voltage range.

(17) In this manner, the receive signal is attenuated by the use of two separate controllable pairs M1, M3, M2, M4 of active components M1, M3, M2, M4, whereby the voltage range, in which the voltage of the receive signal can be reduced to a permissible value, can be very large.

(18) By using two adjustment signal generation circuits 5, 6, both the first adjustment signal and a second adjustment signal can be generated so that they are optimally matched with respect to the electrical properties of the respective pairs M1, M3, M2, M4 of active elements M1, M3, M2, M4. Due to this, the adjustment accuracy of the attenuation can be improved in the entire voltage range so that both under-attenuation as well as over-attenuation can be avoided.

(19) Due to the symmetrical pairwise arrangement and control of the active components M1, M3, M2, M4 it can be attained in a simple manner that the attenuated receive signal is symmetrical with respect to the ground potential, independently of the respective adjusted attenuation.

(20) The first adjustment signal generation circuit 5 has a differential input for the receive signal, which is connected by two capacitors C1 and C2 to the half-wave rectifier circuit D5, D6, D7. The half-wave rectifier circuit D5, D6, D7 is comprised of a series connection of three diodes D5, D6, D7, wherein the capacitor C1 is connected to a first connection of diodes D6 and D7. Furthermore, the capacitor C2 is connected to a second connection of diodes D5 and D6. The first adjustment signal is tapped here at one end of the series connection D5, D6, D7, whereas the other end of the series connection D5, D6, D7 is connected to a ground potential. The voltage of the first adjustment signal is limited here with respect to ground by a voltage limiter 7.

(21) The second adjustment signal generation circuit 6 has a differential input for the receive signal that is connected directly to a full-wave rectifier circuit D1, D2, D3, D4. The full-wave rectifier circuit D5, D6, D7 is composed of four diodes D1, D2, D3, D4 which form a bridge circuit. The voltage of the rectified receive signal is smoothed by means of a capacitor C8, and is limited by means of a voltage limiter 8. The rectified receive signal is fed to the transponder 2 as a supply voltage, and to the voltage detector 9, wherein the latter generates the second adjustment signal from the rectified receive signal.

(22) FIG. 2 shows an exemplary embodiment of the diodes D1 to D7 of the electronic circuit of FIG. 1. Here, the diodes D1 to D7 are each comprised of a MOS transistor, in particular, an NMOS transistor, in which a gate is connected with low impedance to a drain so that it acts as a common bipolar diode. In this manner, the rectifier circuits D1, D2, D3, D4, D5, D6, D7 can be implemented as integrated CMOS circuits that are compact and particularly simple to produce.

REFERENCE LIST

(23) 1 Electronic Circuit Arrangement

(24) 2 First Receiver

(25) 3 Second Receiver

(26) 4 Attenuator Element

(27) 5 First Adjustment Signal Generation Circuit

(28) 6 Second Adjustment Signal Generation Circuit

(29) 7 Voltage Limiter

(30) 8 Voltage Limiter

(31) 9 Voltage Detector

(32) L Inductor

(33) C1 . . . C8 Capacitor

(34) D1 . . . D7 Diode

(35) M1 . . . M4 Active Electronic Component, NMOS Transistor d Drain Terminal

(36) g Gate Terminal

(37) s Source-Terminal

(38) Vref Reference Voltage