Neural recording system

Abstract

A neuron recording system was provided. By using the gain-boosted topology, the amplifier input impedance can be increased while simultaneously reducing the noise. The system can be configured to record local field potentials (LFPs) and neuron spikes, respectively, with low-power consumption. With the flexible digital controller module (DCM), any subset of the recording channels can be activated for recording with independent sampling rate at each channel. A wireless interface to transmit recorded neuron data and an on-chip neuron processor to perform real-time signal processing can be incorporated in the system.

Claims

1. A fully integrated neural amplifier of neural signals, comprising: (a) a first stage amplifier within a neural amplifier, said first stage amplifier configured for connection to a working electrode and a counter electrode, each said electrode connected to a direct current (DC) blocking capacitor (Cin) as input capacitor; (b) a capacitive feedback circuit within said first stage amplifier configured for setting a gain of said neural amplifier as a ratio of said input capacitor (Cin) and a feedback capacitor (Cf); and (c) a folded-cascode (FC) amplifier having an auxiliary gain stage incorporated in said first stage amplifier to increase open loop gain by using a gain booster; (d) wherein said gain booster comprises a first common-source (CS) amplifier, and a second common-source (CS) amplifier; (e) wherein said first common-source (CS) amplifier is formed by a differential pair of transistors with diode-connected load, and provides said auxiliary gain stage with additional transistors so that a first differential input is coupled to input gates of a first pair of common drain coupled transistors M.sub.1c, M.sub.1a, with a second differential input coupled to input gates of a second pair of common drain coupled transistors M.sub.1b, M.sub.1d, source connections from transistors M.sub.1c, M.sub.1d, are coupled to gates of following transistors in that same stage, while source connections from transistors M.sub.1a, M.sub.1b are output to the folded cascode stage in said second common-source (CS) amplifier in order to increase gain and reduce noise; (f) wherein the differential outputs of said first common-source (CS) amplifier are connected to gates of separate PMOS current source transistors M.sub.4a, M.sub.4b within said folded-cascode (FC) amplifier, which are used as the second common-source (CS) amplifier; (g) wherein said second common-source (CS) amplifier is embedded into a folded branch of said folded-cascode (FC) amplifier in order to minimize current consumption; (h) wherein said differential pair of transistors of said first common-source (CS) amplifier shares a same source with a differential pair of transistors of said auxiliary gain stage, but said auxiliary gain stage drains current with a different ratio than in said first common-source (CS) amplifier; and (i) wherein outputs from said auxiliary gain stage are coupled to said second common source amplifier at a complementary input stage providing it with increased pate-source voltage which increases transconductance.

2. The neural amplifier as set forth in claim 1, wherein said neural amplifier is configured for receiving neural signals as local field potentials (LFP), neural spikes, or ECoG signals.

3. The neural amplifier as set forth in claim 1, wherein said neural amplifier is integrated monolithically on a single semiconductor chip.

4. The neural amplifier as set forth in claim 1, wherein said neural amplifier does not require an external/off-chip capacitor.

5. The neural amplifier as set forth in claim 1, wherein in response to biasing input differential transistors M.sub.1a, M.sub.1b, M.sub.1c, M.sub.1d into their sub-threshold region, input-referred noise is reduced using this gain-boosting topology.

6. The neural amplifier as set forth in claim 1, wherein an input signal to said first common-source (CS) amplifier is amplified by a first current path through the differential input pair transistors M.sub.1a, M.sub.1b of the FC amplifier, and by a second current path amplified by the first common-source (CS) amplifier using transistors M.sub.1c, M.sub.1d and M.sub.5a, M.sub.5b as well as the second common-source (CS) amplifier formed by M.sub.4a, M.sub.4b and the impedance seen from transistors M.sub.4a drain.

7. The neural amplifier as set forth in claim 1: further comprising a variable gain bandpass filter coupled to an output of the first stage amplifier; wherein the variable gain bandpass filter comprises a cascade of a transconductor and a transimpedance amplifier with a load capacitor, and an RC first order high pass filter having a voltage gain determined by a product of the transductance of the transconductor and the feedback resistor of the transimpedance amplifier, whereby the variable gain can be adjusted by setting current flow in the transconductor.

8. A fully integrated neural amplifier for amplifying neural signals, comprising: (a) a first stage amplifier within a neural amplifier, said first stage amplifier configured for connection to a working electrode and a counter electrode, each said electrode connected to said first stage amplifier through a separate DC blocking capacitor (Cin), as input capacitor; (b) a capacitive feedback circuit within said first stage amplifier configured for setting a gain of said neural amplifier as a ratio of said input capacitor (Cin) and a feedback capacitor (Cf); and (c) a folded-cascode (FC) amplifier having an auxiliary gain stage incorporated in said first stage amplifier to increase open loop gain by using a gain booster comprising two common-source (CS) amplifiers, in which a first common-source (CS) amplifier is formed by a differential pair of transistors with diode-connected load, so that the differential outputs of said first common-source (CS) amplifier are connected to two gates of current source transistors which comprise a second common-source (CS) amplifier that is embedded into the folded branch of said folded-cascode (FC) amplifier for the purpose of minimizing current consumption; (d) wherein said auxiliary gain stage utilizes additional transistors so that a first differential input is coupled to input gates of a first pair of common drain coupled transistors M.sub.1c, M.sub.1a, with a second differential input coupled to input sates of a second pair of common drain coupled transistors M.sub.1b, M.sub.1d, with source connections from transistors M.sub.1c, M.sub.1d, coupled to following transistors in that same stage, while source connections from transistors M.sub.1a, M.sub.1b are output to said folded cascode amplifier in order to increase gain and reduce noise; (e) wherein the differential outputs of said first common-source (CS) amplifier are connected to gates of separate PMOS current source transistors M.sub.4a, M.sub.4b within said folded-cascode (FC) amplifier, which are used as the second common-source (CS) amplifier; (f) wherein said second common-source (CS) amplifier is embedded into a folded branch of said folded-cascode (FC) amplifier in order to minimize current consumption; (g) wherein said differential pair of transistors of said first common-source (CS) amplifier shares a same source with a differential pair of transistors of said auxiliary gain stage, but said auxiliary gain stage drains current with a different ratio than in said first common-source (CS) amplifier; (h) wherein outputs from said auxiliary gain stage are coupled to said second common source amplifier at a complementary input stage providing it with increased gate-source voltage which increases transconductance; and (i) a variable gain bandpass filter coupled to an output of said first stage amplifier, in which the variable gain bandpass filter comprises a cascade of a transconductor and a transimpedance amplifier with a load capacitor, and an RC first order high pass filter having a voltage gain determined by a product of transductance of the transconductor and the feedback resistor of the transimpedance amplifier, thus allowing variable gain to be adjusted by setting current flow in the transconductor.

9. The neural amplifier as recited in claim 8, wherein an input signal to said first common-source (CS) amplifier is amplified by a first current path through the differential input pair of FC amplifier transistors M.sub.1a, M.sub.1b, and by a second current path amplified by the first common-source (CS) amplifier using transistors M.sub.1c, M.sub.1d and M.sub.5a, M.sub.5c as well as the second common-source (CS) amplifier formed by M.sub.4a, M.sub.4b, and the impedance seen from transistor M.sub.4a drain.

10. The neural amplifier as recited in claim 8, wherein said neural amplifier is configured for receiving neural signals are local field potentials (LFP), neural spikes, or ECoG signals.

11. The neural amplifier as recited in claim 8, wherein said neural amplifier is integrated monolithically on a single semiconductor chip.

12. The neural amplifier as recited in claim 8, wherein said neural amplifier does not require an external or off-chip capacitor.

13. The neural amplifier as recited in claim 8, further comprising a pseudo-resistor (R1) in parallel with said feedback capacitor (Cf) to establish a high-pass cutoff frequency of said first stage amplifier.

14. The neural amplifier as recited in claim 8, wherein said neural amplifier is configured for use with a differential charge-redistribution successive approximation register (SAR) analog-to-digital converter (ADC) for digitizing a plurality of neuron signals.

15. The neural amplifier as recited in claim 8, wherein output from the neural amplifier is configured for coupling to a specific input of a multiplexer that is configured to receive inputs from a plurality of said neural amplifiers, with the output of the multiplexer configured for connection to the input of an analog-to-digital converter (ADC) to digitize the analog signals received from a plurality of said neural amplifiers.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

(1) FIG. 1 shows an architecture of a 64-channel recording system according an exemplary embodiment of the present invention.

(2) FIG. 2 shows a schematic of one neuron recording channel according an exemplary embodiment of the present invention.

(3) FIG. 3 shows a schematic of the gain-boosted amplifier according an exemplary embodiment of the present invention.

(4) FIG. 4 shows a schematic of analog-to-digital converter (ADC) and digital controller module (DCM) according an exemplary embodiment of the present invention.

(5) FIG. 5 shows a layout of a 64-channel recording system according an exemplary embodiment of the present invention.

(6) FIG. 6 shows a frequency response of one recording channel according an exemplary embodiment of the present invention.

(7) FIG. 7 shows a simulated input-referred noise of the neuron recording channel for local field potentials (LFPs) and spikes recording setting according an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(8) The overall system architecture is shown in FIG. 1. An exemplary embodiment of the 64-channel system includes two 32-channel recording units and a shared digital controller module (DCM). Each recording unit contains 32 recording channels, one 32-to-1 multiplexer, and an SAR ADC. Within each channel, the neuron amplifier first magnifies the infinitesimal neuron signal. A programmable gain and bandwidth filter is cascaded and configured based on the signal of interests. Buffer at each channel passes the filtered output to the multiplexer. The ADC then digitizes the signal with a sampling rate of 40 kS/s per channel and feeds the output to DCM for data serialization and performing channel-specific processing to identify multi-site components.

Circuit Design

(9) Single Recording Channel

(10) A schematic of one neuron recording channel is shown in FIG. 2. The first stage adopted an AC-coupled amplifier and provided a mid-band amplification of 39.6 dB. The high-pass cutoff frequency of this amplifier is set by the MOS-bipolar pseudo-resistor formed by M.sub.RA1-RA12 and the feedback capacitor, C.sub.f. The high-pass and low-pass cutoff frequencies of the subsequent bandpass filter can be adjusted by tuning V.sub.tune to change R.sub.HPF and by altering the value of C.sub.L, where R.sub.HPF is formed by PMOS transistors M.sub.RB1-RB11 operating in weak inversion and C.sub.L is the load capacitor of the bandpass filter. The recording channel has the capability to adjust its gain from 47 dB to 59 dB. A critical issue rising from using a sub-100 nm process is the increased gate-leakage current compared to the less advanced process. A difference of 2 in the gate oxide thickness can lead to an order of magnitude change in the gate-leakage current [5]. Therefore, in our design M.sub.RA1-RA12, M.sub.RB1-RB12, and input transistors of amplifier A.sub.1 are implemented with thick-oxide I/O transistors to reduce the leakage current, which increases the amplifier noise and lower the resistance of the pseudo-resistor.

(11) Gain-Boosted Amplifier

(12) The mid-band gain of the neuron amplifier can be approximated as

(13) $\begin{array}{cc}\frac{V_{\mathrm{out}}}{V_{\mathrm{in}}}\frac{C_{\mathrm{in}}}{\frac{C_{\mathrm{in}}+C_f+C_{\mathrm{par}}}{A_1}+C_f}& \left(4\right)\end{array}$
where C.sub.par and A.sub.1 are the parasitic capacitance of the input transistors and the open-loop gain of the amplifier, respectively. Input capacitance (C.sub.in) is expected to be small, i.e. in the range of several pF, to achieve high input impedance of tens of Mega ohms, while feedback capacitance (C.sub.f) must also be reduced to achieve a reasonable gain, for example 40 dB. Though gain error is acceptable for neuron amplifier, a high open-loop gain is still desired to suppress the parasitic effect resulting from large size input transistor and capacitors. However, a high gain is difficult to achieve under the constraint of low supply voltage of 1.2V and power limitation.

(14) As shown in FIG. 3, we designed a gain-boosted folded-cascode amplifier to enhance amplifier's open-loop gain while simultaneously reducing the input-referred noise. For the biasing condition of the amplifier only a small fraction of overall current is flowing into the folded branch of M.sub.3-M.sub.4 reducing its noise contribution. Nonetheless under 1.2V supply voltage, it is impractical in our design to add a source degenerated resistor to lower the noise from M.sub.2. We utilized the fraction of current taken from M.sub.2 to build an auxiliary gain stage formed by M.sub.1c-d and M.sub.5a-b. The additional gain stage enhanced the gain of the amplifier to 1+(21)g.sub.m4/g.sub.m5) times and simultaneously reduced the noise from M.sub.2. By biasing the input differential transistor M.sub.1 into sub-threshold region, the input-referred noise of the amplifier can be derived as equation 2 (see summary). Equation 2 demonstrates the input-referred noise can be reduced by using the gain-boosted topology. Note that g.sub.m2 and g.sub.m4 in equation 2 are small due to the reduced current flowing through. The value of C.sub.in and C.sub.f is chosen as 5 pF and 50 fF for input impedance, noise, and power tradeoff.

(15) Variable Gain Bandpass Filter (BPF)

(16) The variable gain BPF aims to provide independent tuning capabilities of gain and bandwidth in one single stage to reduce the power consumption. This filter is composed of a cascade of a transconductor and a transimpedance amplifier with a load capacitor, and an RC first order high pass filter as shown in FIG. 2. The voltage gain of the filter is decided by the product of transductance GM and R.sub.f, which is the feedback resistor of the transimpedance amplifier. Thus, the gain can be adjusted by setting the current flowing in the transconductor. The variable gain bandpass can provide 7 dB-19 dB gain within a given bandwidth.

(17) Neuron Signal Digitization

(18) A differential charge-redistribution SAR ADC is designed to digitize 64-channel neuron signals. The ADC architecture has unit capacitance of 20 fF. An ADC controller and a multiplexer controller are incorporated in the DCM. A 32:1 multiplexer is placed in front of each ADC to select the channel for sampling. Although using a 5-bit counter to sequentially loop from channel 1 to 32 is straightforward, it may not be the most desirable method in all circumstances. For example, not all of the channels have proper input to be sampled at any time, and the user might only be interested in a subset of channels. Therefore, a channel-of-interest feature is implemented in the multiplexer controller. This enables the user to choose an arbitrary subset of channels, and turn off the rest in order to save power. Some of the channels can even have a higher sampling frequency than others.

(19) FIG. 4 shows an example of the architecture of this multiplexer controller. A 335 register file is employed to store the sampling channel indices as well as the number of channels that will be used. To enable a subset of four specific channels, say ch1, ch10, ch19, and ch28, the register file should be filled with 1, 10, 19, and 28 in the first four entries, and 3 in the last entry. The 5-bit counter will loop from 0-3, thus the desired channel indices will be sent to the channel multiplexer sequentially to enable these channels, and all other channels will not be sampled. If the third entry in the previous example is replaced by ch1, then ch1 will be sampled when the 5-bit counter is either 0 or 2, so it has twice the sampling frequency of ch10 and ch28. Thus, a channel can be filled into multiple entries in the register file to achieve a sampling frequency up to 16 times higher than others.

(20) A programmable 20-bit clock divider is implemented in the ADC controller and serves two purposes: to dissociate the sampling frequency and the oscillator frequency; to provide a flexible sampling frequency setting for each ADC. There are two ADCs in this system, so a high frequency oscillator is required for data stream handling. The clock divider can generate appropriate clock frequency for ADC operation no matter what frequency the oscillator is. In addition, since the channel-of-interest feature allows the user to enable a subset of channels, the accumulated frequency is lower in this mode. Thus, the clock divider can be used to set the accumulated sample frequency for each individual ADC based on the number of activated channels and the desired sample frequency per channel.

Simulation Results

(21) An exemplary 64-channel neuron recording system was designed and under fabrication in TSMC 65 nm CMOS process. The entire system is operated and simulated under 1.2V supply while consuming 40 W per channel. Note that only 6 W is consumed by the neuron recording amplifier and BPF. The chip layout occupies an area of 34 mm.sup.2, as shown in FIG. 5. The exemplary layout and power consumption are not optimized for testing purpose.

(22) FIG. 6 shows the frequency responses of one neuron recording channel. For recording LFPs, the system exhibits a programmable gain from 47 dB to 59 dB within the bandwidth from 0.5 Hz to 500 Hz. While with the immediate setting for spike recording, the system provides variable gain from 46.5 dB to 58.5 dB from 300 Hz 12 kHz.

(23) Note that the gain of spike recording is slightly lower than that of LFPs because of smaller R.sub.HPF value, which lowers the overall output impedance of neuron amplifier. The simulated input-referred noise for both configurations of LFPs and spikes recording is shown in FIG. 7. For LFPs recording, 1/f noise still dominates and thus it is difficult to distinguish the thermal noise level. The overall input-referred noise for both recording settings are 2 V.sub.rms (integrating from 0.1 Hz to 5 kHz) and 3.8 V.sub.rms (integrating from 30 Hz to 100 kHz) under 47 dB gain configuration. Note that the noise integrating bandwidth here is much larger than the signal bandwidth. Since the popular NEF metric [3] only concerns the current of the amplifier, it cannot reflect the power efficiency. Thus we compared both NEF and the modified metric [10]

(24) $\begin{array}{cc}{\mathrm{NEF}}^2*\mathrm{VDD}=\stackrel{\_}{v_{\mathrm{rms},\mathrm{in}}^2}\left(\frac{2P}{*\mathrm{kT}/q*4\mathrm{kT}*\mathrm{BW}}\right)& \left(5\right)\end{array}$
where P is the power consumption of the amplifier and BW is the signal bandwidth.

(25) The performance of the neuron recording system and comparison with other works is summarized in Table 1. The recording system has high input impedance of 31.8 Mohm at 1 kHz to mitigate the inevitable signal attenuation at the electrode-amplifier interface. The recording amplifier with bandpass filter presents the lowest NEF.sup.2*VDD product. An ADC with a flexible sampling rate for individual channels further gives the user more flexibility to monitor the neuron signal of interests. The overall power consumption of the entire system is 2.56 mW at a system clock rate of 23 MHz.

(26) TABLE-US-00001 TABLE I PERFORMANCE SUMMARY AND COMPARISON Reference [3] [8] [9] This Work Technology 0.5 m 0.5 m 0.18 m 65 nm CMOS CMOS CMOS CMOS No. of 1 16 16 64 channels Supply 2.8 3.3 1.8 1.2 voltage (V) Mid-band 40.9 39.6 70 47~59 gain (dB) High-cutoff 0.392~295 0.2~94 100 0.5~0.3k freq.(Hz) Low-cutoff 45~5.32k 140~8.2k 9 . . . 2k 500, 12k freq. (Hz) Input 3.06 1.94 5.4 3.8*.sup.1, 2.0*.sup.2 referred noise (V.sub.rms) Input 11.38 7.9 31.8 impedance @ 1 kHz (Mohm) Power 7.56 26.4 8.6 6 consumption of amplifier (W) NEF 2.37 2.9 4.9 .sup.3.sup.3 NEF.sup.2*VDD 15.7 27.7 43.2 10.8 ADC 16k or 500 30k 4k~40k sampling rate/per channel Resolution 7~12 8 9 (bits) Overall 1.8 0.68 2.56 power consump- tion (mW) .sup.1with noise integrating bandwidth of 30 Hz to 100 kHz .sup.2with noise integrating bandwidth of 0.5 Hz to 5 kHz .sup.3for spike recording