Optical receiver to enhance dynamic range thereof

Abstract

An optical receiver with an expanded dynamic range for an input current is disclosed. The optical receiver includes a photodiode to generate a photocurrent, a trans-impedance amplifier (TIA) to convert the photocurrent into a voltage signal, a dummy TIA with a same arrangement as that of the TIA to generate a reference, a differential amplifier to amplify a difference between the voltage signal and the reference, a current source to extract a portion of the photocurrent, and a level detector to detect an average photocurrent and adjust the reference based on the average photocurrent.

Claims

1. An optical receiver to receive an optical signal, comprising: a photodiode to generate a photocurrent corresponding to the received optical signal; a first trans-impedance amplifier (TIA) to convert the photocurrent into a voltage signal, a second TIA having a same arrangement as an arrangement of the first TIA, the second TIA outputting a reference; a differential amplifier to amplify a difference between the voltage signal and the reference, the differential amplifier outputting two outputs complementary to each other; an offset canceller to extract a portion of the photocurrent based on the outputs of the differential amplifier; and a level detector to detect an average of the photocurrent, the level detector outputting a control current to the second TIA to vary the reference, wherein the first TIA and the second TIA each have a first stage amplifier including a first bipolar transistor and a second stage amplifier including a second bipolar transistor, the second stage amplifiers of the first TIA and the second TIA respectively outputting the voltage signal and the reference, wherein the second TIA receives the control current from the level detector, the control current varying a current flowing in the second stage amplifier of the second TIA, wherein the second stage amplifier of the second TIA includes a load resistor, the second bipolar transistor, and an emitter resistor connected in series between a power supply and ground, the reference being output as a voltage drop caused in the load resistor by a collector current flowing in the second stage amplifier of the second TIA, and wherein the control current is provided to the emitter resistor to decrease the collector current in the second stage amplifier of the second TIA.

2. The optical receiver of claim 1, wherein the level detector includes a current mirror circuit reflecting the photocurrent flowing therein as a source current for the control current flowing therein as a mirror current.

3. An optical receiver to receive an optical signal, comprising: a photodiode to generate a photocurrent corresponding to the received optical signal; a first trans-impedance amplifier (TIA) to convert the photocurrent into a voltage signal, a second TIA having a same arrangement as an arrangement of the first TIA, the second TIA outputting a reference; a differential amplifier to amplify a difference between the voltage signal and the reference, the differential amplifier outputting two outputs complementary to each other; an offset canceller to extract a portion of the photocurrent based on the outputs of the differential amplifier; and a level detector to detect an average of the photocurrent, the level detector outputting a control current to the second TIA to vary the reference, wherein the first TIA and the second TIA each have resistors and transistors, the resistors in the second TIA having resistances greater than resistances of the resistors in the first TIA by a size factor m, the transistors in the second TIA having a size of 1/m of a size of the transistors in the first TIA, and wherein the second TIA has a power consumption smaller than a power consumption of the first TIA.

4. The optical receiver of claim 3, wherein the level detector includes a current mirror circuit reflecting the photocurrent flowing therein as a source current for the control current flowing therein as a mirror current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The foregoing and other purposes, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

(2) FIG. 1 shows a functional block diagram of an optical receiver according to an embodiment of the invention;

(3) FIG. 2 is a circuit diagram of a level detector;

(4) FIG. 3 is a circuit diagram of a modified level detector;

(5) FIG. 4 is a circuit diagram of a TIA;

(6) FIG. 3 is a circuit diagram of a dummy TIA; and

(7) FIG. 6A shows time behaviors of, from the top to the bottom, the photocurrent I.sub.PD and the cancelling current I.sub.AOC, the feedback current I.sub.F, the emitter levels, V.sub.E and V.sub.Ed, and fee output voltages, V.sub.OUT and V.sub.OUTd, respectively, for a small optical power, FIG. 6B shows time behaviors for a large optical power in a conventional circuit, and FIG. 6C shows time behaviors thereof for a large optical power in the present embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(8) Next, some embodiments according to the present application will be described in detail as referring to accompanying drawings. In the description of the drawings, numerals or symbols same with or similar to each other will refer to elements same with or similar to each other without duplicated explanations.

(9) FIG. 1 is a functional block diagram of an optical receiver according to an embodiment of the present invention. The optical receiver 1 in FIG. 1, which is applicable to the optical communication system, receives an optical signal O.sub.in from a transmitting medium, which is not illustrated in figures but it is typically an optical fiber, and converts thus received optical signal O.sub.in into an electrical signal.

(10) The optical receiver 1 includes a photodiode (PD) 3 to convert the received optical O.sub.in into a photocurrent; a trans-impedance amplifier (TIA) 5; another TIA 7, which is called as a dummy TIA in the present embodiment; first and second differential amplifiers, 9 and 11; an automatic offset canceller 13; a current source 15; and a level detector 17.

(11) The TIA 5 couples with the anode of the PD 3 and converts the photocurrent I.sub.PD into a voltage signal V.sub.OUT. The dummy TIA 7 couples with the cathode of the PD 3 through, a capacitor 19 whose capacitance is equivalent to the capacitance of the PD 3. The capacitance of the PD 3 is primarily derived from the junction capacitance of the PD 3. The dummy TIA 7 has an arrangement same with those of the TIA 5; that is, the circuit elements and the circuit configuration of the dummy TIA 7 is the same with those of the TIA 5. The dummy TIA 7 generates a reference V.sub.OUTd for converting the voltage signal V.sub.OUT of the single-phase configuration into two signals each having respective phases complementary to the other, namely, the dual-phase configuration.

(12) The first differential amplifier 9 receives the voltage signal V.sub.OUT in the non-inverting input and the reference V.sub.OUTd the inverting input thereof. The differential amplifier 9 generates two signals complementary to each other, that is, two signals having magnitude substantially same with the other but the opposite phases. The second differential amplifier 11 provided in downstream of the first differential amplifier 9 further amplifies the outputs of the first differential amplifier 9 to preset amplitude as maintaining the relation of the complementary phase.

(13) The offset canceller 13, which receives two outputs of the first differential amplifier 9, generates a control signal provided to the current source 15 such that a difference of DC components or respective averages of two outputs of the first differential amplifier 9 is compensated, or eliminated. The current source 15, which is a variable current source comprised of, for instance, a bipolar transistor and/or field effect transistor (FET), extracts a portion I.sub.AOC of the photocurrent I.sub.PD to be provided to the TIA 5 depending on the control signal from the offset canceller 13. Specifically, the transistor is connected in collector thereof to the anode of the PD 3 and the input of the TIA 5 to flow the cancelling current I.sub.AOC from the photocurrent I.sub.PD. When the photocurrent I.sub.PD contains a large DC component, the cancelling current I.sub.AOC becomes large by the feedback function of the offset canceller 13 and the current source 15. On the other hand, when the photocurrent I.sub.PD contains a smaller DC component, the cancelling current I.sub.AOC reduces.

(14) The level detector 17, which is coupled with the cathode of the PD 3 slid the bias input of the dummy TIA 7, supplies a reverse bias to the PD 3 and monitors an average optical power detected by the PD 3, which is reflected in the average of the photocurrent I.sub.PD. The capacitor 21 connected between the input of the level detector 17 and the ground bypasses AC components of the photocurrent I.sub.PD. The level detector 17 outputs a control current I.sub.adj reflecting the average of the photocurrent I.sub.PD to the dummy TIA 7.

(15) FIG. 2 is a circuit diagram of an example of the level detector 17. The exemplary level detector 17 shown in FIG. 2 includes two FETs, 23A and 23B, exactly, a current mirror circuit formed by two p-type FETs, 23A and 23B. Specifically two FETs, 23A and 23B, are commonly connected in the gates thereof, and also commonly connected in the sources thereof to the power supply Vcc2. The collector of the FET 23A is short-circuited to the gate thereof and connected to the output terminal 25. The collector of the other FET 23B is connected to the other output terminal 27. Coupling the output terminal 25 with the cathode of the PD 3, the photocurrent I.sub.PD flows out from the output terminal 25, and the control current I.sub.adj, which is the mirror current reflecting the photocurrent I.sub.PD, flows out from the other output terminal 27. When two transistors, 23A and 23B, have sizes substantially same with the other, the mirror current I.sub.adj becomes substantially equal to the source current I.sub.PD by the current mirror circuit shown in FIG. 2. The control current I.sub.adj is provided to the dummy TIA 7 to adjust the reference V.sub.OUTd, which is output from the dummy TIA 7 to the first differential amplifier 9 as the reference level for converting a single phase signal into a differential signal. Thus, the reference V.sub.OUTd may be adjusted depending on the average optical power, equivalently, the average photocurrent I.sub.PD.

(16) FIG. 3 is a circuit diagram of another example of the level detector 17A that includes an operational amplifier 29, an FET 31, and two resistors, 33 and 35. The resistor 33 is put between the output terminal 25 and the power supply Vcc2 to cause a voltage drop by the photocurrent I.sub.PD flowing therein. The other resistor 35 is connected between the inverting input of the amplifier 29 and the power supply 35 to cause a voltage drop by the control current I.sub.adj flowing therein. The FET 31, which may be a p-type FET, is connected between the inverting input of the amplifier 29 and the other output terminal 27. Because the operational amplifier 29 operates or generates an output thereof so as to make two input levels, the non-inverting input connected to the resistor 33 and the inverting input connected to the resistor 35, equal to each other, the control current I.sub.adj is set to be substantially equal to the photocurrent I.sub.PD when two resistors have the same resistance. Thus, the control current I.sub.adj may fully reflect the photocurrent I.sub.PD.

(17) Next, details of the TIA 5 and the dummy TIA 7 will be described. FIG. 4 is a circuit diagram of the TIA 5, while, FIG. 5 is a circuit diagram of the dummy TIA 7.

(18) First referring to FIG. 4, the TIA 5 is a type of the two-stage amplifier including two transistors, 37A and 37B. The first transistor 37A is the common emitter configuration where the collector is biased by the power supply Vcc1 through a load resistor 39A, the emitter is directly grounded and the base is coupled with the input terminal 41 to receive the input Vin. The second transistor 37B is also the common emitter configuration where the collector is biased by another power supply Vcc2 through a load resistor 39B, the base is coupled with the collector of the first transistor 37A, and the emitter is grounded through an emitter resistor 43. The output terminal 47 is coupled with the collector of the second transistor 37B to provide an output V.sub.OUT. In addition, the emitter of the second transistor 37B is fed back to the base of the first transistor 37A through a feedback resistor 45.

(19) Details of the dummy TIA 7 will be described as referring to FIG. 5. The dummy TIA 7, as shown in FIG. 5, has a circuit diagram substantially same with that of the TIA 5 except for an additional input terminal 149 to receive the control current I.sub.adj from the level detector 17. In the dummy TIA 7, the resistors, 139A to 145, may have the resistance same with those, 39A to 45, in the TIA 5, or increased from those, 39A to 45, in the TIA 5 by the same ratio. Specifically, when the resistors 139A to 145, have the resistance m (m>1) times greater than those of the resistors, 39A to 45, in the TIA 5, the sizes of the transistors, 137A and 137B, are necessary to be reduced by 1/m because the current flowing from the power supply Vcc2 to the ground becomes smaller. The parameter m is often called as the size factor. Then, the power consumed by the dummy TIA 7 may be reduced.

(20) The operation of the TIA 5 and the dummy TIA 7 will be described. In the dummy TIA 7, substantially no input current I.sub.F is provided from the input terminal 141 because the input terminal 141 couples with the PD 3 through the coupling capacitor 19, and the PD 3 in the cathode thereof is grounded in the AC mode. The DC component appearing in the cathode of the PD 3 is fully isolated by the coupling capacitor 19. When the transistor 137A has a current amplification factor large enough, a voltage drop induced in the feedback resistor 145 by the base current of the transistor 137A becomes small enough, which means that the output level is equal to the input level and the control current. I.sub.adj provided in the terminal 149 fully flows in the emitter resistor 143.

(21) That is, the current flowing in the emitter resistor 143 is given by:
I.sub.Ed2=I.sub.Ed+I.sub.adj,
where I.sub.Ed2 and I.sub.Ed are the current flowing in the emitter resistor 143 and the emitter current flowing out from the second transistor 137B. Setting the resistance of the resistor 143 and the resistor 43 in the TIA 5 to R.sub.Ed2 and R.sub.E2, respectively; and the size ratio of the dummy TIA 7 against the TIA 5 to m (m>1); then, the emitter current I.sub.Ed is given by:
I.sub.Ed=V.sub.Ed/R.sub.Ed2I.sub.adj=V.sub.ind/(mR.sub.E2)I.sub.adj.
Thus, the emitter current I.sub.Ed may be adjusted by the control current I.sub.adj provided from the level detector 17.

(22) Because the emitter current I.sub.Ed is substantially equal to the collector current I.sub.Cd2, the output level V.sub.OUTd may be expressed as:
V.sub.OUTdVcc2mR.sub.C2I.sub.Ed
=Vcc2R.sub.C2V.sub.ind/R.sub.E2+mR.sub.C2I.sub.adj,
where R.sub.C2 and mR.sub.C2 are the resistance of the collector load 39B of the TIA 5 and that 139B of the dummy TIA 7, respectively. Specifically, the control current I.sub.adj is proportional to the average of the optical input power, or the photocurrent I.sub.PD; accordingly, as increasing the average of the optical input power, the emitter current I.sub.Ed of the transistor 137B decreases and the collector level thereof, which is the output V.sub.OUTd of the dummy TIA 7, increases the level.

(23) On the other hand for the TIA 5, a substantial current I.sub.F appears in the input terminal 41 because the TIA 5 is coupled with the PD 3 in DC mode. Then, the emitter current I.sub.E of the transistor 37B becomes:
I.sub.E=(V.sub.inI.sub.FR.sub.F)/R.sub.E2I.sub.F,
where R.sub.F is resistance of the resistor 45. Then, the output level V.sub.OUT of the transistor 37B is:
V.sub.OUTVcc2R.sub.C2I.sub.E
=Vcc2R.sub.C2(V.sub.inI.sub.FR.sub.F)/R.sub.E2+R.sub.C2I.sub.P.

(24) The offset canceler 13 and the current source 15 operate such that two output levels, V.sub.OUT and V.sub.OUTd, becomes equal to each other, or a difference between two levels, V=|V.sub.OUTV.sub.OUTd|, disappears. Moreover, because two input levels, V.sub.in and V.sub.ind, are substantially equal to each other, V.sub.inV.sub.ind, and the input current I.sub.F for the TIA 5 is subtracted from the photocurrent I.sub.PD by the cancelling current I.sub.AOC flowing into the transistor 15, namely, I.sub.F=I.sub.PDI.sub.AOC; cancelling current I.sub.AOC is given by:
I.sub.AOC=I.sub.PD(I.sub.adjmR.sub.E2)/(R.sub.E2+R.sub.F).
In other words, the offset canceller 13 sets the cancelling current I.sub.AOC defined by the equation above described. Thus, the offset canceller 13 extracts a portion I.sub.AOC of the photocurrent I.sub.PD in a whole range of the input optical power, which means that the offset canceller 13 may cancel the offset appearing the output of the differential amplifier 9. Because the control current I.sub.adj is practically proportional to the average input power, the cancelling current I.sub.AOC becomes substantially equal to the photocurrent I.sub.PD, I.sub.AOCI.sub.PD, when the average input power is smaller, which means that, substantially no DC current flows into the TIA 5 for small input power. On the other hand, when the average input power becomes substantial, the DC current corresponding to the second term in the above equation flows into the TIA 5.

(25) Thus, according to the optical receiver 1, the TIA 5 converts the photocurrent I.sub.PD into the voltage signal V.sub.OUT, while, the dummy TIA 7 provides the reference V.sub.OUTd to convert the voltage signal V.sub.OUT of the single phase into the differential signal, where the reference V.sub.OUTd corresponds to, or proportional to, the average of the input optical power. Because the reference V.sub.OUTd fully reflects the average input power, the optical receiver 1 may operate in a whole range of the optical input power without implementing with an integrating filter to pass only low-frequency (LF) components of the voltage signal V.sub.OUT, where the integrating filter is often provided between the TIA 5 and the differential amplifier 9 to generate an average of the voltage signal V.sub.OUT. Moreover, the optical receiver 1 provides the offset canceller 13 to cancel the output offset of the differential amplifier 9. The offset canceller 13 operates to compensate the output offset caused by an offset between two output signals, V.sub.OUT and V.sub.OUTd. Although the output V.sub.OUTd of the dummy TIA 7 corresponds to the average of the voltage signal V.sub.OUT, two TIAs, 5 and 7, independently operate and inevitably cause an offset between respective outputs, which finally results in the output offset of the differential amplifier 9. The offset canceller 13 may effectively cancel the output offset of the differential amplifier 9 by extracting a portion I.sub.AOC of the photocurrent I.sub.PD.

(26) Two TIAs, 5 and 7, have the configuration of the two stage transistors, and the dummy TIA 7, depending on the average of the photocurrent I.sub.PD, decreases the output current of the second stage transistor to increase the reference level V.sub.OUTd. Thus, the increase of the reference level V.sub.OUTd for a large photocurrent I.sub.PD may effectively prevent the second stage transistor 37B in the TIA 5 from being saturated, which improves the overload characteristic, namely, the performance of a large input power, in particular, the frequency response for a large power. Moreover, the power dissipation of the dummy TIA 7 is set to be small enough by setting the size factor m.

(27) The operation of the optical receiver 1 of the present embodiment will be further described as referring to FIGS. 6A to 6C which show time behaviors of respective signals. That is, FIG. 6A shows time behaviors of, from the top to the bottom, the photocurrent I.sub.PD and the cancelling current I.sub.AOC, the feedback current I.sub.F (the current input to the TIA 5), the emitter voltage, V.sub.E and V.sub.Ed, and the output voltages. V.sub.OUT and V.sub.OUTd, respectively, each for smaller input power; FIG. 6B shows time behaviors of them at larger input power for a conventional optical receiver; and FIG. 6C shows time behaviors of them for the larger input power of the present embodiment.

(28) For the smaller input power, as shown in FIG. 6A, the offset canceller 13 operates such that the cancelling current I.sub.AOC becomes substantially equal to the average of the photocurrent I.sub.PD. Then, the average feedback current I.sub.P flowing in the feedback resistor 45 in the TIA 5 becomes zero, the emitter level V.sub.Ed of the dummy TIA 7 becomes equal to the average of the emitter level V.sub.E of the TIA 5, and the output level V.sub.OUTd of the dummy TIA 7 also becomes equal to the output V.sub.OUT of the TIA 5. Thus, the mono-phase to the dual-phase conversion by the differential amplifier 9 may be adequately carried out. Assuming the resistance of the feedback resistor 45 and the photocurrent I.sub.PD are 500 and 100 Ap-p, respectively, namely, the average of 50 A, the emitter shows the amplitude V.sub.E of 100 mVp-p. Because the input level Vin is generally around 0.9 V, the average of the emitter level V.sub.E also becomes around 0.9 V. Setting the power supply Vcc2 and balancing the resistance of two resistors, R.sub.C2=R.sub.E2, the output V.sub.OUT becomes 2.1 V which is lower from the power supply Vcc2 by 0.9 V. Those conditions are often appearing in a practical operation of the two-stage amplifier. In such a condition, the second-stage transistor 37B may be biased over 0.2 V in the base-collector junction V.sub.BC2, which operates the second-stage transistor 37B as an amplifier.

(29) FIG. 6B corresponds to a conventional optical receiver that receives large optical power, where the conventional optical receiver is assumed to have no level detector 17. In the conventional optical receiver, the photocurrent I.sub.PD increases as the average input power increases. The offset canceller 13 operates such that the cancelling current I.sub.AOC becomes equal to the average of the photocurrent I.sub.PD, which results in a condition where the second-stage transistor 37B does not operate as an amplifier, specifically, the base-collector bias V.sub.BC2 thereof is not secured. In a case where the photocurrent I.sub.PD is 2 mAp-p (the average of 1 mA), the amplitude of the emitter level V.sub.E becomes 1.0 Vp-p and the output voltage V.sub.OUT also shows fee amplitude of 1.0 Vp-p with the average of 2.1 V. While, the base of the second-stage transistor 37B swings, with respect to the emitter bias V.sub.E thereof, in a same phase but slightly greater amplitude around the level higher by a forward junction voltage (0.80.9 V), that is, the base of the second-stage transistor 37B swings about 1.0 Vp-p around 1.8 V. Under such a condition, the base-collector bias V.sub.BC2 of the second-stage transistor 37B becomes 0.7V in the worst condition, which is unable for the second stage transistor 37B to operate as an amplifier. The base-collector junction is forwardly biased when the optical signal is off, namely, in the low level, which degrades the performance, in particular, the operational speed of the transistor and extremely distorts the output of the TIA 5.

(30) FIG. 6C corresponds to the optical receiver 1 of the present embodiment feat provides the level detector 17. The level detector 17 adjusts the current I.sub.adj provided to the dummy TIA 7 to suppress the cancelling current I.sub.AOC smaller than the average of the photocurrent I.sub.PD and the substantial current I.sub.F flows in the feedback resistor 45 to lower the emitter level V.sub.E compared with the conventional circuit. Then, the average of the output V.sub.OUT rises to secure the amplifying operation of the second-stage transistor 37B. Specifically, under the conditions same with those corresponding to FIG. 6B, the level detector 17 provides the control current I.sub.adj, whose magnitude is 3/10 of the photocurrent I.sub.PD, to the dummy TIA 7, which rises the output V.sub.OUTd by 0.3 V and lowers the emitter level V.sub.Ed by 0.3 V. Because the offset canceller 13 operates such that two outputs, V.sub.OUTd and V.sub.OUT, becomes equal, the increase of the reference V.sub.OUTd by 0.3 V results in the increase of the output V.sub.OUT by 0.3 V and the decrease of the emitter level V.sub.E by 0.3 V, which, also decreases of the collector level V.sub.C1 of the first-stage transistor 37A or the base level of the second-stage transistor 37B. Accordingly, the base-collector bias V.sub.BC2 of the second-stage transistor 37B becomes 0.1 V even in the worst case thereof, which secures the high-speed operation of the second-stage transistor 37B.

(31) The control current shows the same function with that described above even when the input power is small. However, leaving the cancelling current I.sub.AOC in substantial when the input power is small, the minimum receiving sensitivity degrades because the cancelling current I.sub.AOC causes shot noise in the current source 15 and the first stage transistor 37A. However, the present optical receiver decreases the cancelling current I.sub.AOC in the small input power; accordingly, the shot noise due to the cancelling current I.sub.AOC is substantially ignorable. When the input optical power becomes large, the photocurrent I.sub.PD also increases to compensate the increase of the cancelling current I.sub.AOC and the shot noise is also ignorable.

(32) While particular embodiments of the present invention have been described herein for purposes of illustration, many modifications and changes will become apparent to those skilled in the art. Accordingly, the appended claims are intended to encompass all such modifications and changes as fall within the true spirit and scope of this invention.