RFID transponder with rectifier and voltage limiter

Abstract

The present invention relates to a transponder, which comprises an antenna and a multi-stage rectifier. The antenna is connected to an input of the multi-stage rectifier having m rectifier stages, and a shunt limiter is connected to an output of the rectifier and connected to an n.sub.th stage of the multi-stage rectifier, wherein n<m.

Claims

1. A transponder, comprising: an antenna, and a multi-stage rectifier, wherein the antenna is connected to an input of the multi-stage rectifier having m rectifier stages, wherein a shunt limiter is both connected to an output of the rectifier and connected to an n.sub.th stage of the multi-stage rectifier, wherein n<m, and wherein the multi-stage rectifier has a plurality of stages m and the nth stage of the multi-stage rectifier, where n<m, is connected to the shunt limiter which is also connected to the output of the multi-stage rectifier, the multi-stage rectifier having the antenna connected to the input thereof.

2. The transponder according to claim 1, wherein the shunt limiter comprises a first transistor having a drain and a source, wherein one of the source and the drain is connected to the output of the rectifier.

3. The transponder according to claim 2, wherein the first transistor of the shunt limiter comprises a gate connected to the n.sub.th stage of the multi-stage rectifier.

4. The transponder according to claim 2, wherein shunt limiter comprises a first resistor connecting the other one of the drain and the source of the first transistor with ground Vss.

5. The transponder according to claim 2, wherein the shunt limiter comprises a second transistor having a drain and a source, wherein one of the drain and the source is connected to the output of the rectifier.

6. The transponder according to claim 5, wherein the second transistor comprises a gate connected to a node connected with a first resistor and with one of the source and the drain of the first transistor.

7. The transponder according to claim 5, wherein the drain of the second transistor is connected to the source of the first transistor.

8. The transponder according to claim 5, wherein the shunt limiter comprises a compensation circuit connecting the drain of one of the first and second transistors with the source of the other one of the first and the second transistors.

9. The transponder according to claim 8, wherein the compensation circuit comprises a second resistor in series with a capacitor.

10. The transponder according to claim 2, wherein the first transistor is a PMOS transistor.

11. The transponder according to claim 5, wherein the second transistor is a NMOS transistor.

12. The transponder according to claim 1, wherein each stage of the multi-stage rectifier comprises an input capacitor, wherein the input capacitors of the multiple stages are connected in parallel.

13. The transponder according to claim 1, wherein each stage of the multi-stage rectifier comprises an output capacitor.

14. The transponder according to claim 12, wherein each stage of the multi-stage rectifier comprises a rectifier arrangement comprising at least one transistor or at least one diode.

15. An electronic device comprising a transponder according to claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the invention will become apparent from the following description of non-limiting exemplary embodiments, with reference to the appended drawings, in which:

(2) FIG. 1 schematically shows a conventional transponder according to the prior art;

(3) FIG. 2 shows the assembly of a multi-stage rectifier in combination with a shunt limiter according to a first embodiment of the present invention;

(4) FIG. 3 shows a more detailed illustration of the shunt limiter according to FIG. 2;

(5) FIG. 4 shows a more detailed illustration of the multi-stage rectifier according to FIG. 2; and

(6) FIG. 5 shows another schematic implementation of a combination of a multi-stage rectifier with a shunt limiter.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

(7) In FIG. 1, a conventional transponder 1, typically implemented as an RFID transponder is shown. The transponder 1 comprises an antenna 2 that is connected to a modulator 6 and a demodulator 7. Moreover, the antenna 2 is connected to a rectifier 3 that serves to transfer a RF signal received by the antenna 2 into a DC signal in order to provide a power source for the various electronic components of the RFID transponder 1. At the output of the rectifier 3, a driving voltage V.sub.DD is provided. The output of the rectifier 3 is further connected with a limiter 4. The demodulator 7 as well as the modulator 6 are connected with a logic controller 5, which is driven by the voltage provided at the output of the rectifier 3.

(8) The RFID transponder 1 as shown in FIG. 1 further comprises a power management 8, a memory 9 as well as an oscillator 10. Power management 8, memory 9 and oscillator 10 are all connected to the logic controller. Power management 8, memory 9 and oscillator 10 are further driven by the voltage V.sub.DD obtainable at the output of the rectifier 3.

(9) In FIG. 2, the general configuration of the transponder 100 according to one embodiment of the present invention is schematically illustrated. For illustration purpose in FIG. 2, there are only shown an antenna 2, a multi-stage rectifier 103 and a shunt limiter 104. The output 21 of the multi-stage rectifier 103 provides an output voltage V.sub.DD. The output 21 is connected to the shunt limiter 104. Moreover, there is provided a rectifier tap 20 that is connected to an n.sub.th stage of the multi-stage rectifier 103. The rectifier tap 20 is also connected to the shunt limiter 104. The output 21 of the multi-stage rectifier 103 is tied to ground V.sub.SS by a capacitor 23.

(10) In FIG. 3, an exemplary embodiment of the shunt limiter 104 is provided. The shunt limiter 104 comprises a first transistor 22 and a second transistor 24. In the present embodiment, the first transistor 22 is implemented as a PMOS transistor P.sub.L while the second transistor 24 is implemented as a NMOS transistor N.sub.L. As it is illustrated in FIG. 3, the gate 22g of the first transistor 22 is connected to the rectifier tap 20 which is connected to the n.sub.th stage of the multi-stage rectifier 103. The drain 22d of the first transistor 22 is connected to the output 21 of the multi-stage rectifier V.sub.DD.

(11) A source 22s of the first transistor is connected with a node 25 and further with a first resistor 26. The source 22s of the first transistor 22 is connected to ground V.sub.SS via the first resistor 26.

(12) The second transistor 24 has a gate 24g that is connected to said node 25. Hence, the gate 24g is tied to ground V.sub.SS via the first resistor 26. The gate 24g is also connected to the source 22s of the first transistor 22. A drain 24d of the second transistor 24 is connected to the output 21 of the multi-stage rectifier 103. The drain 24d of the second transistor 24 is also connected to the drain 22d of the first transistor 22. The source 24s of the second transistor 24 is connected to ground V.sub.SS.

(13) In addition, there is provided a compensation circuit 28 comprised of a second resistor 27 and a capacitor 29 that are connected in series. Here and as shown in FIG. 3, the drain 24d of the second transistor 24 is connected to the source 22s of the first transistor 22 via said compensation circuit 28.

(14) In FIG. 4, the general architecture of a multi-stage rectifier 103 is shown in more detail. Here, only four stages of a multi-stage rectifier 103 are shown. The multi-stage rectifier 103 comprises a first stage 31, a second stage 32 and eventually further stages that are not illustrated. In a generalized view, the multi-stage rectifier 103 comprises an n.sub.th stage 33 and an m.sub.th stage 34. Here, the m.sub.th stage 34 represents the last stage of the multi-stage rectifier 103 and provides an output 21 with a rectified supply voltage V.sub.DD. The n.sub.th stage 33 represents an arbitrary stage located between the first stage 31 and the last stage 34.

(15) The input 35 of the multi-stage rectifier 103 is connected with a series of input capacitors 41, 42, 43, 44. The input capacitors 41, 42, 43, 44 of the various stages 31, 32, 33, 34, respectively are connected in parallel with the input 35 of the multi-stage rectifier 103. The input capacitors 41, 42, 43, 44 are each connected to a rectifier arrangement 61, 62, 63, 64, wherein the rectifier arrangements 61, 62, 63, 64 of the various stages 31, 32, 33, 34 are all connected in series. In the embodiment according to FIG. 4, each rectifier arrangement 61, 62, 63, 64 comprises a NMOS transistor N1, N2, Nn, Nm and a PMOS transistor P1, P2, Pn, Pm.

(16) NMOS and PMOS transistors of each rectifier arrangement 61, 62, 63, 64 are connected in series. A node connected with the source of the NMOS transistor N1 with the drain of the PMOS transistor P1 is connected to the input capacitor 41. Each rectifier stage 31, 32, 33, 34 also comprises an output capacitor 51, 52, 53, 54. Each output capacitor 51, 52, 53, 54 is connected to ground and is connected to a node located between two adjacently arranged rectifier arrangements 61, 62, 63, 64. In detail, the output capacitor 51 of the first stage 31 is connected to a node located connected to the rectifier arrangement 61 of the first stage 31 connected to the rectifier arrangement 62 of the second stage 32. Each stage 31, 32, 33, 34 is further provided with two auxiliary charge pumps 70 connected to the gate of the stage's NMOS transistor and PMOS transistor, respectively.

(17) As it is explicitly shown in FIG. 4, the n.sub.th stage 33 is provided with a rectifier tap 20 which is further connected to the gate 22g of the first transistor 22 of the shunt limiter 104.

(18) The function of the combination of the multi-stage rectifier 103 with the shunt limiter 104 is as follows. The shunt limiter 104 will begin to shunt current to ground when the voltage between the output 21 of the multi-stage rectifier 103 and the gate 22g of the first transistor 22 reaches the threshold voltage of said first transistor 22. As the gate voltage at the gate 22g increases, the current through the first transistor 22 will increase until enough voltage is built up across the first resistor 26 to turn on the second transistor 24. Once the second transistor 24 turns on, it will shunt current to ground and will thus limit the output 21 of the multi-stage rectifier 103.

(19) When the current through the first transistor 22 times the resistance of the compensation circuit 28 is equal to the threshold voltage of the second transistor 24 a full limiting will take place. Prior to this condition little or no current will be consumed in the limiter 104. This is of particular benefit in a low power RFID transponder 100 as the shunt limiter 104 will not degrade performance when it is not limiting. The onset of the limiter beginning to function occurs under the following condition:

(20) V.sub.rec=V.sub.thPL.Math.m/(mn), wherein V.sub.thPL is the threshold voltage of the first transistor 22, m is the total number of stages of the multi-stage rectifier 103, and n is the number of stages from the multi-stage rectifier input to the n.sub.th stage thereof being connected to the gate 22g of the first transistor 22. In a practical implementation with for instance a six stage rectifier 103, wherein the fourth stage being used and connected to the gate 22g of the first transistor 22 of the shunt limiter 104 and with a threshold voltage of the first transistor of 600 mV a limiter with a clamp voltage of 1.8 V will be provided.

(21) Then, the gain of the limiter can be expressed as follows:

(22) ((n/m).Math.gm.sub.PL.Math.R1).Math.gm.sub.NL.Math.R.sub.rect, wherein n/m is the feedback ratio of the rectifier, gm.sub.PL is the trans-conductance of the first transistor 22, R1 is the resistance of the first resistor 26, gm.sub.NL is the trans-conductance of the second transistor and R.sub.rect is the output impedance of the rectifier 103.

(23) Typically, the loop gain of the arrangement of the multi-stage rectifier 103 with the shunt limiter 104 can be configured to be in a range between 20-40 dB. But in typical implementations, it depends on the amount of current the limiter 104 is shunting as this current affects the trans-conductance of both, the first and the second transistors 22, 24. Hence, the gain increases as the shunt current increases. When compared to a simple passive limiter such as a stack of diodes the presently described inventive embodiments provide numerous benefits. The combination of a multi-stage rectifier 103 with a shunt limiter 104 has a narrower range of onset of limiting. There is only one variation of a threshold voltage, whereas a stack of diodes inherently comprises multiple variations of threshold voltages. The present embodiments also have higher loop gain, which facilitates a tighter range of output voltage versus shunt current.

(24) When compared to an active limiter, typically implementing a differential amplifier scheme, there are also some advantages with the currently described configuration. The combination of a multi-stage rectifier 103 with a shunt limiter 104 does not require an explicit voltage reference, such as a band gap or an equivalent reference. This helps to reduce current and power consumption. The present combination does also not require a current source to bias any transistors. This again saves power and complexity. A further benefit arises in that the combination of the multi-stage rectifier 103 with a shunt limiter 104 does not come along with any startup issues. A typical active loop solution would require a voltage reference and/or bias currents. Both of these must be available and at the proper operation condition for the limiter to function correctly. This makes it very difficult for the limiter to start properly. The combination of the shunt limiter 104 with the multi-stage rectifier 103 does not rely on any external references and thus will start-up right away without the necessity of any calibration or tuning.

(25) In FIG. 5, another implementation of a combined multi-stage rectifier 203 with a shunt limiter 104 is illustrated. Here, the multi-stage rectifier 203 comprises a series of diode arrangements. In comparison to the configuration according to FIG. 4, the rectifier arrangements 161, 162, 163, 164, 165, 166 each comprise two diodes instead of a combination of an NMOS transistor and a PMOS transistor. In the sketch of FIG. 5 only the diodes D1, D2 of the rectifier arrangement 161 and the diodes D3, D4 of the rectifier arrangement 162 are illustrated. Apart from that, each rectifier stage also comprises an input capacitor and an output capacitor. As it is shown in FIG. 5, the fifth stage of the multi-stage rectifier 203 is connected to the shunt limiter 104.