Chip with Protection Function and Method for Producing Same

Abstract

A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Claims

1-13. (canceled)

14. A chip comprising: a varistor layer composed of zinc oxide; a multilayered electrode structure which realizes a varistor function in the varistor layer; at least two solderable or bondable external contacts on a first main surface of the varistor layer; and a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer comprises, as main constituents, oxides of Si and/or Ge, B and K, which in total comprise at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

15. The chip according to claim 14, further comprising electrical connection pads on a second main surface of the varistor layer, the electrical connection pads configured to connect an electrical component.

16. The chip according to claim 15, wherein the external contacts and the connection pads are deposited electrolytically, and wherein the external contacts and the connection pads comprise at least one of Ni, Ag and Au.

17. An arrangement comprising: a chip according to claim 15; and an electrical component, wherein the electrical component is mounted on the second main surface of the varistor layer and is electrically connected to the connection pads, and wherein the electrical component is interconnected with the electrode structure and with the external contacts.

18. The arrangement according to claim 17, wherein the electrical component is an LED.

19. The chip according to claim 14, wherein the electrode structure comprises at least 4 electrode layers arranged one above another and alternately connected to the two external contacts.

20. The chip according to claim 14, wherein the glass layer is free of ZnO and Bi.sub.2O.sub.3.

21. The chip according to claim 14, wherein the glass layer contains a filler having a better thermal conductivity than quartz.

22. The chip according to claim 21, wherein the glass layer comprises solid filler particles composed of ZrO2.

23. The chip according to claim 14, wherein the glass layer contains, as further constituents, oxides of metals selected from Li, Na, Mg, Ca, Sr and Ba.

24. The chip according to claim 23, wherein the constituents Li and Na are contained in proportions of up to, in each case, a maximum of 5% by weight, and the others up to, in each case, a maximum of 15% by weight.

25. The chip according to claim 14, wherein the chip comprises a maximum thickness of 1000 m.

26. The chip according to claim 14, wherein the chip comprises a maximum thickness of 500 m.

27. The chip according to claim 14, wherein the chip comprises a maximum thickness of 250 m.

28. A method for producing a chip, the method comprising: producing a stack by stacking green sheets composed of a ZnO one above another, the green sheets comprising a print with an electrode material; sintering the stack of green sheets thereby forming a varistor layer having a multilayered electrode structure; printing a metallization paste on a first and/or a second main surface of the varistor layer for defining external contacts and/or connection pads; printing a glass paste thereon in a structured manner such that areas provided for the external contacts and/or the connection pads remain uncovered; firing and sintering the metallization paste and the glass paste thereby producing a metallization and a structured glass layer, wherein the glass layer comprises, as main constituent, oxides of Si and/or Ge, B and K, which in total comprise at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti; and reinforcing electrolytically or electroless regions of the metallization which are provided for the external contacts and/or the connection pads and which are not covered by the glass layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The invention is explained in greater detail below on the basis of exemplary embodiments and the associated figures. The figures serve merely for illustrating the invention and are therefore not represented as true to scale. Therefore, neither absolute nor relative dimensional indications can be inferred from the figures.

[0030] In the figures:

[0031] FIG. 1 shows a simple embodiment of a chip according to the invention in schematic cross section;

[0032] FIG. 2 shows a chip having external contacts and connection pads;

[0033] FIG. 3 shows a chip having plated-through holes;

[0034] FIG. 4a shows a further embodiment of a chip;

[0035] FIG. 4b shows a variant of FIG. 4a;

[0036] FIG. 5 shows a chip with an electrical component mounted on the second main surface;

[0037] FIG. 6 shows various green sheets printed partly with electrode material, from which a varistor layer can be produced;

[0038] FIG. 7 shows a varistor layer after the green sheets have been stacked one above another and after the stack has been sintered;

[0039] FIG. 8 shows the arrangement after the application of external contacts;

[0040] FIG. 9 shows the arrangement after the application of a glass layer;

[0041] FIG. 10 shows the finished chip after the thickening of the metallization for the external contacts; and

[0042] FIGS. 11a and 11b show two possible interconnections of a chip with varistor function with an electrical component to be protected.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0043] FIG. 1 shows a simple embodiment of a chip CH. The latter has, in integrated form, a multilayered electrode structure, wherein a plurality of electrode layers ES are arranged within the varistor layer VS in an overlapping manner one above another such that they can be connected to different electrodes or different contacts. In the embodiment illustrated, the electrode layers ES are alternately assigned to a first and second external contact AK and connected to the corresponding external contact AK via a respective plated-through hole DK1, DK2. The regions of the first main surface of the varistor layer VS which are not covered by the external contact AK are covered with a glass layer GS. Accordingly, the first main surface has either a glass layer covering or a metallization structured to form an external contact AK. The varistor layer comprising zinc oxide itself does not emerge at the first main surface. The second main surface of the varistor layer VS opposite the first main surface can also be covered with a glass layer GS in order to protect it from aggressive baths such as are used for electroplating, for example.

[0044] FIG. 2 shows a further embodiment of a chip according to the invention, wherein, in contrast to FIG. 1, besides an external contact AK on the first main surface, a connection pad AF is also present on the second main surface, said connection pad being connected to at least one part of the electrode structure within the varistor layer. In the embodiment illustrated, the varistor is thus contactable via a connection pad AF and an external contact AK, which here are arranged on different main surfaces. On the second main surface, too, a glass layer GS is then arranged here, which omits only the connection pad AF and thus protects the varistor layer against aggressive media.

[0045] FIG. 3 shows a further embodiment of a chip, wherein, in a manner similar to that in FIG. 2, both external contacts AK and connection pads AF are provided which contact the electrode structure of the varistor via plated-through holes DK1 and DK2 from the first and again from the second main surface. Two further plated-through holes DK and DK connect a respective external contact AK, AK on the first main surface to a respective connection pad AF, AF on the second main surface. The connection pad AF is not directly connected to the electrode structure of the varistor, such that an electrical connection from the first to the second main surface is led via the external contact AK' and enables a further component to be connected. The connection pad AF is connected to the electrode structure of the varistor via the plated-through hole. All connections of varistor and component connected thereto are possible in this way via the external contacts on the first main surface. Regions of the two main surfaces that are not occupied by external contacts AK and connection pads AF are covered by a glass layer GS and the varistor layer is thus protected.

[0046] FIG. 4a shows a chip similar to FIG. 1, wherein the plated-through holes DK1 and DK2 connect external contacts AK both to the electrode structure of the varistor and here additionally to connection pads AF on the second main surface. The connection pads AF and the external contacts AK are illustrated here with a larger layer thickness than the glass layer GS. Two connection pads AF suitable for connecting a component are thus present on the second main surface, via which an electrical component can be connected in parallel with the chip with varistor function and then protects the latter against overvoltages. Further connection pads AF and the external contacts AK are possible but not necessary for simple components. A voltage pulse which acts on the component or on the connection pads AF and exceeds the varistor voltage can then be dissipated harmlessly via the electrode structure toward the external contact AK.

[0047] FIG. 4b shows a chip similar to FIG. 4a, wherein the connection pads AF and the external contacts AK are embodied as two- or multilayered metallization. In this case, it is possible for the respective upper sublayerfacing away from the chipof the two- or multilayered metallization to have a larger area than the bottommost sublayer and partly also to overlap the glass layer. This has the advantage that a larger area is available for soldering or bonding with the component or with a circuit environment and that this larger area has a higher current-carrying capacity. The strength of a soldering connection or other bonding connection is also increased as a result.

[0048] FIG. 5 shows the chip from FIG. 3, wherein an electrical component BE is now mounted on the connection pads AF with the aid of a connecting means on the second main surface. Mounting can be carried out by means of soldering contacts LK, for example, as illustrated in the figure. In this way, an electrical and mechanical contact between chip and component BE is produced at the same time. The chip CH can thus serve as a carrier for the component BE and the component can be connected to a circuit environment via the external contacts AK of the chip CH. The varistor function integrated in the chip serves as protection for the component BE.

[0049] FIG. 6 shows three different green sheets GF1, GF2 and GF3 on the basis of a zinc oxide material, from which a chip according to the invention can already be assembled. The topmost green sheet GF1 illustrated has no structuring or metallization. The two lower green sheets are like image and mirror image, for example, and serve to connect the metallization, which indeed comprises a respective electrode layer, to one of two different plated-through holes. The plated-through holes are, e.g., stamped in the green sheets GF and the holes are then filled with conductive paste.

[0050] In order to produce this green sheet, a zinc oxide powder is finely ground, provided with a dopant and once again homogeneously mixed and ground. If appropriate, a glass forming agent is added in order to set the sintering temperature to a desired value. A certain shapability and cohesion of the green sheet is ensured with the aid of an organic binder. The green sheet can be shaped by sheet drawing, casting or any other conventional technique.

[0051] The second green sheet GF2 is printed with an electrode material which can be sintered to form an electrode layer ES2. Furthermore, at least two plated-through holes DK are provided in said green sheet, said plated-through holes being produced, for example, by holes being stamped into the green sheet. Afterward the plated-through holes are filled with a conductive compound, usually with the electrode material.

[0052] The third green sheet GF3 illustrated is similar to the second green sheet, but the plated-through holes and the structure of the printed electrode material in both green sheets GF2, GF3 are applied in a horizontally mirrored fashion in order to connect the respective electrode layer ES in the varistor to different plated-through holes and thus to different contacts.

[0053] FIG. 7 shows the green sheets illustrated in FIG. 6 stacked one above another to form a varistor layer VS. The figure illustrates only two inner electrode layers ES in order to clarify the alternating arrangement of the electrode layer.

[0054] In order to achieve the necessary current-carrying capacity, an expedient varistor, that is to say a chip with varistor function, generally comprises a plurality of electrode layers alternately connected to different contacts. In the illustrated stack, the electrode layers are alternately assigned to two plated-through holes arranged congruently or in an overlapping manner in the stack in order to ensure a continuous line of conduction through to a main surface, here the first main surface. As the topmost layer, here a green sheet without any plated-through hole and without an electrode layer is applied, which serves for covering the inner electrode layers ES.

[0055] It goes without saying that it is also possible to use green sheets having plated-through holes which, from the second main surface, too, enable an excess to inner electrode layers or the later external contacts on the first main surface.

[0056] In the next step, the stack of green sheets placed one above another and possibly pressed is sintered, the chip arising as a solid monolithic composite made from the originally separate green sheets. The binder burns out completely and metallic electrode layers, the ceramic varistor layer and purely metallic plated-through holes remain in the chip.

[0057] The varistor layer VS obtained after sintering is then provided with a metallization M for the external contacts AK. For this purpose, a metallization paste is printed onto the corresponding main surface such that the metallization is in contact with a respective plated-through hole DK. FIG. 8 shows the arrangement at this method stage.

[0058] Afterward, a layer of a glass-containing paste with the specifications already mentioned is printed onto the first main surface such that only the metallizations M provided for the external contacts continue not to be covered by the glass paste layer. This can be carried out by screen printing or some other spatially resolving method. Afterward, the entire arrangement is subjected to a further sintering process, wherein a fixedly adhering metallization and the now impermeable and likewise fixedly adhering glass layer GS are obtained.

[0059] Alternatively, the metallization paste can be fired before the glass paste is applied, and the glass layer can be fired separately in a further sintering process.

[0060] FIG. 9 shows the arrangement with fired metallizations M for external contacts and a fired glass layer GS.

[0061] In the next step, the metallizations M that have hitherto only been printed and fired are reinforced electrolytically or in an electroless manner in order to obtain solderable surfaces. For this purpose, conventional standardized electroplating baths are used, which are usually set up to be basic or acidic.

[0062] Suitable depositable metals for the external contacts AK, which can also be used for the connection pads AF, comprise nickel and gold and/or nickel and silver layers. However, other metallizations comprising other metals and, if appropriate, further layers can also be applied electrolytically or in an electroless manner, without the properties of the chips CH, in particular the varistor function, being detrimentally affected thereby.

[0063] FIG. 10 shows the arrangement after the thickening or completion of the external contacts AK. Depending on the desired use, the thickness of the external contacts AK can exceed the thickness of the glass layer GS. Glass layer and metallization or external contacts and glass layer can also terminate flush with one another. It is also possible to recess the external contacts AK and connection pads AF (not illustrated in FIGS. 6-10) in the glass layer GS, such that they lie at a deeper level than the surface of the glass layer.

[0064] Although only the production of external contacts AK, that is to say of solderable metallizations on a first main surface of the chip, has been described in the figures, nevertheless connection pads AF can also be produced on the second main surface of the chip in the same way and in parallel with the external contacts AK.

[0065] In one exemplary embodiment, a glass paste having the following composition is chosen for producing the glass layer GS: 78% by weight SiO.sub.2, 19% by weight B.sub.2O.sub.3 and 3% by weight K.sub.2O. Such a glass has a softening point of 775 C. and, after sintering, has a coefficient of thermal expansion of approximately 2.8 ppm/K. Firstly, however, a glass paste is produced from the glass powder or the finely distributed and homogeneously mixed oxides. In parallel therewith a varistor layer VS is processed up to the method stage illustrated in FIG. 8 that is to say up to the production of the first metallization M before the application of the glass layer GS.

[0066] At this stage, the varistor properties are determined for comparison purposes. Afterward, the glass paste is printed and fired and the varistor is measured again.

[0067] It is found that the varistor voltage remains unchanged and that the leakage current does not exceed the permissible current intensities and is less than 0.1 A in the exemplary embodiment.

[0068] An electroplating is subsequently carried out on the test components in order to thicken the metallizations M to the desired layer thickness of the external contacts AK and connection pads AF. A further determination of the varistor values at this method stage shows that the electroplating had no negative effects whatsoever on the varistor properties.

[0069] This proves that the varistor function is not adversely influenced by the printed and fired glass layer nor is the varistor layer damaged by the subsequent electroplating bath.

[0070] In a parallel experiment, a glass paste is used in which 15% by volume of zirconium oxide powder is added as filler to the glass composition. This glass layer is also fired at approximately 850 C. An electrical measurement of the chip reveals that here, too, the varistor function or the electrical varistor properties are not altered negatively.

[0071] With the chip according to the invention it is possible to realize a varistor which has a varistor voltage in the range of approximately 10 V with a structural size of, for example, 1.21.2 mm.sup.2 and a layer thickness of 250 m. The clamping voltage U.sub.c (residual voltage) is typically at the maximum of 100 V in the case of a standardized 8 kV pulse. This shows that the chip with the varistor function can manifest an excellent protective effect even with this small structural size. As a result of the high thermal conductivity, the small structural size and the contacts that are structurable without any problems, the chip can be used as a substrate for electrical components such as for LEDs, for example.

[0072] FIGS. 11a and 11b show different possibilities of how the chip with varistor function can be interconnected with an electrical component and here in particular with a light emitting diode.

[0073] In FIG. 11a, the varistor V is connected in parallel with the component BE. In the event of the varistor voltage being exceeded, the current can thus flow away through the varistor V and in this case as it were short-circuit the component until the harmful voltage has been reduced.

[0074] In FIG. 11b, the varistor V is connected in parallel with the component BE with respect to ground. In the event of the varistor voltage being exceeded, it is thus possible to dissipate the harmful overvoltage or the current through the varistor V to ground. In both cases, the component remains protected against harmful overvoltages above the varistor voltage.

[0075] In this interconnection, which is preferably realized in an arrangement in accordance with FIG. 5, the chip according to the invention is designed to dissipate excess waste heat or heat loss such as that of the LED component reliably through the varistor layer to the external contacts, where it can be dissipated harmlessly at a heat sink within a PCB (printed circuit board).

[0076] The invention is not restricted to the structures and methods illustrated in the exemplary embodiments. In particular, the electrode structure of the varistor layer can have an arbitrary number of electrode layers and an arbitrary structuring. The number of green sheets, plated-through holes, external contacts and connection pads can also be chosen arbitrarily and be adapted to the requirements for a desired use. Only external contacts or both external contacts and connection pads may be provided, which individually and independently of one another may or may not be connected to the electrode structure.