DIELECTRIC SUBSTRATE FOR SUPERCONDUCTIVE DEVICE AND SUPERCONDUCTIVE ARTICLE UTILIZING SUCH SUBSTRATE

Abstract

A substrate structure is provided for use in a superconductive device. The substrate structure has at least one of its two opposite surfaces configured for carrying at least one superconductive structure thereon. The substrate structure comprises a substrate made of a dielectric material composition and having a tape-like shape of a predetermined geometry characterized by a width-thickness aspect ratio of at least 10 and global planarity of said at least one surface defined by a surface roughness on a nanometric scale substantially not exceeding 1 nm rms.

Claims

1. A substrate structure for use in a superconductive device, the substrate structure having at least one surface configured for carrying thereon at least one superconductive structure, wherein the substrate structure comprises a substrate made of a dielectric material composition and having a tape-like shape of a predetermined geometry characterized by a width-thickness aspect ratio of at least 10 and substantial planarity of said at least one surface defined by a surface roughness on a nanometric scale substantially not exceeding 1 nm rms.

2. The substrate structure of claim 1, wherein said substrate two opposite surfaces configured for carrying two superconductive structures respectively, each of said surfaces having said global planarity.

3. The substrate structure of claim 1, further comprising at least one buffer layer on said at least one surface of the substrate configured for carrying the superconductive structure.

4. he substrate structure of claim 3, wherein the buffer layer is selected to have a lattice parameter matching a lattice parameter of the superconductor structure to be carried thereon.

5. The substrate structure of claim 3, wherein the buffer layer is at least 100 times thinner than the substrate.

6. The substrate structure of claim 1, wherein the substrate has a thickness substantially not exceeding 0.5 mm.

7. The substrate structure of claim 1, wherein the substrate is made of sapphire or silicon material.

8. The substrate structure of claim 1, being longer than 1 m.

9. The substrate structure of claim 1, wherein the substrate is flexible, having a bending radius substantially not exceeding 20 cm.

10. The substrate structure of claim 1, wherein the surface of the substrate configured for carrying the superconductive structure has said substantial global planarity defined by the surface roughness on the nanometric scale substantially not exceeding 1 nm rms, and has wave features arranged spatially on a millimetric scale.

11. The substrate structure of claim 1, wherein the surface of the substrate configured for carrying the superconductive structure has a pattern of discrete features of a size not exceeding 33 m.sup.2 arranged with density not exceeding 10.sup.6 features per cm.sup.2.

12. A superconductive device comprising at least one superconductive element, the superconductive element comprising the substrate structure of claim 1, and at least one superconductive structure on said at least one surface.

13. The device of claim 12, comprising two similar superconductive structures on the two opposite surfaces of the substrate structure, respectively.

14. The device of claim 11, wherein the substrate structure with the at least one superconductive structure on the at least one of said surfaces is configured to form at least one bifilar superconducting coil, such that electric current flowing in segments of adjacent coil windings facing each other are identical in magnitude and have opposite directions, thereby reducing stray magnetic fields and providing reduced AC losses.

15. The device of claim 11, comprising at least two said superconductive elements, arranged in a spaced-apart parallel relationship.

16. The device of claim 15, wherein said at least two superconductive elements are connected in series or in parallel.

17. The device of claim 15, wherein in each superconductor element, electric current flowing in one of the superconductive structures is identical in magnitude and opposite in direction to electric current flowing in the other superconductive structure, thereby reducing stray magnetic fields and providing reduced AC losses.

18. The device of claim 12, being configured and operable as a fault current limiter.

19. A bifilar-type superconductive device comprising the substrate structure of claim 1, and comprising at least one bifilar superconductive coil formed by said substrate, having a tape-like shape carrying at least one superconductive tape on at least one of its opposite surfaces, such that when electric current flows through the coil, the electric current in segments of adjacent coil windings facing each other are identical in magnitude and have opposite directions, thereby reducing stray magnetic fields and providing reduced AC losses of the device.

20. A bifilar-type superconductive device comprising the substrate structure of claim 1, and comprising at least two superconductive elements each formed by said substrate structure having a tape-like shape and carrying two superconductive tapes on its two opposite surfaces, such that when electric current flows through the superconductor element, the electric current in one of the superconductive structures is identical in magnitude and opposite in direction to electric current in the other superconductive structure of said element, thereby reducing stray magnetic fields and providing reduced AC losses.

21. A fault current limiter device comprising a bifilar-type superconductive device of claim 19.

22. A method for manufacturing a superconductive device, the method comprising: manufacturing a substrate structure, said manufacturing comprising applying an Edge Defined Growth to a ribbon made of a dielectric material composition, thereby pulling the ribbon directly to a desired tape-like shape characterized by a width-thickness aspect ratio of at least 10 and global planarity of at least one of two opposite surfaces of the ribbon tape defined by a surface roughness on a nanometric scale substantially not exceeding 1 nm rms; and forming at least one superconductor layer above said at least one surface.

23. The method of claim 22, wherein said ribbon tape has two opposite surfaces configured for carrying two superconductive structures respectively, each of said surfaces having said global planarity.

24. e method of claim 22, comprising coating the ribbon tape on said at least one surface thereof with a buffer layer, such that said at least one superconductive structure is formed on said buffer layer, the buffer layer being selected to have a lattice parameter matching a lattice parameter of the superconductor structure to be carried thereon.

25. he method of claim 23, comprising coating the substrate structure on the opposite surfaces thereof with buffer layers, and forming two of superconductive structures on said buffer layers, the buffer layers being selected to have a lattice parameter matching a lattice parameter of the superconductor structures.

26. The method of claim 24, wherein the buffer layer is at least 100 times thinner than the ribbon tape.

27. The method of claim 22, wherein the ribbon tape has a thickness substantially not exceeding 0.5 mm.

28. The method of claim 22, wherein the substrate is made of sapphire or silicon material.

29. The method of claim 22, wherein the substrate is flexible, having a bending radius substantially not exceeding 20 cm.

30. The method of claim 24, wherein the buffer layer is formed on the substrate using epitaxial growth.

31. The method of claim 30, wherein said epitaxial growth comprises at least one of the following: Magnetron sputtering, Pulsed Laser Deposition (PLD), Sol-Gel deposition, Ion-beam-assisted deposition (IBAD).

32. The method of claim 22, wherein the surface of the ribbon tape configured for carrying the superconductive structure has thickness modulation forming wavy features spatially arranged on a millimetric scale.

33. The method of claim 22, wherein the surface of the ribbon tape configured for carrying the superconductive structure has a pattern of discrete features of a size not exceeding 33 m.sup.2 arranged with density not exceeding 10.sup.6 features per cm.sup.2.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawings will be provided by the Office upon request and payment of the necessary fee.

[0038] In order to better understand the subject matter that is disclosed herein and to exemplify how it may be carried out in practice, embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0039] FIGS. 1A and 1B schematically illustrate the substrate structure according to the examples of the invention;

[0040] FIGS. 1C to 1F illustrate experimental substrate structure showing global planarity (nanometric scale roughness) and thickness modulation (millimetric scale wavy features) of the surface of the substrate obtained using the technique of the invention;

[0041] FIG. 2 schematically illustrate an example of manufacturing a double-side coated substrate; and

[0042] FIGS. 3A and 3B schematically illustrate two examples of a superconductive device utilizing the substrate structure of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS

[0043] Reference is made to FIGS. 1A and 1B showing schematically two examples of the substrate structure 10 of the invention. The substrate structure includes a dielectric substrate 12 of a predetermined geometry, as will be exemplified further below. Also, preferably, the substrate structure includes at least one buffer layer on at least one surface of the substrate. In the example of FIG. 1A, the substrate structure 10 includes the buffer layer 14A on one surface 12A of the substrate 12. In the example of FIG. 1B, the substrate structure 10 includes two buffer layers 14A and 14B on two opposite surfaces 12A and 12B, respectively, of the substrate 12.

[0044] The geometry of the substrate 12 is selected to provide a high aspect ratio between the width W and thickness T of the substrate. The thickness t of the buffer layer 14A (14B) is at least two orders smaller than thickness T of the substrate 12. For example, the substrate may have thickness T about 100 m and may be coated (on at least one surface) by the buffer layer having thickness t about 1 m or less. Hence, the thickness of the substrate structure 10 is practically defined by the thickness T of the substrate 12. It should be understood that the illustration is schematic, and the geometric parameters are not in scale.

[0045] The thickness of the substrate structure is preferably in a range of 0.05-0.4 mm. In some embodiments, the length of such high aspect ratio substrate structure is such that the substrate structure is flexible with a bending radius of 20 cm or less. The width of the substrate structure is preferably in a range of 4-10 mm, but in some embodiments the width may be larger than 10 mm. The width-thickness ratio may be in a range of about 10-50, and in some embodiments may be larger than 50.

[0046] Generally, the width of the substrate structure is at least 10 times higher than the thickness thereof. Such a thin substrate structure may be desirably flexible, e.g. with a bending radius of less than 20 cm, allowing it to be compactly packed to form a device with a moderate form factor. The length of the substrate structure may be in a range of 0.1 m to 10 m, or larger than 10 m.

[0047] Also, the substrate 12 has a substantially planar geometry, i.e. has global planarity or flatness of at least that surface of the substrate on which the buffer layer is to be formed to carry a superconductor structure on top thereof. In case of the double-side configuration of a superconducting device, the substrate 12 has two opposite planar surfaces 12A and 12B which are substantially parallel to one another.

[0048] As indicated above, the global planarity/flatness of the substrate's surface may be defined by its substantial/global smoothness on a nanometric scale. For example, a 11 micron surface has surface roughness substantially not exceeding 1 nm rms, and preferably less than 0.3 nm rms. As for the millimetric scale (e.g. 100100 micron surface), the surface may have micron-scale thickness modulations, e.g. 10-100 micron deep formed by wavy features on spatial millimeter scale, as well as local non-ordered (random or quazi-random) regions or defects. Such regions/defects are of a small size (e.g. not exceeding 33 m.sup.2) arranged with low density, e.g. not exceeding 10.sup.6 defects per cm.sup.2.

[0049] In this connection, reference is made to FIGS. 1C to 1F showing the experimental substrate's surface. FIG. 1C shows an atomic force microscope (AFM) image of 11 micron area of the flat substrate's surface, and FIG. 1D shows the surface roughness along an arbitrary line exhibiting steps with a smooth roughness of less than 1 nm. FIG. 1E a long range (millimetric scale) thickness modulation of such flat substrate. FIG. 1F illustrates non-ordered local crystallographic defects on the flat surface. In this example, the substrate was produced using direct pulling technique (Edge Defined Growth (EFG)), providing for pulling ribbon directly in its desired shape.

[0050] The above-described high aspect ratio, global planarity, dielectric substrate can be produced directly in the desired shape and surface quality using appropriate techniques such as Edge Defined Growth (EFG). Pulling ribbon directly in its desired shape, instead of commonly used bulk-crystal growth techniques, has several key advantages, as follows. This direct pulling technique eliminates a need for post growth polishing and cutting. The substrate is directly made in the desired shape and geometry. Desirably small surface roughness of the as-grown substrate can be automatically achieved (the so-obtained surface is flat/smooth), e.g. roughness smaller than 1 nm rms. In comparison, when using bulk growth methods, the dielectric material is cut from a large crystal boule and then undergoes several complicated polishing steps. Also the direct pulling technique provides shorter production time, which is due to the small mass of the thin substrate (short cooling times). Also, this technique provides for production of a continuous substrate without length limitation.

[0051] The direct pulling based manufacturing method, such as the EFG method, may be used for manufacturing a continuously long single crystal thin r-plane sapphire ribbon or tape. Typically, the tape is less than 1 mm thick and usually more than 0.1 mm thick, and possess some flexibility.

[0052] As an example, the inventors tested a 0.15 mm thick sapphire tape with a bending radius of 12.5 cm. For some applications, e.g. current leads, the sapphire strips may be shorter, about 1 m long, thicker than about 0.3 mm thick, and consequently nonflexible.

[0053] Another exemplary application is a fault current limiter (FCL) which contains multiple (e.g. 50-100) 1 m long non-flexible sapphire strips, having 0.5 mm thickness and 10 cm width. In the final device, these long strips may be connected in parallel/series.

[0054] Yet another application is power cables that are continuously long and flexible and exhibit low AC losses. Such power cables will require long (>1 km), thin (0.15 mm thick) sapphire strips that are flexible (e.g. having a bending radius of 15 cm).

[0055] As indicated above, the tape width is substantially larger than the thickness, preferably having a width/thickness aspect ratio of more than 10 and having two extending (or major) surfaces. The surfaces have global planarity as described above with the inherit waviness (local pattern or thickness modulations). Preferably, the sapphire tape width is about 4-12 mm. The two major surfaces of the tape have an r-plane crystallographic orientation (1-102) possibly with a small mis-cut angle of less than 5 degrees.

[0056] The manufacturing of a long planar sapphire tape is done by pulling a seed from an appropriate pedestal/crucible setup. Such pulling method is inevitably prone to vibrations that cause thickness variations along the strip (wavy features). Moreover, chemical contamination from the pulling system (crucible, pedestal, etc.) and surrounding materials can locally damage the crystallographic order of the strip. The sapphire strip produced by such technique possesses physical properties allowing it to be successfully coated with a high quality epitaxial superconductor layer (e.g. YBCO) by various, well known, techniques. As indicated above, the as-grown sapphire tape is characterized by global planarity on a nano-metric scale (e.g. scanning a surface of 11 micron) defined by the surface roughness substantially not exceeding 1 nm rms. Usually, the surface consists of multiple step like features, each step being nanometrically flat (<1 nm rms) and the height of wavy features (thickness modulation) being less than 10 nm. On a mm-scale (e.g. 100100 micron surface) there may be long range thickness modulations 10-100 m deep. Local, non-ordered areas or defects (not exceeding 33 m.sup.2 size) may exists on a limited scale with overall spatial density not exceed 10.sup.6 defects per cm.sup.2.

[0057] Reference is made to FIG. 2 schematically showing an example of a system 100 for producing double-side coated substrate structure 10 (such as that of FIG. 1B). In this example, the system utilizes the magnetron sputtering technique. As shown, after producing the above-described dielectric substrate 12 (i.e. with the desired geometry: high aspect ratio and high planarity), the substrate 12 is coated on both surface 12A and 12B thereof with an appropriate buffer layer. In the present example, the system 100 includes magnetic sputters 102 and heaters 104 accommodated at opposite sides of the thin substrate tape being rolled in a rolling direction d between two support rollers R.sub.1 and R.sub.2. Generally, the buffer layer can be epitaxially grown using any known suitable method, such as Magnetron sputtering, Pulsed Laser Deposition (PLD), Sol-Gel deposition, Ion-beam-assisted deposition (IBAD), etc. The coating can be done continuously using a feeding mechanism (e.g. rolling mechanism as shown in the figure) on both sides simultaneously. Alternatively, the buffer can be coated on one or both surfaces 12A, 12B, separately, possibly ex-situ.

[0058] It should be noted, although not specifically shown, that at least one superconductor layer may then be formed on the substrate structure 10. The superconductive layer may be YBa.sub.2Cu.sub.3O.sub.7-x. The superconductive structure (single- or multi-layer structure) may be formed directly on top of the buffer layer. Alternatively, an additional self-template layer may be provided between the buffer and the superconductor.

[0059] Thus, the present invention provides a novel substrate structure for use in a superconducting device, enabling low AC losses in the device based on the high aspect ratio double sided substrate. The superconducting device of the invention includes a superconducting tape utilizing the above-described substrate structure. More specifically, such a device may include at least one superconductor tape (generally, thin superconductive structure) coated on the at least one surface of the aforementioned high aspect ratio high planarity dielectric substrate structure.

[0060] In some embodiments, the device is configured for driving AC currents in opposite directions in the two superconducting structures. This significantly reduces the electric AC losses as compared to a similar device made from metallic coated superconductor tapes (coated conductor).

[0061] A flexible double-sided superconductor tape structure with the properties described above may be wound in a coil shape, forming what is known as a bifilar winding coil. Such a bifilar coil has a low parasitic self-inductance, while maintaining a small form factor with a large amount of superconducting material.

[0062] Such a device may be configured and operable as a superconducting fault current limiter or SFCL, a reusable fuse that limits the current in a power grid. An SFCL is connected in series to the power grid, and, during ideal operation, does not dissipate energy (no voltage drop). During a fault, the superconductor inside becomes a normal material and dissipates the excess energy in the form of heat. The total power capacity of an SFCL depends on the total area of the superconducting material, with typical energy densities of 1000-2000 W/cm.sup.2.

[0063] Reference is made to FIGS. 3A and 3B exemplifying the bifilar-type superconductive devices utilizing the high aspect ratio, global planarity dielectric substrate structure. In the example of FIG. 3A, the superconducting device 20 contains a bifilar superconducting coil (generally, at least one such coil) made of the above described flexible high-aspect ratio dielectric substrate structure. In the example of FIG. 3B, the superconducting device 30 is constructed of multiple separated pieces of the aforementioned non-flexible double sided superconducting tape. Superconductor tapes can be connected in series (forming device elements) to achieve higher power limiting capabilities through having an effectively larger superconductor area and hence higher normal state resistance. In addition, multiple device elements can be connected in parallel to achieve higher current capacity of the entire superconducting device. The electric current in each superconductor element flows in a so-called anti-parallel fashion, i.e. the current on the top layer is identical in magnitude but opposite in direction to the current flowing in the bottom layer, as shown in FIG. 3B, in order to reduce stray magnetic fields and achieve low AC losses.

[0064] As described above, the substrate used in such bifilar coil may be made from any known suitable dielectric material composition. The use of the dielectric substrate structure made from sapphire or silicon might be advantageous. For example, this enables to obtain higher energy capacity, as compared to an FCL based on coated conductors. This is due to better heat conduction of the substrate. The high thermal conductance assures that, during a fault, heat propagates quickly along the superconductor thereby avoiding high energy concentration and possible burn out of the device. It has been shown that sapphire wafers provide for increased, up to 3 orders of magnitude, power limiting capabilities [Ernst Helmut Brandt and Mikhail Indenbom, Type-II-superconductor strip with current in a perpendicular magnetic field, Physical Review B, Volume 48, Number 17, 1 Nov. 1993, pp. 12893-12906]. Also, the use of sapphire or silicon substrate reduces the maintenance and cryogenic costs. The bifilar configuration, enabled by the dielectric thin substrate, reduces the stray magnetic fields and substantially lowers the AC losses during ideal operation.