Differential operational amplifier and bandgap reference voltage generating circuit

Abstract

A differential operational amplifier, which comprises: a voltage adjusting module, coupled between a first predetermined voltage source and a second predetermined voltage source, for adjusting a first voltage via a first voltage adjusting value to generate a first adjusted voltage, and for adjusting a second voltage via a second voltage adjusting value to generate a second adjusted voltage, wherein the first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature; and a differential signal computing module, coupled between the first predetermined voltage source and the second predetermined voltage source, for generating an output voltage according the first adjusted voltage and the second adjusted voltage.

Claims

1. A differential operational amplifier, comprising: a voltage adjusting module, coupled between a first predetermined voltage source and a second predetermined voltage source, for adjusting a first voltage via a first voltage adjusting value to generate a first adjusted voltage, and for adjusting a second voltage via a second voltage adjusting value to generate a second adjusted voltage, wherein the first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature; and a differential signal computing module, coupled between the first predetermined voltage source and the second predetermined voltage source, for generating an output voltage according the first adjusted voltage and the second adjusted voltage; wherein the voltage adjusting module comprises: a first transistor, comprising: a first terminal coupled to the first predetermined voltage source, a control terminal receiving the first voltage, a second terminal outputting the first adjusted voltage, wherein the first voltage adjusting value is a voltage difference between the control terminal of the first transistor and the second terminal of the first transistor; and a second transistor, comprising: a first terminal coupled to the first predetermined voltage source, a control terminal receiving the second voltage, a second terminal outputting the second adjusted voltage, wherein the first voltage adjusting value is a voltage difference between the control terminal of the first transistor and the second terminal of the first transistor.

2. The differential operational amplifier of claim 1, wherein the first transistor is a first NMOSFET, wherein the first terminal of the first transistor is a drain terminal, the control terminal of the first transistor is a gate terminal, and the second terminal of the first transistor is a source terminal; wherein the second transistor is a second NMOSFET, wherein the first terminal of the second transistor is a drain terminal, the control terminal of the second transistor is a gate terminal, and the second terminal of the second transistor is a source terminal.

3. The differential operational amplifier of claim 2, wherein the voltage adjusting module further comprises: a first native NMOSFET, comprising: a drain terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the first NMOSFET, and a source terminal coupled to the drain terminal of the first NMOSFET; and a second native NMOSFET, comprising: a drain terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the second NMOSFET, and a source terminal coupled to the drain terminal of the second NMOSFET.

4. The differential operational amplifier of claim 1, wherein the differential signal operating module comprises: a first PMOSFET, comprising a gate terminal receiving the first adjusted voltage; a second PMOSFET, comprising: a gate terminal receiving the second adjusted voltage, and a source terminal coupled to a source terminal of the first PMOSFET; a third PMOSFET, comprising: a source terminal receiving the first adjusted voltage, and a drain terminal coupled to the source terminal of the first PMOSFET and the second PMOSFET; a fourth PMOSFET, comprising: a source terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the third PMOSFET, and a drain terminal coupled to the gate terminal of the third PMOSFET and an output terminal; a third NMOSFET, comprising: a drain terminal coupled to the drain terminal of the second PMOSFET and a gate terminal of the third NMOSFET, and a source terminal coupled to the second predetermined voltage source; a fourth NMOSFET, comprising: a drain terminal coupled to the drain terminal of the first PMOSFET, a source terminal coupled to the second predetermined voltage source, and a gate terminal coupled to a base of the third NMOSFET; a fifth NMOSFET, comprising: a drain terminal coupled to the output terminal, a gate terminal coupled to the drain terminal of the fourth NMOSFET, and a source terminal coupled to the second predetermined voltage source.

5. The differential operational amplifier of claim 4, wherein the differential signal computing module comprises: a third native NMOSFET, comprising: a drain terminal coupled to the drain terminal of the fourth PMOSFET, a gate terminal coupled to the gate terminal of the fifth NMOSFET, and a source terminal coupled to the drain terminal of the fifth NMOSFET.

6. The differential operational amplifier of claim 5, further comprising: a sixth NMOSFET, comprising: a drain terminal coupled to the source terminal of the first NMOSFET, and a source terminal coupled to the second voltage source; and a seventh NMOSFET, comprising: a drain terminal coupled to the source terminal of the second NMOSFET, a source terminal coupled to second predetermined voltage source, and a base coupled to a gate terminal of the sixth NMOSFET.

7. The differential operational amplifier of claim 6, further comprising: a fifth PMOSFET, comprising: a source terminal coupled to the first predetermined voltage source, a gate terminal coupled to a base of the fourth PMOSFET; and an eighth NMOSFET, comprising: a drain terminal coupled to a drain terminal of the fifth PMOSFET and a gate terminal of the eighth NMOSFET, a source terminal coupled to the second predetermined voltage source.

8. A bandgap reference voltage generating circuit, comprising: a current mirror, for generating a first current at a first current output terminal, for generating a second current at a second current output terminal, and for generating a third current at a third current output terminal, wherein the second current maps from the first current and the third current maps from the first current or the second current; a differential operational amplifier, comprising: an operational output terminal; a first operational input terminal; a second operational input terminal; a voltage adjusting module, coupled between a first predetermined voltage source and a second predetermined voltage source, for adjusting a first voltage via a first voltage adjusting value to generate a first adjusted voltage, and for adjusting a second voltage via a second voltage adjusting value to generate a second adjusted voltage, wherein the first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature; and a differential signal computing module, coupled between the first predetermined voltage source and the second predetermined voltage source, for generating a control voltage according the first adjusted voltage and the second adjusted voltage; a voltage generating module, for generating a first voltage at the first operational input terminal according to the first current, and for generating a second voltage at the second operational input terminal according to the second current, wherein the differential operational amplifier generates the control signal to the current mirror according to the first voltage and the second voltage, to control the first current, the second current and the third current; and a reference voltage resistance device, comprising a first terminal receiving the third current and a second terminal coupled to the second voltage source, wherein the third current generates a reference voltage at the first terminal of the reference voltage resistance device; wherein the voltage adjusting module comprises: a first transistor, comprising: a first terminal coupled to the first predetermined voltage source, a control terminal receiving the first voltage, a second terminal outputting the first adjusted voltage, wherein the first voltage adjusting value is a voltage difference between the control terminal of the first transistor and the second terminal of the first transistor; and a second transistor, comprising: a first terminal coupled to the first predetermined voltage source, a control terminal receiving the second voltage, a second terminal outputting the second adjusted voltage, wherein the first voltage adjusting value is a voltage difference between the control terminal of the first transistor and the second terminal of the first transistor.

9. The bandgap reference voltage generating circuit of claim 8, wherein the first transistor is a first NMOSFET, wherein the first terminal of the first transistor is a drain terminal, the control terminal of the first transistor is a gate terminal, and the second terminal of the first transistor is a source terminal; wherein the second transistor is a second NMOSFET, wherein the first terminal of the second transistor is a drain terminal, the control terminal of the second transistor is a gate terminal, and the second terminal of the second transistor is a source terminal.

10. The bandgap reference voltage generating circuit of claim 9, wherein the voltage adjusting module further comprises: a first native NMOSFET, comprising: a drain terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the first NMOSFET, and a source terminal coupled to the drain terminal of the first NMOSFET; and a second native NMOSFET, comprising: a drain terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the second NMOSFET, and a source terminal coupled to the drain terminal of the second NMOSFET.

11. The bandgap reference voltage generating circuit of claim 8, wherein the differential signal operating module comprises: a first PMOSFET, comprising a gate terminal receiving the first adjusted voltage; a second PMOSFET, comprising: a gate terminal receiving the second adjusted voltage, and a source terminal coupled to a source terminal of the first PMOSFET; a third PMOSFET, comprising: a source terminal receiving the first adjusted voltage, and a drain terminal coupled to the source terminal of the first PMOSFET and the second PMOSFET; a fourth PMOSFET, comprising: a source terminal coupled to the first predetermined voltage source, a gate terminal coupled to the gate terminal of the third PMOSFET, and a drain terminal coupled to the gate terminal of the third PMOSFET and an output terminal; a third NMOSFET, comprising: a drain terminal coupled to the drain terminal of the second PMOSFET and a gate terminal of the third NMOSFET, and a source terminal coupled to the second predetermined voltage source; a fourth NMOSFET, comprising: a drain terminal coupled to the drain terminal of the first PMOSFET, a source terminal coupled to the second predetermined voltage source, and a gate terminal coupled to a base of the third NMOSFET; a fifth NMOSFET, comprising: a drain terminal coupled to the output terminal, a gate terminal coupled to the drain terminal of the fourth NMOSFET, and a source terminal coupled to the second predetermined voltage source.

12. The bandgap reference voltage generating circuit of claim 11, wherein the differential signal computing module comprises: a third native NMOSFET, comprising: a drain terminal coupled to the drain terminal of the fourth PMOSFET, a gate terminal coupled to the gate terminal of the fifth NMOSFET, and a source terminal coupled to the drain terminal of the fifth NMOSFET.

13. The bandgap reference voltage generating circuit of claim 12, further comprising: a sixth NMOSFET, comprising: a drain terminal coupled to the source terminal of the first NMOSFET, and a source terminal coupled to the second voltage source; and a seventh NMOSFET, comprising: a drain terminal coupled to the source terminal of the second NMOSFET, a source terminal coupled to second predetermined voltage source, and a base coupled to a gate terminal of the sixth NMOSFET.

14. The bandgap reference voltage generating circuit of claim 13, further comprising: a fifth PMOSFET, comprising: a source terminal coupled to the first predetermined voltage source, a gate terminal coupled to a base of the fourth PMOSFET; and an eighth NMOSFET, comprising: a drain terminal coupled to a source terminal of the fifth PMOSFET and a gate terminal of the eighth NMOSFET, a source terminal coupled to the second predetermined voltage source.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram illustrating a differential operational amplifier for a prior art bandgap reference voltage generating circuit.

(2) FIG. 2 is a schematic diagram illustrating a relation between a temperature and a PMOSFET's V.sub.DS for a prior art differential operational amplifier.

(3) FIG. 3 is a schematic diagram illustrating a situation that a difference between the first voltage and the second voltage changes corresponding to the temperature variation, for prior art.

(4) FIG. 4 is a block diagram illustrating a differential operational amplifier, according to one embodiment of the present invention.

(5) FIG. 5 is a circuit diagram illustrating a differential operational amplifier, according to one embodiment of the present invention.

(6) FIG. 6 is a circuit diagram illustrating a differential operational amplifier, according to another embodiment of the present invention.

(7) FIG. 7 is a schematic diagram illustrating a relation between a temperature and a PMOSFET's V.sub.DS for a differential operational amplifier according to the present invention.

(8) FIG. 8 is circuit diagram illustrating a bandgap reference voltage generating circuit applying the differential operational amplifier according to the present invention.

(9) FIG. 9 is a schematic diagram illustrating a comparison between the bandgap reference voltage generating circuit of the present invention and the bandgap reference voltage generating circuit for prior art.

DETAILED DESCRIPTION

(10) FIG. 4 is a block diagram illustrating a differential operational amplifier 400, according to one embodiment of the present invention. As shown in FIG. 4, the differential operational amplifier 400 comprises a voltage adjusting module 401 and a differential signal computing module 403. The voltage adjusting module 401 is coupled between a first predetermined voltage source and a second predetermined voltage source (V.sub.DD and GND, not illustrated in FIG. 4), for adjusting a first voltage V.sub.1 via a first voltage adjusting value to generate a first adjusted voltage V.sub.1a, and for adjusting a second voltage V.sub.2 via a second voltage adjusting value to generate a second adjusted voltage V.sub.2a. The first voltage adjusting value and the second voltage adjusting value change corresponding to a temperature. The differential signal computing module 403 is coupled between the first predetermined voltage source and the second predetermined voltage source, for generating an output voltage V.sub.out according the first adjusted voltage V.sub.1a and the second adjusted voltage V.sub.2a at an output terminal T.sub.o.

(11) FIG. 5 is a circuit diagram illustrating a differential operational amplifier, according to one embodiment of the present invention. However, please note, the circuit diagram in FIG. 5 is only for example and does not mean to limit the present invention. As shown in FIG. 5, the voltage adjusting module 401 comprises: a first NMOSFET N.sub.1, comprising: a drain terminal coupled to the first predetermined voltage source V.sub.DD, a gate terminal receiving the first voltage V.sub.1, a source terminal outputting the first adjusted voltage V.sub.1a. The first voltage adjusting value is a voltage difference V.sub.GS1 between the gate terminal of the first NMOSFET N.sub.1 and the source terminal of the first NMOSFET N.sub.1. Additionally, the voltage adjusting module 401 comprises a second NMOSFET N.sub.2, comprising: a drain terminal coupled to the first predetermined voltage source V.sub.DD, a gate terminal receiving the second voltage V.sub.2, a source terminal outputting the second adjusted voltage V.sub.2a. The second voltage adjusting value is a voltage difference V.sub.GS2 between the gate terminal of the second NMOSFET N.sub.2 and the source terminal of the second NMOSFET N.sub.2. Please note, the first NMOSFET N.sub.1 and second NMOSFET N.sub.2 can be replaced by other transistors.

(12) The differential signal operating module 403 comprises: a first PMOSFET P.sub.1, a second PMOSFET P.sub.2, a third PMOSFET P.sub.3, a fourth PMOSFET P.sub.4, a third NMOSFET N.sub.3, a fourth NMOSFET N.sub.4 and a fifth NMOSFET N.sub.5. The first PMOSFET P.sub.1 comprises a gate terminal receiving the first adjusted voltage V.sub.1a. The second PMOSFET P.sub.2 comprises: a gate terminal receiving the second adjusted voltage V.sub.2a, and a source terminal coupled to a source terminal of the first PMOSFET P.sub.1. The third PMOSFET P.sub.3 comprises: a source terminal coupled to a first predetermined voltage source V.sub.DD, and a drain terminal coupled to the source terminal of the first PMOSFET P.sub.1 and the second PMOSFET P.sub.2. The fourth PMOSFET P.sub.4 comprises: a source terminal coupled to the first predetermined voltage source V.sub.DD, a gate terminal coupled to the gate terminal of the third PMOSFET, and a drain terminal coupled to the gate terminal of the third PMOSFET P.sub.3 and an output terminal T.sub.o. The third NMOSFET N.sub.3 comprises: a drain terminal coupled to the drain terminal of the second PMOSFET P.sub.2 and a gate terminal of the third NMOSFET N.sub.3, and a source terminal coupled to the second predetermined voltage source GND. The fourth NMOSFET N.sub.4 comprises: a drain terminal coupled to a drain terminal of the first PMOSFET P.sub.1, a source terminal coupled to the second predetermined voltage source GND, and a gate terminal coupled to a base of the third NMOSFET N.sub.3. The fifth NMOSFET N.sub.5, comprises: a drain terminal coupled to the output terminal T.sub.o, a gate terminal coupled to the drain terminal of the fourth NMOSFET N.sub.4, and a source terminal coupled to the second predetermined voltage source GND.

(13) The structure for the differential signal computing module 403 in FIG. 5 is a two stage CMOS differential operational amplifier, wherein the first PMOSFET P.sub.1, the second PMOSFET P.sub.2, the third PMOSFET P.sub.3, the third NMOSFET N.sub.3 and the fourth NMOSFET N.sub.4 are included in the first stage, and the fourth PMOSFET P.sub.4, the fifth NMOSFET N.sub.5 are included in the second stage. The third PMOSFET P.sub.3 provides a biasing voltage to the first stage amplifier, the first PMOSFET P.sub.1 and the second PMOSFET P.sub.2 form a differential input pair. Additionally, the third NMOSFET N.sub.3 and the fourth NMOSFET N.sub.4 are arranged to provide active loading and to implement a single end output transforming for the circuit. The second stage amplifier is a common source amplifier. The fourth PMOSFET P.sub.4 is arranged to provide a bias voltage and for active loading.

(14) In one embodiment, the first NMOSFET N.sub.1, the second NMOSFET N.sub.2, the third NMOSFET N.sub.3, the fourth NMOSFET N.sub.4, the fifth NMOSFET N.sub.5, the sixth NMOSFET N.sub.6, the seventh NMOSFET N.sub.7 and the eighth NMOSFET N.sub.8 operate at a 1.2 v. Also, the first PMOSFET P.sub.1, the second PMOSFET P.sub.2 operate at 1.2 v, and the third PMOSFET P.sub.3, the fourth PMOSFET P.sub.4, the fifth PMOSFET P.sub.5 operate at 3.3 v. However, it is not limited.

(15) As above-mentioned, the first voltage V.sub.1 and the second voltage V.sub.2 have a negative correlation for the temperature, thus increase while the temperature decreasing. In the embodiments, the voltage output at the output terminal T.sub.o is generated according to the first adjusted voltage V.sub.1a and the second adjusted voltage V.sub.2a. Comparing with the first voltage V.sub.1 and the second voltage V.sub.2, the first adjusted voltage V.sub.1a and the second adjusted voltage V.sub.2a respectively minuses V.sub.GS1 and V.sub.GS2 for the first NMOSFET N.sub.1 and the second NMOSFET N.sub.2, which increase corresponding to the decreasing of the temperature. Therefore, the amount that the first adjusted voltage V.sub.1a and the second adjusted voltage V.sub.2a increase corresponding to the temperature decreases, as shown in FIG. 7 of the present invention. Accordingly, the output voltage generated at the output terminal T.sub.o can suffer less disturbance from the temperature.

(16) The differential operational amplifier can further comprise other devices. For example, the differential operational amplifier 400 further comprises a sixth NMOSFET N.sub.6 and a seventh NMOSFET N.sub.7. The sixth NMOSFET N.sub.6 comprises: a drain terminal coupled to the source terminal of the first NMOSFET N.sub.1, and a source terminal coupled to the second voltage source GND. The seventh NMOSFET N.sub.7 comprises: a drain terminal coupled to the source terminal of the second NMOSFET N.sub.2, a source terminal coupled to second predetermined voltage source GND, and a base coupled to a gate terminal of the sixth NMOSFET N.sub.6. The sixth NMOSFET N.sub.6 and the seventh NMOSFET N.sub.7 are arranged to be an equivalent resistor, to help the first NMOSFET N.sub.1, the second NMOSFET N.sub.2 generate currents. Additionally, the differential operational amplifier 400 further comprise a fifth PMOSFET P5 and an eighth NMOSFET N.sub.8, which are applied as a buffer. The fifth PMOSFET P.sub.5 comprises: a source terminal coupled to the first predetermined voltage source V.sub.DD, a gate terminal coupled to a base of the fourth PMOSFET P.sub.4. The eighth NMOSFET N.sub.8 comprises: a drain terminal coupled to a drain terminal of the fifth PMOSFET and a gate terminal of the eighth NMOSFET, a source terminal coupled to the second predetermined voltage source GND.

(17) The voltage adjusting module and the differential signal computing module provided by the present invention can further comprise other devices besides the devices in FIG. 5. FIG. 6 is a circuit diagram illustrating a differential operational amplifier, according to another embodiment of the present invention. As shown in FIG. 6, the voltage adjusting module 601 further comprises a first native NMOSFET N.sub.a1 and a second native NMOSFET N.sub.a2 besides the first NMOSFET N.sub.1 and the second NMOSFET N.sub.2. The first native NMOSFET N.sub.a1 comprises: a drain terminal coupled to the first predetermined voltage source V.sub.DD, a gate terminal coupled to the gate terminal of the first NMOSFET N.sub.1, and a source terminal coupled to the drain terminal of the first NMOSFET N.sub.1. The second native NMOSFET N.sub.a2 comprises: a drain terminal coupled to the first predetermined voltage source V.sub.DD, a gate terminal coupled to the gate terminal of the second NMOSFET N.sub.2, and a source terminal coupled to the drain terminal of the second NMOSFET N.sub.2. Since the conductive voltage for the native NMOSFETs, thus the first native NMOSFET N.sub.a1 and the second native NMOSFET N.sub.a2 can make sure the VDS for the first NMOSFET N.sub.1 and the second NMOSFET N.sub.2 is not over the breaking voltage. The differential signal computing module 603 further comprises a third native NMOSFET N.sub.a3, which comprises: a drain terminal coupled to the drain terminal of the fourth PMOSFET P.sub.4, a gate terminal coupled to the gate terminal of the fifth NMOSFET N.sub.5, and a source terminal coupled to the drain terminal of the fifth NMOSFET N.sub.5. Similarly, while operating at a high voltage environment, the third native NMOSFET N.sub.a3 can make sure that the V.sub.DS of the fifth NMOSFET N.sub.5 is not over the breaking voltage. In one embodiment, the first native NMOSFET N.sub.a1, the second native NMOSFET N.sub.a2, and the third native NMOSFET N.sub.a3 all operate at a 3.3 v.

(18) FIG. 8 is circuit diagram illustrating a bandgap reference voltage generating circuit applying the differential operational amplifier according to the present invention. As shown in FIG. 8, the bandgap reference voltage generating circuit 800 comprises a current mirror 801, a differential operational amplifier OP, an input voltage generating module 803 and a reference voltage resistance device R.sub.r. The current mirror 801 receives a first predetermined voltage V.sub.DD and generates a first current I.sub.1 at a first current output terminal T.sub.c1, generates a second current I.sub.2 at a second current output terminal T.sub.c2, and generates a third current I.sub.3 at a third current output terminal T.sub.c3. The second current I.sub.2 maps from the first current I.sub.1, and the third current I.sub.3 maps from the first current I.sub.1 or the second current I.sub.2. The differential operational amplifier comprises: an operational output terminal T.sub.o1, a first operational input terminal T.sub.11 and a second operational input terminal T.sub.12. The input voltage adjusting module 803 generates a first voltage V.sub.1 at the first operational input terminal T.sub.11 according to the first current I.sub.1, and generates a second voltage V.sub.2 at the second operational input terminal T.sub.12 according to the second current I.sub.2. The differential operational amplifier OP generates a control voltage V.sub.c at the operational output terminal T.sub.o1 according to the first voltage V.sub.1 and the second voltage V.sub.2 (i.e. the output voltage V.sub.out in FIG. 4) to the current mirror 801 to control the first current I.sub.1, the second current I.sub.2 and the third current I.sub.3. In the following embodiment, the first voltage V.sub.1 and the second voltage V.sub.2 are the same due to the virtual short of the differential operational amplifier OP, thus the first current I.sub.1 and the second current I.sub.2 are the same. Additionally, the third current I.sub.3 maps from the second current I.sub.2 and is the same as the second current I.sub.2, but not limited. A reference voltage V.sub.r is generated while the third current I.sub.3 flowing through the reference voltage resistance device R.sub.r. Furthermore, the differential operational amplifier OP can comprise the circuits as above-mentioned description.

(19) In one embodiment, the current mirror 801 comprises a PMOSFET P.sub.o, the PMOSFET P.sub.Q and the PMOSFET P.sub.R. The PMOSFET P.sub.o comprises: a source terminal coupled to the first predetermined voltage V.sub.DD, a drain terminal as the first current output terminal T.sub.c1, and a gate terminal receiving the control voltage V.sub.c. The PMOSFET P.sub.Q comprises: a source terminal coupled to the first predetermined voltage V.sub.DD, a drain terminal as the second current output terminal T.sub.c2, and a gate terminal receiving the control voltage V.sub.c. The PMOSFET P.sub.R comprises: a source terminal coupled to the first predetermined voltage V.sub.DD, a drain terminal as the third current output terminal T.sub.c2, and a gate terminal coupled to a base of the PMOSFET P.sub.Q.

(20) In one embodiment, the input voltage generating module 803 comprises: a first resistance device R.sub.1, a second resistance device R.sub.2, a third resistance device R.sub.3, a first BJT Q.sub.1 and a second BJT Q.sub.2. The first terminal of the resistance device R.sub.1 is coupled to the first operational input terminal T.sub.I1. The collecting terminal of the first BJT Q.sub.1 is coupled to a second terminal of the first resistance device R.sub.1, and the emitting terminal of the first BJT Q.sub.1 is coupled to a second predetermined voltage GND. The second resistor R.sub.2 comprises a first terminal coupled to the first operational input terminal T.sub.I1, and a second terminal coupled to a second predetermined voltage GND. The second BJT Q.sub.2 comprises: a collecting terminal coupled to the second operational input terminal T.sub.I2, an emitting terminal coupled to the second predetermined voltage GND, and a basic terminal coupled to a basic terminal of the first BJT Q.sub.1 and coupled to the second predetermined voltage GND. The third resistance device R.sub.3 comprises: a first terminal coupled to the second operational input terminal T.sub.I2, and a second terminal coupled to the second predetermined voltage GND.

(21) The operation for the embodiment of FIG. 8 is illustrated as below. In the following embodiment, the resistance values of the second resistance device R.sub.2 and the third resistance device R.sub.3 are assumed to be the same, and a size of the second BJT Q.sub.2 is X times for the first BJT Q.sub.1. As above-mentioned, the first voltage V.sub.1 and the second voltage V.sub.2 are the same due to the virtual short of the differential operational amplifier OP. The currents flowing through the second resistance device R.sub.2 and the third resistance device R.sub.3 are the same since the second resistance device R.sub.2 and the third resistance device R.sub.3 have the same resistance values. Accordingly, the currents flowing through the first BJT Q.sub.1 and the second BJT Q.sub.2 are the same. In such case, the voltage difference between the emitting terminal of the first BJT Q.sub.1 and the second BJT Q.sub.2 is V.sub.T ln X, wherein V.sub.T is a thermal voltage and equals to

(22) $\frac{\mathrm{KT}}{q},$
q is a Coulomb charge, K is Boltzmann's constant and T is a temperature. Thus, the voltage difference between two terminals for the first resistor R.sub.1 is V.sub.T ln X.

(23) In view of above-mentioned concept, the first current I.sub.1 is

(24) $\frac{V_T\ln X}{R_1}+\frac{V_{\mathrm{EB}2}}{R_2},$
wherein V.sub.EB2 is a voltage difference between a basic terminal and an emitting terminal of the second BJT Q.sub.2. The third current I.sub.3 also equals to

(25) $\frac{V_T\ln X}{R_1}+\frac{V_{\mathrm{EB}2}}{R_2},$
since the first current I.sub.1 equals to the second current I.sub.2, and the second current I.sub.2 equals to the third current I.sub.3. Therefore, the reference voltage V.sub.r equals

(26) $\frac{V_T\ln X}{R_1}+\frac{V_{\mathrm{EB}2}}{R_2}]R_r.$
Ideally, V.sub.T has a positive correlation with the temperature variation, and V.sub.EB2 has a negative correlation with the temperature variation, such that the variation for the voltages counteracts with each other. By this way, the reference voltage Vr can be kept at a constant value regardless of the temperature variation. As above-mentioned, the first voltage V.sub.1 and the second voltage V.sub.2 affects V.sub.DS for the transistor in the differential operational amplifier due the temperature variation. Therefore, the stability for the reference voltage V.sub.r if no above-mentioned calibration is performed.

(27) FIG. 9 is a schematic diagram illustrating a comparison between the bandgap reference voltage generating circuit of the present invention and the bandgap reference voltage generating circuit for prior art. As shown in FIG. 9, the reference voltage for the prior art significantly changes corresponding to the temperature, therefore the reference voltage provided by the present invention is more stable.

(28) In view of above-mentioned description, the present invention adjusts the first and the second input voltages via at least one adjusting amount changing corresponding to the temperature variation. Thereby the firs input voltage and the second input voltage have less difference corresponding to the temperature variation, thus the suppressing for the V.sub.DS of the transistor in the differential operational amplifier decreases. By this way, the differential operational amplifier can have a better performance, and the bandgap reference voltage generating circuit applying the differential operational amplifier can generate a more stable reference voltage.

(29) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.