Semiconductor structure with a spacer layer
09536984 ยท 2017-01-03
Assignee
Inventors
Cpc classification
H10D30/4755
ELECTRICITY
H10D84/84
ELECTRICITY
H10D30/0289
ELECTRICITY
H10D84/0142
ELECTRICITY
H10D62/824
ELECTRICITY
H10D64/513
ELECTRICITY
H10D30/0297
ELECTRICITY
H10D30/015
ELECTRICITY
H10D64/256
ELECTRICITY
International classification
Abstract
A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a III-N material Al.sub.xIn.sub.yGa.sub.zN in which 0x1, 0y1, and 0z1, at least one sublayer has a non-zero Ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer. Also described are methods for fabricating such semiconductor structures, with gate and/or ohmic recesses formed by selectively removing adjacent layers or sublayers. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.
Claims
1. A method for making a III-Nitride (III-N) semiconductor device, comprising: patterning a semiconductor structure to expose a gate region of a transistor, wherein the semiconductor structure comprises: a channel layer comprising a first III-N material for providing electrical conduction; a band-offset layer disposed on the channel layer, the band-offset layer comprising a second III-N material, and having a wider bandgap than the channel layer; a spacer layer disposed on the band-offset layer, the spacer layer comprising a third III-N material, and having a narrower bandgap than the band-offset layer; a cap layer disposed on the spacer layer, the cap layer comprising at least two sublayers, wherein each sublayer is selectively etchable with respect to sublayers immediately below and above, wherein each sublayer comprises a III-N material Al.sub.xIn.sub.yGa.sub.zN in which 0x1, 0Y1 and 0Z1, wherein at least one of the sublayers has a non-zero Ga content with 0<Z1, and wherein a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer; selectively recessing the gate region of the transistor by removing a number of adjacent sublayers of the cap layer to form a gate recess, wherein a bottom of the gate recess is within or on a layer selected from the group consisting the channel layer, the band-offset layer, the spacer layer, and one of the sublayers of the cap layer; disposing a gate dielectric material above at least a portion of the channel layer and over the gate recess; forming a gate electrode for the transistor; and forming a pair of ohmic contacts outside the gate region for the transistor.
2. The method of claim 1, wherein the spacer layer comprising the third III-N material has zero Al content.
3. A multi-layer semiconductor structure for use in a III-Nitride (III-N) semiconductor device, comprising: a channel layer comprising a first III-N material for providing electrical conduction; a band-offset layer disposed on the channel layer, the band-offset layer comprising a second III-N material, and having a wider bandgap than the channel layer; a spacer layer disposed on the band-offset layer, the spacer layer comprising a third III-N material, and having a narrower bandgap than the band-offset layer; a cap layer disposed on the spacer layer, the cap layer comprising at least two sublayers, wherein each sublayer is selectively etchable with respect to sublayers immediately below and above, wherein each sublayer comprises a III-N material Al.sub.xIn.sub.yGa.sub.zN in which 0x1, 0Y1 and 0Z1, wherein at least one of the sublayers has a non-zero Ga content with 0<Z1, and wherein a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer; a gate region comprising a gate recess and a gate dielectric material disposed above at least a portion of the channel layer and over the gate recess, wherein a bottom of the gate recess is within or on a layer selected from the group consisting the channel layer, the band-offset layer, the spacer layer, and one of the sublayers of the cap layer; and a pair of ohmic contacts disposed outside the gate region.
4. The multi-layer semiconductor structure of claim 3, further comprising a Ga-polar surface.
5. The multi-layer semiconductor structure of claim 3, wherein a thickness of the spacer layer is less than or equal to 20 nm, and greater than or equal to 0.2 nm.
6. The multi-layer semiconductor structure of claim 3, wherein the spacer layer is n-type doped.
7. The multi-layer semiconductor structure of claim 3, wherein the sublayer immediately above the spacer layer is selectively etchable over the spacer layer using a wet etching process.
8. The multi-layer semiconductor structure of claim 3, wherein the sublayer immediately above the spacer layer is etched at a rate greater than three times as high as the spacer layer.
9. The multi-layer semiconductor structure of claim 3, wherein adjacent sublayers of the cap layer have Al contents alternating between less than 50% (0x<0.5) and greater than 50% (0.5<x1).
10. The multi-layer semiconductor structure of claim 3, wherein the spacer layer comprising the third III-N material has zero Al content.
11. The multi-layer semiconductor structure of claim 3, wherein the first III-N material is GaN, wherein the second III-N material is Al.sub.xIn.sub.yGa.sub.zN in which x+y+z=1, 0<x1, 0y1, and 0z1, and wherein the third III-N material is GaN.
12. The multi-layer semiconductor structure of claim 3, wherein each of the first, the second, and the third III-N materials is selected from the group consisting of GaN, AlN, AlGaN, InAlN, and AlInGaN.
13. The multi-layer semiconductor structure of claim 3, further comprising: a gate contact disposed above and covering the gate recess; and a gate field plate extension disposed over the gate dielectric material, outside the gate recess.
14. The multi-layer semiconductor structure of claim 3, wherein each bottom of the pair of ohmic contacts are within or on a layer selected from the group consisting the channel layer, the band-offset layer, the spacer layer, and a sublayer of the cap layer.
15. The multi-layer semiconductor structure of claim 3, wherein the band-offset layer comprising the second III-N material has a non-zero Al content.
16. The multi-layer semiconductor structure of claim 15, wherein the second III-N material is Al.sub.xGa.sub.zN in which x+z=1, 0.05<x0.4, and 0.6z<0.95.
17. The multi-layer semiconductor structure of claim 3, further comprising a carrier-donor layer disposed above at least a portion of the channel layer to provide carriers to the channel layer.
18. The multi-layer semiconductor structure of claim 17, wherein the carrier-donor layer has a thickness of at least 0.2 nm, and a doping concentration of at least 10.sup.16 cm.sup.3.
19. The multi-layer semiconductor structure of claim 1, further comprising: an anode region comprising an anode dielectric material disposed above at least a portion of the channel layer; and an ohmic cathode electrode disposed outside the gate region.
20. The multi-layer semiconductor structure of claim 19, wherein a bottom of the ohmic cathode electrode is within or on a layer selected from the group consisting the channel layer, the band-offset layer, the spacer layer, and a sublayer of the cap layer.
Description
BRIEF DESCRIPTION OF DRAWINGS
(1) Embodiments of the present invention described herein are exemplary, and not restrictive. Embodiments will now be described, by way of examples, with reference to the accompanying drawings. In these drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like reference character. For purposes of clarity, not every component is labeled in every drawing. The drawings are not necessarily drawn to scale, with emphasis instead being placed on illustrating various aspects of the techniques and devices described herein.
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DETAILED DESCRIPTION OF THE INVENTION
(23) In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details. In other instances, structures, devices, activities, and methods are shown using schematics, use cases, and/or flow diagrams in order to avoid obscuring the invention. Although the following description contains many specifics for the purposes of illustration, anyone skilled in the art will appreciate that many variations and/or alterations to suggested details are within the scope of the present invention. Similarly, although many of the features of the present invention are described in terms of each other, or in conjunction with each other, one skilled in the art will appreciate that many of these features can be provided independently of other features. Accordingly, this description of the invention is set forth without any loss of generality to, and without imposing limitations upon, the invention.
(24) Broadly, embodiments of the present invention relate to multi-layer semiconductor structures and methods for fabricating such structures, with one or more gate recesses. Such multi-layer structure may facilitate the monolithic integration of Group III-Nitride (III-N) transistors having different threshold voltages. The threshold voltage of a transistor is a gate voltage past which the transistor is turned from an on-state to an off-state, or vice versa. Such multi-layer semiconductor structures utilize selectively etchable layers or sublayers disposed over a common substrate, where selective etchability enables gate recesses and/or ohmic recesses to be formed with controllable depths, leading to desired or targeted threshold voltages. Monolithic integration of different types of transistors, especially E-mode and D-mode transistors, may greatly enhance the utility of such devices, by allowing the further addition of digital or control functions to analog and mix-signal components on a common substrate, thus improving the performance of the resulting integrated circuits, while also providing design flexibility to reduce production cost and circuit foot-print.
(25) Gate recess is an important technology for certain types of transistors, including nitride semiconductor-based transistors such as AlGaN/GaN high-electron-mobility transistors (HEMTs). In radio frequency AlGaN/GaN HEMTs, gate recess has been used to reduce short channel effects and to improve the current gain cut-off frequency. In power switching applications, gate recess has been used to fabricate normally-off field effect transistors, such as AlGaN/GaN HEMTs. Since both GaN and AlGaN are very inert to wet chemical etchants, chlorine-based dry plasma etching is typically used to form gate recesses in AlGaN/GaN devices. There are, however, two major drawbacks to dry plasma etching: 1) it may cause plasma damage, creating a high density of defect states and degrading the channel mobility in the recessed region; and 2) due to variations in the plasma etch rate, it may be difficult to control the recess depth precisely by timed etching, which causes a variation in transistor parameters such as the transconductance (g.sub.m) and threshold voltage (V.sub.T). Control of device variations becomes even more challenging when devices with different gate lengths are subjected to the same gate recess etching process, as the etching rates can be different for different transistor gate lengths and/or aspect ratios.
(26) Described herein are semiconductor structures and processes for forming such semiconductor structures while reducing or eliminating plasma-induced damage and etch-based process variations. A recess etching fabrication technology is described which can precisely control the etching depth and produce an extremely low defect density on the recessed surface. In some embodiments, the semiconductor structures described herein may be formed of compound semiconductor material(s), such as III-V semiconductor material(s), particularly Group III-Nitride (III-N) semiconductor material(s). Using such techniques, high performance transistors can be fabricated, such as RF III-N and/or normally-off III-N power transistors, for example.
(27) Further described herein are multi-layer semiconductor structures that enable the integration of multiple transistors with different threshold voltages on a common substrate, and processes for forming such semiconductor structures. While providing precise control over individual etching depths and producing extremely low defect densities on recessed surfaces, the multi-layer semiconductor structure and recess etching fabrication technology as described herein further enable flexible, side-by-side integration of multiple transistor devices with different gate recess depths and/or ohmic recess depths, leading to different threshold voltages.
(28) The techniques described herein can exploit etching selectivity between different semiconductor materials such as different III-N semiconductor materials. For example, GaN can be selectively etched over materials such as AlN, AlGaN, InAlN and AlInGaN with high Al content using a dry etching technique. In some embodiments, a selective dry etching step followed by a wet etching step can be used to achieve precise control of recess depth and to produce a surface with a low density of defect states. The wet etching step, if performed, may be selective or non-selective. If the wet etching step is selective, AlN, AlGaN, InAlN and AlInGaN with high Al content can be selectively etched over materials such as GaN, AlGaN, InGaN, and AlInGaN with low Al content using a wet etching technique. However, the techniques described herein are not limited as to a wet etching step.
(29) With reference to the figures, embodiments of the present invention are now described in detail.
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(31) In some embodiments, a semiconductor material with a lattice constant different from that of substrate 2 may be formed over substrate 2. In some embodiments, a buffer layer 4 may be included between substrate 2 and the overlying semiconductor material to accommodate a difference in lattice constant. Substrate 2 may include a group IV, III-V, or II-VI semiconductor material such as silicon, germanium, or ZnO for example. Other typical substrates include SiC, Sapphire, Si, and bulk GaN. The semiconductor material formed over substrate 2 may include a compound semiconductor material, such as a III-V semiconductor material (e.g., a III-N material). Suitable techniques for accommodating a lattice mismatch between substrate 2 and a semiconductor material of different lattice constant using a buffer layer 4 are understood by those of ordinary skill in the art, and will not be detailed herein. In some embodiments, a substrate 2 having a suitable lattice constant for the formation of overlying compound semiconductor material(s) may be used, and buffer layer 4 may be omitted. For example, substrate 2 may be a GaN substrate, a ZnO substrate or another substrate of a material with a lattice constant similar to that of a compound semiconductor material to be formed thereon. The techniques described herein are not limited as to substrate 2 or buffer layer 4. In addition, although not shown explicitly in
(32) Substrate 2 and the layers of semiconductor materials formed thereon may be monocrystalline, and may have any suitable crystallographic orientation. Compound semiconductor materials, if included in substrate 2 or an overlying layer, may have any suitable composition at the face of the semiconductor material. If a III-N material is included, it may have an N-face composition or a group III face composition. For example, GaN may be grown either N-face/N-polar, Ga-face/Ga-polar or in non-polar orientations.
(33) Channel layer 6 may be formed of a semiconductor material suitable for formation of a channel therein. In some embodiments, channel layer 6 may include a III-V semiconductor material, such as a III-N semiconductor material. In some embodiments, channel layer 6 may include gallium nitride (GaN). In some embodiments, a nitride semiconductor material may be used such as B.sub.wAl.sub.xIn.sub.yGa.sub.zN, for example, in which w, x, y and z each has a suitable value between zero and one (inclusive), and w+x+y+z=1.
(34) In some embodiments, a semiconductor heterostructure may be formed in the semiconductor structure 1. For example, in some embodiments a barrier layer 8 comprising B.sub.w1Al.sub.x1In.sub.y1Ga.sub.z1N and a channel layer 6 comprising B.sub.w2Al.sub.x2In.sub.y2Ga.sub.z2N may be formed, where a semiconductor material of barrier layer 8 has a larger bandgap and/or polarization than that of channel layer 6. However, the techniques described herein are not limited as to the formation of heterostructures.
(35) As implicitly implied above, in some embodiments, each layer formed over substrate 2, including buffer layer 4, channel layer 6, and barrier layer 8 may comprise more than one materials, including III-N materials. For example, buffer layer 4 may comprise an AlN/GaN superlattice. In some embodiments, a portion or one or more regions of buffer layer 4 or channel 6 may be GaN. Such regions may be located at layer interfaces, or at positions particularly defined with respect to desired gate or ohmic contact regions. For example, the nucleation layer as described before may be included as part of buffer layer 4 at the interface with substrate 2. In yet some other embodiments, one or more layers formed over substrate 2 may be doped with a suitable dopant.
(36) As discussed above, in some embodiments, a barrier layer 8 may be formed having two or more layers or sublayers. For example, barrier layer 8 may include a dual-layer barrier structure having an upper barrier layer 10 of a first semiconductor material that is etchable using a first etching technique and a lower barrier layer 12 of a second semiconductor material that is etchable using a second etching technique. In some embodiments, upper barrier layer 10 may include a semiconductor material that is selectively etchable in a dry etching process, such as GaN, for example, or another nitride semiconductor material such as B.sub.wAl.sub.xIn.sub.yGa.sub.zN, for example, in which w, x, y and z each has a suitable value between zero and one (inclusive), and w+x+y+z=1, and the composition is such that the nitride semiconductor material is selectively etchable using a dry etching process. For example, upper barrier layer 10 may include a semiconductor material such as B.sub.wAl.sub.xIn.sub.yGa.sub.zN in which x is less than 0.25.
(37) Upper barrier layer 10 may be doped or undoped. Doping of upper barrier layer 10 may supply carriers to channel layer 6 underneath. After gate recessing, one or more doped regions may be formed between the gate and the source and/or between the gate and the drain, outside of the gate-recess. A doped region may be polarization doped or may include dopants such as n-type dopants or p-type dopants. A doped region may have any suitable doping concentration and distribution. For example, dopants may be provided at the lower surface of upper barrier layer 10, the upper surface of upper barrier layer 10, and/or in another location. The doping profile can be uniform or non-uniform. The doping concentration may be at least 10.sup.16 cm.sup.3. In some embodiments, a delta-doping profile may be used. If upper barrier layer 10 is doped, any suitable doping technique may be used, such as implantation or diffusion. In some embodiments, upper barrier layer 10 may be doped during its formation (e.g., growth). In some embodiments, the doping type of upper barrier layer 10 may be of the same type as that of carriers in the channel region. For example, the doping type in upper barrier layer 10 may be n-type for an n-channel transistor and p-type for a p-channel transistor. In some embodiments, the doped region may be highly doped.
(38) Lower barrier layer 12 may include a semiconductor material that is etchable using a wet etching technique, such as aluminum nitride (AlN), for example, or another material such as B.sub.wAl.sub.xIn.sub.yGa.sub.zN, for example, in which w, x, y and z each has a suitable value between zero and one (inclusive), and w+x+y+z=1, and the composition is such that the nitride semiconductor material is etchable using a wet etching process. For example, lower barrier layer 12 may include a semiconductor material such as B.sub.wAl.sub.xIn.sub.yGa.sub.zN in which x is greater than 0.5. Furthermore, lower barrier layer 12 may be doped using any suitable doping technique such as those discussed above with respect to the optional doping of upper barrier layer 10.
(39) The reference herein to B.sub.wAl.sub.xIn.sub.yGa.sub.zN or a B.sub.wAl.sub.xIn.sub.yGa.sub.zN material refers to a semiconductor material having nitride and one or more of boron, aluminum, indium and gallium. Examples of B.sub.wAl.sub.xIn.sub.yGa.sub.zN materials include binary, ternary, and quaternary compounds such as GaN, AlN, AlGaN, AlInGaN, InGaN, and BAlInGaN, by way of illustration. Examples of B.sub.wAl.sub.xIn.sub.yGa.sub.zN materials also include compounds with relatively percentages in which w, x, y and z each has a suitable value between zero and one (0w1, 0x1, 0y1, and 0z1), and w+x+y+z=1. A B.sub.wAl.sub.xIn.sub.yGa.sub.zN material may include other materials besides nitride, boron, aluminum, indium and/or gallium as well. For example, a B.sub.wAl.sub.xIn.sub.yGa.sub.zN material may be doped with a suitable dopant such as silicon and germanium. Furthermore, in the present disclosure, the terms B.sub.wAl.sub.xIn.sub.yGa.sub.zN material and III-N material are used interchangeably to represent nitride-based compound semiconductor materials, unless otherwise specified or limited.
(40) A process of forming a transistor in the semiconductor structure 1 of
(41) As shown in
(42) As discussed above, the first etching technique may include a dry etching technique (e.g., dry plasma etching, also referred-to as reactive ion etching (RIE)). If the upper barrier layer includes GaN, a fluorine-based etching process may be used, for example.
(43) As shown in
(44) If the second etching step is performed, a portion of lower barrier 12 may be removed in a window formed by the removal of a region of upper barrier layer 10 in the first etching step. In some embodiments, the etch process used in the second etching step may selectively etch lower barrier layer 12 with respect to a layer overlying lower barrier layer 12 and which may be in contact with lower barrier layer 12, such as upper barrier layer 10, for example. In some embodiments, the etch process used in the second etching step may selectively etch lower barrier layer 12 with respect to a layer below lower barrier layer 12 which may be in contact with lower barrier layer 12, such as channel layer 6 and/or a band-offset layer. The selectivity of the etching of lower barrier layer 12 with respect to upper barrier layer 10 and/or channel layer 6 may be greater than one, such that the rate of etching of lower barrier layer 12 is greater than that of upper barrier layer 10 and/or channel layer 6. In some embodiments, the selectivity may be greater than 3:1, such that lower barrier layer 12 is etched at a rate greater than three times as high as upper barrier layer 10 and/or channel layer 6. However, the second etching step is not required to be selective, and in some embodiments may not selectively etch lower barrier layer 12 with respect to upper barrier layer 10 or channel layer 6.
(45) As discussed above, the etching technique used in the second etching step may be a wet etching technique.
(46) As shown in
(47) In some embodiments, upper barrier layer 10 may be selectively etched over lower barrier layer 12 in the source and/or drain region(s). Lower barrier layer 12 may be wet etched in the source and/or drain regions(s) so that an ohmic metallization can be formed on the remaining barrier layer in the source and/or drain regions(s). The dry and/or wet etching of upper barrier layer 10 and/or lower barrier layer 12, respectively, to form the source and/or drain region(s) may be performed in the same etching process(es) used to form the gate recess, in some embodiments, or in a different process.
(48) In some embodiments, the portion of barrier layer 8 remaining after the formation of gate recess 16 may have a thickness smaller than a critical thickness to prevent the formation of a two dimensional electron gas (2DEG) under the gate (see
(49) The operation of normally-on and normally-off transistors is summarized as follows. When a normally-off, or Enhancement mode (E-mode) transistor has no voltage applied to the gate, the transistor is in the off-state and is substantially non-conducting. When a suitable voltage is applied to the gate, a normally-off transistor is in the on-state and carriers can flow between its main conduction terminals (e.g., source and drain). The threshold voltage of a transistor is a gate voltage past which the transistor is turned from an on-state to an off-state, or vice versa. The threshold voltage V.sub.T of a normally-off (E-mode) transistor is generally positive. When a normally-on, or Depletion mode (D-mode) transistor has no voltage applied to the gate, the transistor is in the on-state and carriers can flow between its main conduction terminals (e.g., source and drain). When a normally-on transistor has a suitable voltage applied to the gate, the normally-on transistor is in the off-state and is substantially non-conducting. The threshold voltage V.sub.T of a normally-on (D-mode) transistor is generally negative.
(50) In some embodiments, carriers may be supplied to channel layer 6 by a layer different from upper barrier layer 10 or lower barrier layer 12.
(51) Carrier-donor layer 22 may supply carriers to channel layer 6. After gate recessing, which removes a portion of carrier-donor layer 22 as well, the remaining portion of carrier-donor layer 22 may supply carriers to channel layer 6 approximately outside of the region under the gate. Carrier-donor layer 22, if included in the semiconductor stack, may be doped using any suitable doping technique such as those discussed above with respect to the optional doping of upper barrier layer 10. After gate recessing, one or more doped regions may be formed in carrier-donor layer 22 between the gate and the source and/or between the gate and the drain, outside of the gate-recess. A doped region may be polarization doped or may include dopants such as n-type dopants or p-type dopants. A doped region may have any suitable doping concentration and distribution. For example, dopants may be provided at the lower surface of carrier-donor layer 22, the upper surface of carrier-donor layer 22, and/or in another location. The doping profile may be uniform or non-uniform. In some embodiments, carrier-donor layer 22 may have a thickness of at least 0.2 nm, and a doping concentration of at least 10.sup.16 cm.sup.3. In some embodiments, carrier-donor layer 22 may comprise sublayers with different doping concentrations. In some embodiments, a delta-doping profile may be used. Any suitable doping technique may be used, such as implantation or diffusion, for example. In some embodiments, carrier-donor layer 22 may be doped during its formation or growth. In some embodiments, the doping type of carrier-donor layer 22 may be of the same type as that of carriers in the channel region. For example, the doping type in carrier-donor layer 22 may be n-type for an n-channel transistor and p-type for a p-channel transistor. In some embodiments, a doped region may be highly doped. If a carrier-donor layer 22 is included, in some embodiments, upper barrier layer 10 and/or lower barrier layer 12 may not be doped.
(52) In some embodiments, carrier-donor layer 22 may be formed of a semiconductor material that is etchable by a dry etching process. Carrier-donor layer 22 may include a compound semiconductor such as a III-V semiconductor material, e.g., a III-N semiconductor material, such as B.sub.wAl.sub.xIn.sub.yGa.sub.zN, for example, in which w, x, y and z each has a suitable value between zero and one (inclusive), and w+x+y+z=1, and the composition is such that the III-N semiconductor material is etchable using a dry etching process. As shown in
(53) In some embodiments, carrier-donor layer 22 may shape the electric field in the semiconductor structure (e.g., in the channel region). The doping density may be tuned as needed to shape the electric field. In some embodiments, carrier-donor layer 22 may be used as a passivation layer. Carrier-donor layer 22 may have any suitable thickness. In some embodiments, the thickness of carrier-donor layer 22 may be greater than 5 nm.
(54) As shown in
(55) In some embodiments, a semiconductor structure may include a band-offset layer 32 between channel layer 6 and lower barrier layer 12. Band-offset layer 32 may increase the band-offset between a barrier layer 38 and channel layer 6. As shown in
(56) As shown in
(57) In some embodiments, a semiconductor structure may include a plurality of dual-layer barrier structures. Any suitable number of dual-layer barrier structures may be included. For example, as illustrated in
(58) Descriptions as provided above are techniques for forming a recess that may be applied to form a gate recess of a transistor. Such techniques may be applied to any suitable type of transistors, including any type of field effect transistors such as MISFETs (Metal-Insulator Semiconductor Field Effect Transistors), and MESFETs (Metal-Semiconductor Field Effect Transistors).
(59) The techniques described herein are not limited to techniques for forming a gate-recess. Such techniques may be used any other application where a damage-free, uniform and/or reproducible etch is desired. One example is the formation of ohmic recesses to reduce ohmic contact resistance and/or to form gold-free ohmic contacts. Another example is the formation of one or more recesses to access an n-doped layer in a GaN light emitting diode or laser. A further example is the formation of one or more recesses to access the base and/or collector layers in a III-N bipolar transistor.
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(62) The DC (direct current) characteristics of the recessed-gate GaN MISFET 500 may be studied. Device threshold voltage V.sub.T may be defined as V.sub.T=V.sub.gsi0.5V.sub.ds, where V.sub.gsi is the interception voltage from a linear extrapolation of an I.sub.d-V.sub.gs curve, not shown here. A small drain voltage (V.sub.ds=0.1 V) may be applied to place the device in a linear operation region. Averaging over 13 devices, the recessed-gate GaN MISFETs have a uniform V.sub.T of 0.300.04 V. The average subthreshold slope is 621 mV/decade. A bidirectional gate voltage sweep in the transfer characteristics shows less than 10 mV hysteresis in the threshold voltage. The recessed-gate transistor has a similar on-resistance (R.sub.on=10 .Math.mm) as a planar gate transistor with the same source-to-drain distance (Lsd=11 m). The relatively low maximum drain current of both recessed-gate and planar gate transistors is due to the large gate length and gate-to-source distance, relatively low 2DEG density (7.110.sup.12 cm-2), and high contact resistance (1.2 .Math.mm) of the non-optimized ohmic contact.
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(64) In addition to semiconductor structure 40, both semiconductor structure 600 and semiconductor structure 650 may be used for fabricating multiple types of transistors with different threshold voltages (V.sub.T). The threshold voltage of a transistor is a gate voltage past which the transistor is turned from an on-state to an off-state, or vice versa. Semiconductor structure 600 may include a substrate layer 602, a buffer layer 604, a channel layer 606, a band-offset layer 630 and a cap layer 608. Each of substrate layer 602, buffer layer 604, channel layer 606, and band-offset layer 630 may be formed using materials and processes similar for substrate layer 2, buffer layer 4, channel layer 6, and band-offset layer 32 respectively, according to descriptions of embodiments shown in
(65) Instead of pairs of upper and lower barrier layers, epitaxy structure 600 includes a cap layer 608 comprising a plurality of n selectively etchable sublayers, such as sublayer 611 with thickness t.sub.1, sublayer 612 with thickness t.sub.2, sublayer 618 with thickness t.sub.n-1, and sublayer 619 with thickness t.sub.n where n may be any even or odd integer greater than or equal to two, according to various embodiments of the present invention. For example, a multi-layer semiconductor structure 600 with a cap layer 608 having n=4 sublayers and an optional carrier-donor layer is the illustrative semiconductor structure 40 shown in
(66) In some embodiments, each i-th sublayer (1i<n) is selectively etchable with respect to the (i+1)-th sublayer below using some etching technique, thus the (i+1)-th sublayer below may serve as an etch stop for the i-th sublayer under the given etching technique. The n-th sublayer may further be selectively etchable with respect to band-offset layer 630, spacer layer 632, or any layer disposed directly below and/or in contact with the n-th sublayer. Spacer layer 632 may or may not be selectively etchable over band-offset layer 630. In some embodiments, each sublayer is selectively etchable with respect to both the sublayer above and the sublayer below using some etching technique, such as dry etching, wet etching, or a combination of dry etching and wet etching. For example, selectively etchable sublayers may be classified into two types. All odd sublayers counting from the first sublayer 611 may be formed of a material that is selectively etchable with respect to even sublayers by a first etching technique, such as dry etching, while all even sublayers counting from the second sublayer 612 may be formed of a material that is selectively etchable with respect to odd sublayers by a second etching technique, such as wet etching, or vice versa. The n-th sublayer may further be selectively etchable with respect to band-offset layer 630, spacer layer 632, or any layer disposed directly below and/or in contact with the n-th sublayer, using a dry etch process, a wet etch process or a combination thereof. The n-th sublayer may be etched at a faster rate the layer below, and the selectivity of the etch process may be greater than 3:1, such that the n-th sublayer is etched at a rate greater than three times as high as the rate at which layer below is etched. Spacer layer 632 may or may not be selectively etchable over sublayer 619 and/or band-offset layer 630. Band-offset layer 630 may or may not be selectively etchable over sublayer 619 and/or spacer layer 632. Each of the odd sublayers may have the same structure, composition, and/or thickness. Alternatively, each of the odd sublayers may have a different structure, composition, and/or thickness. Similarly, each of the even sublayers may have the same structure, composition, and/or thickness, or a different structure, composition, and/or thickness. In yet some other embodiments, each sublayer may be selectively etchable with respect to a selected subset of all other sublayers, using one or more etching techniques. For example, in some embodiments, selectively etchable sublayers may be classified into three types, where each type is repeated every three sublayers, and where each type is selectively etchable over the other two types using one or more etching techniques.
(67) More specifically, as discussed with respect to
(68) The reference herein to B.sub.wAl.sub.xIn.sub.yGa.sub.zN, B.sub.wAl.sub.xIn.sub.yGa.sub.zN material, or III-N material refers to a semiconductor material having nitride and one or more of boron, aluminum, indium and gallium. An Al.sub.xIn.sub.yGa.sub.zN material is a B.sub.wAl.sub.xIn.sub.yGa.sub.zN material where w=0. Examples of B.sub.wAl.sub.xIn.sub.yGa.sub.zN materials include, but are not limited to, GaN, AlN, AlGaN, AlInGaN, InGaN, and BAlInGaN, Al.sub.0.15Ga.sub.0.85N, and Al.sub.0.65Ga.sub.0.35N, by way of illustration. A B.sub.wAl.sub.xIn.sub.yGa.sub.zN material may include other materials besides nitride, boron, aluminum, indium and/or gallium. For example, a B.sub.wAl.sub.xIn.sub.yGa.sub.zN material may be doped with a suitable dopant such as silicon or germanium.
(69) In some embodiments, selective etchability of sublayers within cap layer 608 is achieved by alternating aluminum content or composition of adjacent or consecutive sublayers between a relatively high value or percentage and a relatively low value or percentage. In other words, selective etchability may be achieved by alternating between Al-light and Al-rich sublayers, or adjusting the value of x for material B.sub.wAl.sub.xIn.sub.yGa.sub.zN or Al.sub.xIn.sub.yGa.sub.zN as described above. In one example, consecutive or adjacent sublayers of cap layer 608 may have Al contents alternating between less than 0.5 inclusive and greater than 0.5 exclusive, less than 0.5 exclusive and greater than 0.5 inclusive, or less than 0.5 exclusive and greater than 0.5 exclusive. In other examples, consecutive or adjacent sublayers of cap layer 608 may have Al content alternate between less than 0.25 and greater than 0.5, less than 0.35 and greater than 0.5, or less than 0.35 and greater than 0.65, inclusive or exclusive. In some embodiments, at least one of the plurality of selectively etchable sublayers has an Al content great than 0.5. In addition, at least one of the selectively etchable sublayers may have a non-zero Ga content (0<z1). Moreover, B, Al, In, and Ga compositions in each type of sublayers may not necessarily be the same. For example, when n is odd, first sublayer 611 and n-th sublayer 619 may have x=0.1 and x=0.2 respectively, while second layer 612 and (n1)-th sublayer 618 may have x=0.6 and x=0.7 respectively. Similarly, when n is even, first sublayer 611 and (n1)-th sublayer 618 may have x=0.1 and x=0.2 respectively, while second sublayer 612 and n-th sublayer 619 may have x=0.6 and x=0.7 respectively.
(70) In
(71) Furthermore, optional spacer layer 632 shown in
(72)
(73) Similar to the exemplary transistor shown in
(74) The E/D-mode integration shown in
(75) To form a recess such as the gate recess for transistor 710, a suitable masking process may be used to define a region to be etched. A first etching process may be performed to selectively etch the material of first selectively etchable layer 611 with respect to the material of second selectively etchable layer 612. The selectivity of the etch process used in the first etching step may be greater than one, such that first selectively etchable layer 611 is etched at a faster rate than second selectively etchable layer 612. In some embodiments, the selectivity of the etch process used in the first etching step may be greater than 3:1, such that first selectively etchable layer 611 is etched at a rate greater than three times as high as the rate at which second selectively etchable layer 612 is etched. The first etching technique may include a dry etching technique (e.g., dry plasma etching, or reactive ion etching (RIE)). If first selectively etchable layer 611 includes GaN, a fluorine-based etching process may be used. Second selectively etchable sublayer 612 may serve as an etch stop to stop the dry etching process at its upper surface. The dry etching process may damage the upper surface of second selectively etchable sublayer 612, creating a damaged region. However, in some embodiments the dry etching process may not produce any significant damage.
(76) Next, a second etching step may be performed using a second etching technique to remove a portion of second selectively etchable sublayer 612, through a window formed by the removal of a region of first selectively etchable sublayer 611 in the first etching step. In some embodiments, the etch process used in the second etching step may selectively etch second selectively etchable sublayer 612 with respect to a layer overlying second selectively etchable sublayer 612 and which may be in contact with second selectively etchable sublayer 612, such as first selectively etchable sublayer 611, for example. In some embodiments, the etch process used in the second etching step may selectively etch second selectively etchable sublayer 612 with respect to a layer below second selectively etchable sublayer 612 which may be in contact with second selectively etchable sublayer 612, such a third selectively etchable sublayer below, and/or spacer layer 632, or band-offset layer 630. The selectivity of the etching of second selectively etchable sublayer 612 with respect to first selectively etchable sublayer 611 and/or the third selectively etchable sublayer, spacer layer 632, or band-offset layer 630 may be greater than one, such that the rate of etching of second selectively etchable sublayer 612 is greater than that of first or third selectively etchable sublayers, for example. In some embodiments, the selectivity may be greater than 3:1, such that second selectively etchable sublayer 612 is etched at a rate greater than three times as high as the first or the third selectively etchable sublayers. In some embodiments, the etching technique used in the second etching step may be a wet etching technique.
(77) Once the gate recess is formed through first selectively etchable sublayer 611 and second selectively etchable sublayer 612, the first and second etching techniques, or dry etching and wet etching processes as discussed above, may be performed iteratively to remove consecutive or adjacent selectively etchable sublayers, until gate recess depth 713 is achieved. The last etching step to remove a portion of sublayer 619 may be either dry etching or wet etching. In the exemplary structure 700, gate recess depth 713 is approximately the summation of layer thicknesses t.sub.1, t.sub.2, . . . , and t.sub.n. Gate dielectric 714 and gate 712 may be formed in the resulting gate recess for transistor 710, using processes similar to those for depositing gate dielectric 18 and gate 20 shown in FIG. 1D. For planar-gate transistor 720, gate dielectric 724 and gate 722 may be formed concurrently with, or separately from, gate dielectric 714 and gate 712 of transistor 710. Source contacts 716 and 726, and drain contacts 718 and 728 may be formed before or thereafter.
(78)
(79) In various embodiments, ohmic contacts may be made with or without recesses, and either before or after the formation of the gate regions to accommodate for other process considerations such as thermal budget, ohmic contact performance and process complexity. In the example shown in
(80) To fabricate structure 800 shown in
(81) For ohmic contacts, ohmic recesses for contacts 816 and 818 may be formed before gate electric and gate metal deposition. For example, ohmic recesses may be formed together or concurrently with one of the gate recesses, if the recess depths are the same. Furthermore, ohmic metal deposition, patterning and optional thermal annealing steps may be performed either before or after gate dielectric and gate metal deposition, or gate electrodes formation, to allow optimization of thermal budgets and process complexities. In some embodiments, the recessed structure is subjected to a thermal annealing at a temperature below 1500 C., before gate electrode and ohmic contact deposition or formation. In some embodiments, metal layers are deposited over ohmic contacts and formed transistors, for interconnecting the ohmic contacts, or as field plates for managing electric field in the transistors.
(82)
(83)
(84) One advantage of using structures such as 900 in
(85) Although only two types of transistors are discussed in the illustrative examples shown in
(86) While
(87)
(88) More specifically,
(89)
(90)
(91) Illustrative DC (direct current) characteristics of integrated E/D-mode transistors, with or without gate or ohmic recesses as illustrated by
(92) As an other example of integrated devices that may be implemented using the multi-layer semiconductor structure disclosed herein,
(93) In this particular example, a dedicated carrier-donor layer 610 is included in the multi-layer structure, and formed over the top sublayer 611 of cap layer 608. However, in other cases, carrier-donor layer 610 may be optional and omitted. In addition, structures and techniques as described herein are not limited in this respect, and one or more carrier-donor layers such as carrier-donor layer 610 may be formed within cap layer 608, inserted between selectively etchable sublayers, or in another location. In some embodiments, carrier-donor layer 610 may be formed of the same material as that of top sublayer 611. Moreover, although not shown in
(94) Furthermore, although two selectively etchable sublayers 611 and 619 are shown in this example for illustrative purposes, in various embodiments, any non-zero number of selectively etchable sublayers may be present, where each sublayer is selectively etchable over or with respect to a sublayer immediately below or above, or is selectively etchable over both sublayers below and above. As discussed with respect to
(95) To fabricate transistor 1600, exemplary processes described with respect to transistors 710 and 720 shown in
(96)
(97)
(98)
(99) In addition to transistors as discussed herein, the multi-layer semiconductor structure as disclosed may be applied to other integrated devices as well.
ADDITIONAL ASPECTS
(100) Use of ordinal terms such as first, second, third, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.
(101) Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of including, comprising, or having, containing, involving, and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. For example, an apparatus, structure, device, layer, or region recited as including, comprising, or having, containing, involving, a particular material is meant to encompass at least the material listed and any other elements or materials that may be present. The partially open-ended phrase consisting essentially of is meant to encompass essentially the material listed and does not preclude the presence of relatively small quantities of other materials, including the presence of dopants.
(102) Various aspects of the apparatus and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing description and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments. In other words, although the present invention has been described with reference to specific exemplary embodiments, it will be evident that the various modification and changes can be made to these embodiments without departing from the broader scope of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than in a restrictive sense. It will also be apparent to the skilled artisan that the embodiments described above are specific examples of a single broader invention which may have greater scope than any of the singular descriptions taught. There may be many alterations made in the descriptions without departing from the scope of the present invention.