Method of fabricating a micro machined channel

Abstract

The invention relates to a method of fabricating a micro machined channel, comprising the steps of providing a substrate of a first material and having a buried layer of a different material therein, and forming at least two trenches in said substrate by removing at least part of said substrate. Said trenches are provided at a distance from each other and at least partly extend substantially parallel to each other, as well as towards said buried layer. The method comprises the step of forming at least two filled trenches by providing a second material different from said first material and filling said at least two trenches with at least said second material; forming an elongated cavity in between said filled trenches by removing at least part of said substrate extending between said filled trenches; and forming an enclosed channel by providing a layer of material in said cavity and enclosing said cavity.

Claims

1. Method of fabricating a micro machined channel, comprising the steps of: Providing a substrate of a first material and having a buried layer of a different material therein; Forming at least two trenches in said substrate by removing at least part of said substrate, wherein said trenches are provided at a distance from each other and wherein said trenches at least partly extend substantially parallel to each other, wherein said trenches extend towards said buried layer; Forming at least two filled trenches by providing a second material different from said first material and filling said at least two trenches with at least said second material; Forming an elongated cavity in between said filled trenches by removing at least part of said substrate extending between said filled trenches; Forming an enclosed channel by providing a layer of material in said cavity and enclosing said cavity; and Providing walls of the channel with sidewall heating.

2. Method according to claim 1, wherein after said step of forming an elongated cavity, said cavity is at least partly bound by said filled trenches.

3. Method according to claim 1, wherein said step of forming at least two trenches comprises etching said two trenches.

4. Method according to claim 1, wherein said step of forming at least two filled trenches comprises a low pressure chemical vapor deposition step.

5. Method according to claim 1, wherein said second material comprises polycrystalline or monocrystalline silicon.

6. Method according to claim 1, wherein said step of forming an enclosed channel comprises a low pressure chemical vapor deposition step.

7. Method according to claim 1, wherein in forming said enclosed channel by providing a layer of material, said layer of material comprises low-stress silicon rich silicon nitride.

8. Method according to claim 1, wherein said method comprises the step of defining an exterior of said channel by removing at least part of said substrate.

9. Method according to claim 8, wherein said removing comprises a release etching step.

10. Method according to claim 1, wherein said substrate comprises a silicon on insulator wafer.

11. Method according to claim 10, wherein said substrate comprises a device layer, a buried oxide (BOX) layer and a handle layer.

12. Method according to claim 1, wherein said step of forming an elongated cavity comprises etching said elongated cavity.

13. Method according to claim 12, wherein said etching comprises isotropic etching of said substrate.

14. Method according to claim 1, further comprising a masking step for creating a mask.

15. Method according to claim 14, wherein said masking comprises wet thermal oxidation of the substrate.

16. Method according to claim 14, comprising the step of patterning said mask.

17. Method according to claim 16, wherein said patterning comprises reactive ion etching.

Description

(1) The invention will next be explained by means of the accompanying drawings and description of the figures. In the figures different stages of fabricating a micro machined channel from a substrate are shown, and in particular:

(2) FIG. 1—a schematic cross sectional view of a substrate, such as a Silicon on Insulator wafer, wherein a hard mask is formed using wet thermal oxidation;

(3) FIG. 2—Patterning of the hard mask via RIE, and trench formation via BOSCH DRIE etching;

(4) FIG. 3—BOX protection with parylene-C via CVD;

(5) FIG. 4—Parylene-C etching with O.sub.2 plasma and hard mask stripping in BHF;

(6) FIG. 5—Parylene-C stripping in piranha, dry thermal oxidation of SI to create isolation layer, and trench filling with polycrystalline Si via LPCVD;

(7) FIG. 6—Patterning of isotropic etch mask with RIE;

(8) FIG. 7—Isotropic etching of Si to create channels;

(9) FIG. 8—Deposition of low-stress SiRN via LPCVD;

(10) FIG. 9—Release Etching of channels with isotropic etching.

(11) FIGS. 1-9 schematically show an embodiment of the method of fabricating a micro machined channel 101 according to the invention. In general, the method comprises the steps of: Providing a substrate 11 of a first material (FIG. 1) and having a buried layer 14 therein of a different material; Forming at least two trenches 21, 22 in said substrate 11 by removing at least part of said substrate 11 (FIG. 2), in particular up to the buried layer 14; Forming at least two filled trenches 31, 32 by providing a second material different from said first material and filling said at least two trenches 21, 22 with at least said second material (FIG. 5); Forming an elongated cavity 51 in between said filled trenches 31, 32 by removing part of said substrate 11 extending between said filled trenches 31, 32 (FIG. 7); and Forming an enclosed channel 5 by providing a layer of material 61 in said cavity 51 and enclosing said cavity 51 (FIG. 8).

(12) In an embodiment, said enclosed channel 5 may be partially released from said substrate by defining an exterior of said channel 5 by removing at least part of said substrate 11 (FIG. 9). By removing part of said substrate for defining an exterior of said channel, the fabrication of free-hanging, mechanical stable and thermally isolated channels may be realized.

(13) The process will now be described in more detail.

(14) FIG. 1 shows that an SOI wafer 11 (having for example a 50 μm device layer 13, a 200 nm BOX layer 14, and a 400 μm handle layer 15) is oxidized via wet thermal oxidation (for instance at 1150° C.) for creating a hard mask 12. This SiO.sub.2 layer 12 is patterned with 3 μm wide trenches to create the actual mask 12.

(15) FIG. 2 shows that the high aspect ratio trenches 21, 22, which may for example be 3 μm wide, are etched completely down to the BOX layer 14 with a Bosch process using a DRIE plasma system.

(16) Then, referring to FIG. 3, the trenches 21, 22 are filled with a polymer 71, in particular parylene-C, which in the embodiment shown is deposited as a conformal 2 μm thick layer via CVD. The chosen thickness is, in this case, more than half the trench 21, 22 width, ensuring full filling of the trenches 21, 22.

(17) FIG. 4 shows that the surface parylene-C is etched back using an O2 plasma in a barrel etcher. Advantageously, etching on the surface has a higher rate than etching inside the trenches, which means that the SiO.sub.2 hard mask 12 is stripped in BHF (7:1 NH.sub.4F:HF) whilst protecting the buried (BOX) layer 14. The remaining polymer 71 is stripped away in piranha solution (3:1 H.sub.2SO.sub.4:H.sub.2O.sub.2), for instance at 90° C.

(18) However, the step of filling the trenches 21, 22 with a polymer 71, in particular parylene-C, can in principle be omitted. Therein, the hard mask 12 is removed and it is accepted that the BOX layer 14 in the trenches 21, 22 is etched.

(19) In the next step, shown in FIG. 5, the trenches are refilled with a multilayer system consisting of a thin SiO.sub.2 etch-stop layer 35 grown via dry thermal oxidation and subsequent filling via LPCVD of polycrystalline Si 36. This way, filled trenches 31, 32 are obtained. Of course, other materials such as Silicon Nitride are conceivable as well. In that case, the Silicon Nitride may already function as an etch-stop 5 layer for some etching techniques, meaning that the additional SiO.sub.2 35 layer is not necessary anymore. Thus in effect, the trench may be filled, in an embodiment, with a filling material, which may be a layered material or a single material. The filling material may function as an etch stop layer for specific etching techniques.

(20) Preferably, the polycrystalline Si 36 is then removed from the surface of the wafer 11 by means of isotropic silicon etching to prevent problems when etching the cavity 51.

(21) As shown in FIG. 6 a slit pattern 41, which will be used as isotropic etch mask, is etched between two adjacent trenches 31, 32 with RIE.

(22) Now referring to FIG. 7, it is shown that the Si of the device layer 13 is etched away through the slits 41 with an isotropic gas phase process, stopping on the SiO.sub.2 etch-stop 35. This way the cavity 51 is formed.

(23) After etching away the Si 13 for forming the cavity 51, the inner channel wall of the channel 5 is formed via LPCVD of low-stress silicon rich silicon nitride 61, which is conformally grown to a thickness slightly more than half the slit 41 width, ensuring full closure of all slits 41 (see FIG. 8).

(24) As an optional last step, the channels are completely etched free from the top and the bottom, with a suitable etching process, for example an isotropic gas phase etch or semi-isotropic RIE etch.

(25) The TASCT process according to an embodiment of the invention may start with a single SOI wafer and may use XeF.sub.2 to etch channel 5 through slits 41 arrays and release channel 5 from the bulk substrate 11, due to XeF.sub.2 has fast etch rate and high selectivity for silicon over silicon dioxide. In the depth direction, the Box layer 14 can act as the silicon etch stop through the slits 41, therefore channels 5 are confined in the device layer 13. In the planar direction, high aspect-ratio trenches 21, 22 are etched in the device layer 13, all the trench walls 31, 32 are coated with thin layer of thermal oxide 35 as XeF.sub.2 etch stop. Therefore, within the trenches 31, 32 confined device layer 13, through the slits 41 arrays channels 5 can be etched and result with the designed shape and sizes. Outside the trench confined channels, the handle layer 15 and device layer 13 silicon can be etched by XeF.sub.2 until reaching the etch stop, which may be the thermal oxide trench walls 35.

(26) In an embodiment, the side walls of the channel 5 formed may be given a heater function. To this end, highly doped device layer silicon 13 is encapsulated/sandwiched within two refilled trenches 31, and these trenches all have thermal oxide coatings 35 and can provide electrical isolation from the bulk silicon substrate 13. In this way, by heating up the channel from the sidewall directions, thermal loss to the environment can be minimized.

(27) The channel 5 top and bottom surfaces may be made from low-stress SiRN membranes, they can be connected by the pillars and sidewalls made from trenches 31, 32 to achieve good mechanical strength. Therefore these thin membranes can be several millimeters long or wide.

(28) The top and bottom membrane thickness may be determined by the width of the rectangular slits 41. Heaters and sensors can be placed on top of the channel ceiling surface to efficiently heat up the channel 5 from the top and sense temperature profile. The bottom membrane may be made very thin and transparent which may be beneficial for observing processes in the micro channel. For example, when used as a combustion channel, the transparency gives good access to microscopic views of flame location in the channel.

(29) The method according to the invention allows for fabricating mechanically stable, thermally isolated microfluidic channels 5 with silicon heaters embedded in the sidewalls, using trench-assisted surface channel technology (TASCT).

(30) Sidewall heating results in highly uniform heating while allowing high heating powers because of the relatively large cross-sectional area (20 μm×50 μm) of the silicon heaters. In demonstrator devices a maximum temperature of 400° C. was reached at a heating power of 1.4 W, limited by mechanical stress.

(31) The method allows a wide range in channel widths and heater thicknesses. The latter allows variation of the power dissipation and thus the temperature profile along the length of the channel.

(32) In most fabrication technologies for suspended microchannels, heating is only possible using heaters on top of the channels 5, resulting in temperature gradients within the cross-section of the channel 5. The method according to the invention allows to incorporate resistive heaters inside the sidewalls of the channels 5, enabling heating from two sides which results in a more uniform temperature profile.

(33) Furthermore, the relatively large cross-sectional area of the heaters allows large heating powers. Important applications are high-temperature physical parameter sensing and (bio)microreactors. In most applications, flow rates up to 1 g h-1 (±0.3 mL s-1) are desired.

(34) Within the method the final shape of the microchannels 5 is independent of the actual channel etch. The outline is defined by using refilled trenches as etch stops. The final channel 5 cross-section is square or rectangular, with a height defined by the used SOI wafer and a width defined by the design. Besides the possibility of sidewall heating, the process also allows in-channel structures like strengthening pillars or mixing-enhancers.

(35) In an exemplary embodiment, straight, 8,500 μm long, channels with sidewall heaters and resistive Pt temperature sensors can be fabricated in a p-type SOI wafer (1e-3-1e-2 Ωcm) via the proposed method. The fabrication may then for instance comprise three stages:

(36) 1) Microfluidic channels are fabricated by Bosch etching 50 μm deep trenches in the device layer (DL) and refilling them with a multi-layer system, Bosch etching of inlets in the handle layer (HL), reactive ion etching (RIE) of a slit pattern in the hard mask on the DL, isotropically etching the channels with XeF.sub.2, and as final step the formation of the inner wall of the microfluidic structure by low-pressure chemical vapor deposition (LCPVD) of SiRN.

(37) 2) Sensor structures and the interfacing of the sidewall heaters are fabricated by first etching openings to the sidewall heaters via RIE, directly followed by sputtering of Ta and Pt and patterning this via ion beam etching. Then, a capping layer of SiN.sub.x is deposited via plasma-enhanced chemical vapor deposition and patterned with RIE.

(38) 3) Microchannels are suspended as final step via a multi-step approach in which the silicon in the device and handle layers is etched away by XeF.sub.2.

(39) The method according to the invention also allows springs and suspensions structures to be made. In a first embodiment, channel structure or solid silicon in the device layer may be used, as they are defined by trenches, therefore any desired shapes such as serpentine springs can be made. Second choice is using a thin membrane of 500 nm thick TEOS, which functions as the slits hard mask, as the spring or suspension by etching all the silicon beneath it by XeF.sub.2. In conclusion, with the method according to the invention a lot of freedom in designing the desired shape and size for the flexure and suspension is possible, due to the high selectivity of XeF.sub.2 over silicon than silicon dioxide.

(40) In general, many applications for the channel according to the invention are possible. The channels obtainable with the invention may be made with a relatively large cross-sectional area, and with high precision, which is advantageously in terms of fluid dynamics (boundary layer, laminar/turbulent flow, flow development).

(41) One particular application may be the fabrication of a small sized combustion chamber to burn gas blends on chip and measure adiabatic flame temperature. With additional integration of a micro-Coriolis sensor, it is possible to determine the Wobbe Index of any gas blend. In particular when a free-hanging channel is used, thermal heat loss to the environment may be minimized to ensure to be smaller than the heat generated from combustion. In general, a large channel with bigger cross-sectional area may be formed, as this is advantageous to maintain a continuous flame propagation to obtain the adiabatic flame temperature. To overcome the radical quenching, channel inner wall materials may be made chemically inert to avoid radical adsorption and further recombination to cause radical extinction.

(42) To provide thermal isolation, relatively large cavities may furthermore be provided underneath and to the sides of the combustion chamber. The cavity underneath may have a height of for instance up to 400 μm, such as 200-400 μm, for instance 300-400 μm. The cavities to the side may have a width (each) of for instance up to 400 μm, such as 200-400 μm, for instance 300-400 μm.