Optical switch with all-optical memory buffer

Abstract

Consistent with some disclosed embodiments, an optical switch includes: a scheduler; and a buffer for buffering an optical packet including, arranged in a circuit, a clock generator for generating a clock signal, an optical unbalanced Mach Zehnder Interferometer (MZI) and a fiber delay line (FDL) having an FDL length, wherein the optical packet has an optical packet signal, wherein the scheduler is configured to insert the optical packet into the buffer and to determine a number of circulations of the optical packet through the circuit, wherein the MZI modulates the clock signal based on the optical packet signal to create a reshaped optical packet after each circulation of the optical packet through the circuit, and wherein the FDL introduces a delay in the optical packet proportional to the FDL length.

Claims

1. An optical buffer for buffering an optical packet, comprising: a clock generator for generating a clock signal; an optical unbalanced Mach Zehnder Interferometer (MZI); a fiber delay line (FDL) having an FDL length; a scheduler; and an exit semiconductor optical amplifier (SOA) at an exit of the optical buffer, wherein the clock generator, the optical unbalanced MZI, the FDL, the scheduler and the exit SOA are arranged in a circuit, wherein the optical packet has an optical packet signal, wherein the scheduler is configured to insert the optical packet into the optical buffer and to determine a number of circulations of the optical packet through the circuit, and to activate the exit SOA to release the optical packet from the optical buffer, wherein the MZI includes a pair of MZI semiconductor optical amplifiers (SOAs) to modulate the clock signal based on the optical packet signal to create a reshaped optical packet after each circulation of the optical packet through the circuit, and wherein the FDL introduces a delay in the optical packet proportional to the FDL length, and wherein the circuit comprises an optical dispersion management module to compensate for dispersion introduced in the FDL, and wherein the clock and optical packet are fed into each of the pair of MZI SOAs in counter-propagating directions for causing cross gain modulation (XGM) and cross phase modulation (XPM) of the clock signal and of the optical packet signal, and wherein the reshaped optical packet is a wavelength converted optical packet, and wherein the clock generator includes a tunable laser, and wherein the scheduler is further configured for powering down the exit SOA and the tunable laser following release of the optical packet to thereby empty the optical buffer.

2. The optical buffer of claim 1, wherein the circuit comprises a semiconductor optical amplifier (SOA) to compensate for losses introduced in the FDL.

3. The optical buffer of claim 1, wherein the clock generator includes an electro-optical modulator configured for modulating a laser output of the tunable laser based on the clock signal.

4. The optical buffer of claim 1, further comprising a WDM multiplexer and a WDM demultiplexer for sharing the FDL therewith between multiple buffers.

5. The optical buffer of claim 1, wherein the FDL is one of a single core fiber optic cable or a multi-core fiber optic cable.

6. The optical buffer of claim 1, wherein the MZI SOAs are quantum dot SOAs.

7. The optical buffer of claim 1, further comprising an optical packet splitter for directing the optical packet through the pair of the MZI SOAs, wherein the optical packet splitter splits a signal strength unequally between the pair of MZI SOAs.

8. The optical buffer of claim 1, wherein the scheduler is further configured to time the activation of the exit SOA such that it coincides with an nT time period, where n is an integer and T is an optical packet circulation time through the optical buffer, such that the optical packet is released through the exit SOA from a beginning to an end of the optical buffered optical packet, and such that release of a partial optical packet through the exit SOA is prevented.

9. The optical buffer of claim 1, wherein the released optical packet is a wavelength converted optical packet.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Aspects, embodiments, and features disclosed herein will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. In the drawings and descriptions set forth, identical reference numerals indicate those components that are common to different embodiments or configurations:

(2) FIG. 1 shows a block diagrams of an optical packet switch;

(3) FIGS. 2A-2B show block diagrams of an optical packet switch according to some embodiments;

(4) FIGS. 2C-2D shows operation of an optical packet switch according to some embodiments;

(5) FIGS. 3A-3C show block diagrams of an optical packet switch according to some embodiments.

DETAILED DESCRIPTION

(6) Embodiments disclosed herein relate to systems, devices and methods that enable high data rate optical packet switches with all-optical packet buffering.

(7) FIGS. 2A-2B show an all-optical packet switch according to some embodiments. As shown in FIG. 2A a NN optical packet switch 210 may include N input ports 212-1 . . . 212-N and N output ports 214-1 . . . 214N. Input data signals 102 may feed optical data packets into input ports 212 and these optical data packets may be routed to one of output ports 214 to be output as output data signals 104. Data signals 102, 104 are packet-based optical data signals. It should be appreciated that although optical switch 210 includes N input ports 212 and N output ports 214, not all of the input ports 212 and output ports 214 are connected to other communication devices. Switch 110 includes a scheduler 216 for directing of data packets within switch 210.

(8) Packets may be directed by scheduler 216 into a buffer 220 to slow the throughput of a packet in order to prevent discarding of packets or packet loss due to contention. Scheduler 216 is a computing device as defined herein. Scheduler 216 is in data communication with the components of buffer 220 as described further below.

(9) In some embodiments, the components of optical packet switch 210 may be provided as an integrated circuit (IC) on a shared semiconductor substrate. It should be appreciated that other switch internal components aside from scheduler 216 and buffer 220 may be required for the operation of switch 210 but these are not shown in the figures in order to reduce the complexity of the figures. The components of buffer 220 are described in more detail with reference to FIG. 2B and may include a clock generator 221, an optical unbalanced Mach Zehnder Interferometer (MZI) 245 and an FDL 247 configured in a circuit arrangement. The components 221, 245, and 247 of buffer 220 as described below are exemplary implementations and other implementations may be contemplated. In some embodiments, the components of buffer 220 may be formed on a common semiconductor as an IC.

(10) In clock generator 221, a tunable continuous wave (CW) laser 222 may provide a source laser signal (herein designated .sub.2) that may be modulated by an EO modulator 228 based on the signal from a clock 226 to form an optical clock signal (herein designated .sub.2 CLOCK). The wavelength of laser 222 may be chosen by scheduler 216 according to the output port wavelength required for switching purposes as described further below. The period of clock 226 may be substantially the same as the data rate of signals 102. A driver 224 may provide power to CW laser 222.

(11) The optical clock signal from clock generator 221 may be fed into an unbalanced Mach Zehnder Interferometer (MZI) 245 acting as an optical logical AND gate as described, for example, in Singh, Pallavi, et al. All-Optical Logic Gates: Designs, Classification, and Comparison. Advances in Optical Technologies (2014), hereby incorporated by reference. Within MZI 245, the optical clock signal may be split by a splitter 230 into an upper branch 231 and a lower branch 233. The splitting ratio of splitter 230 into upper branch 231 and lower branch 233 may be controlled by scheduler 216 to optimize the functionality of buffer 220. Non-limiting examples of split ratios include 50/50, 90/10 and 80/20. In some implementations, a clock generator 221 may be implemented using a tunable pulsed laser (not shown).

(12) In MZI 245, the outputs of splitter 230 may be connected to circulators 232-1 and 232-2. Circulators 232-1 and 232-2 may in turn be connected to, respectively, semiconductor optical amplifiers (SOAs) 234-1 and 234-2. In FIGS. 2B-2D, the circulators are shown as having a clockwise or anticlockwise direction, but it should be appreciated that the direction employed will be functional. SOAs 234-1 and 234-2 may be respectively provided with power by, respectively, drivers 236-1 and 236-2. In some embodiments, SOAs 234-1 and 234-2 may be quantum dot SOAs.

(13) An input packet (herein designated .sub.1-S1) to be buffered is provided from a port 212 that may be in communication with MZI 245 at coupler 238. Coupler 238 may be connected to a splitter 240. The output of splitter 240 may be connected to circulators 242-1 and 242-2. The splitting ratio of splitter 240 may be controlled by scheduler 216 in order to optimize the functionality of buffer 220. Non-limiting examples of split ratios include 50/50, 90/10 and 80/20. Circulators 242 may include ports connected to SOAs 234 and to a coupler 244. Coupler 244 may combine the signals from circulators 242.

(14) The output of MZI 245 at coupler 244 may be connected to a splitter 246. Splitter 246 may be connected to SOA 252 and FDL 247. SOA 252 may be connected to one of output ports 214.

(15) In some embodiments, MZI 245 may be implemented using a co-propagating scheme including tunable filters (not shown). In some embodiments, MZI 245 may be replaced with an ultra-nonlinear interferometer (UNI) configuration (not shown). In some embodiments, MZI 245 may be replaced with Sagnac interferometer (SI) gates.

(16) The length of FDL 247 substantially determines the delay introduced by a single circulation of a packet through FDL 247 in buffer 220 and hence determines the optical buffer memory size. As a non-limiting example, an FDL of 1 km will introduce a delay of approximately 5 s. For a data rate of 100 Gbps, such a delay translates to an approximate optical buffer memory size of 0.5 Mbit.

(17) The output of FDL 247 may be connected to an SOA 248. The output of SOA 248 may be connected to an optical dispersion management (DM) module 250. DM 250 may correct for dispersion management introduced by FDL 247. In some embodiments, DM 250 may include chirped Bragg gratings controlled by a temperature controller (not shown). The output of DM 250 may be connected to coupler 238.

(18) In buffer 220, scheduler 216 may monitor and control all components and provide for automatic adjustment of adjustable components such as laser 222, SOA 234-1, SOA 234-2, SOA 248, DM 250, drivers 224, 236 and SOA 252. Scheduler 216 may be configured to ensure the synchronization of the clock signal and optical packet to be buffered.

(19) The signal path within buffer 220 is illustrated in FIGS. 2C and 2D. In use, as shown in FIG. 2C, an optical clock signal at a second wavelength (herein designated .sub.2 CLOCK) may be fed into MZI 245 at splitter 230. Splitter 230 may introduce a phase shift of /2 into the clock signal such that upper branch 231 carries the original clock signal .sub.2 CLOCK while lower branch 233 carries the phase shifted clock signal (herein designated .sub.2 CLOCK-PS) or vice versa. The clock signals .sub.2 CLOCK and .sub.2 CLOCK-PS may pass through circulators 232-1 and 232-2 into SOAs 234-1 and 234-2 respectively.

(20) An input optical data packet at a first wavelength (also referred to herein as a data signal and herein designated .sub.1-S1) to be buffered may be provided from port 212 to MZI 245 at coupler 238. Scheduler 216 directs packet .sub.1-S1 into buffer 220 for a period determined by scheduler 216 before the buffered packet is released from buffer 220 to an output port 214. Since the output port 214 may operate at a different wavelength to the input port, switch 210 may provide for wavelength conversion as part of the buffering process. The wavelength chosen by scheduler for tunable laser 222 may be the wavelength of the destination output port 214.

(21) Packet .sub.1-S1 may then be directed by splitter 240 towards both of circulators 242-1 and 242-2. In some embodiments, splitter 240 may split the signal strength unequally between the two branches to thereby unbalance MZI 245. Non-limiting examples of split ratios include 90/10 and 80/20.

(22) Circulators 242 may direct packet .sub.1-S1 into SOAs 234 in a counter-propagating direction to that of .sub.2 CLOCK and .sub.2 CLOCK-PS. The interaction of data packets .sub.1-S1 with the clock signals to .sub.2 CLOCK and .sub.2 CLOCK-PS may result in cross-gain and cross phase modulation (XGM, XPM) of the clock signals with the packet signals resulting, in SOA 234-1, in a modulated clock signal (herein designated .sub.2-XGM and, in SOA 234-2, in a phase shifted modulated clock signal (herein designated .sub.2-XGM-PS). It should be appreciated that each XGM clock .sub.2-XGM and .sub.2-XGM-PS is essentially a partially reshaped wavelength-converted data packet. Similarly, in the counter-propagating direction, data packets may be modulated via XGM and XPM with the clock signals resulting in .sub.1-XGM and .sub.1-XGM-PS. The counter-propagating modulated data packets .sub.1-XGM and .sub.1-XGM-PS may be directed by circulators 232 into terminators 235.

(23) The modulated clock signals .sub.2-XGM and .sub.2-XGM-PS may be combined in coupler 244 to form a reshaped, wavelength converted output packet, herein designated .sub.2-S1. Coupler 244 may introduce a further phase shift of /2 into .sub.2-XGM-PS for a complete phase shift of R in order to provide the required logical AND at the output (coupler 244) of MZI 245. The reshaped, wavelength converted output packet .sub.2-S1 of coupler 244 may be directed by splitter 246 to SOA 252 and FDL 247. When scheduler 216 determines that output packet .sub.2-S1 has completed a required buffering period, scheduler 216 may power on SOA 252 to thereby release packet .sub.2-S1 to one of connected output ports 214. It should be appreciated that scheduler 216 may time the opening (powering on) of SOA 252 such that it coincides with an nT time period, where n is integer and T is the packet circulation time through buffer 220, such that a buffered packet may be released through SOA 252 from the beginning to the end of buffered packet, and such that release of a partial packet through SOA 252 may be prevented. Once a packet has been released from buffer 220, laser 222 and SOA 248 may be powered off by scheduler 216 in order to empty buffer 220.

(24) Packet .sub.2-S1 traverses FDL 247 until SOA 248. SOA 248 may amplify the signal after FDL 247 to compensate for signal losses incurred in FDL 247. The amplified signal may further be passed through DM 250 to compensate for dispersion introduced by FDL 247.

(25) As shown in FIG. 2D, the output signal from DM 250, herein designated .sub.2-S1-REGEN, may be reintroduced into MZI 245 at coupler 238. Packet .sub.2-S1-REGEN may then be directed by splitter 240 towards both of circulators 242-1 and 242-2. In some embodiments, splitter 240 may split the signal strength unequally between the two branches to thereby unbalance MZI 245. Non-limiting examples of split ratios include 90/10 and 80/20.

(26) Circulators 242 may direct packet .sub.2-S1-REGEN into SOAs 234 in a counter-propagating direction to that of .sub.2 CLOCK and .sub.2 CLOCK-PS. The interaction of data packets .sub.2-S1-REGEN with the clock signals to .sub.2 CLOCK and .sub.2 CLOCK-PS may result in XGM and XPM of the clock signals with the circulated packet signals resulting, in SOA 234-1, in a modulated clock signal (herein designated .sub.2-XGM and, in SOA 234-2, in a phase shifted modulated clock signal (herein designated .sub.2-XGM-PS). It should be appreciated that each XGM clock .sub.2-XGM and .sub.2-XGM-PS may essentially be a partially reshaped circulated data packet. In the counter-propagating direction, data packets may be modulated via XGM and XPM with the clock signals resulting in .sub.2-XGM and .sub.2-XGM-PS. The counter-propagating modulated data packets .sub.2-XGM and .sub.2-XGM-PS may be directed by circulators 232 into terminators 235.

(27) The packet reshaping and regeneration process may thus enable several circulations of the packet through FDL 247, with the packet being effectively regenerated on each circulation.

(28) As with the first circulation (FIG. 2C), the modulated clock signals .sub.2-XGM and .sub.2-XGM-PS may be combined in coupler 244 to form a regenerated output packet, herein designated .sub.2-S1. Coupler 244 may introduce a further phase shift of /2 into .sub.2-XGM-PS for a complete phase shift of in order to provide the required logical AND at the output (coupler 244) of MZI 245. The regenerated output packet .sub.2-S1 of coupler 244 may be directed by splitter 246 to SOA 252 and FDL 247. When scheduler 216 determines that output packet .sub.2-S1 has completed a required buffering period, scheduler 216 may power on SOA 252 to thereby release packet .sub.2-S1 to one of output ports 214 as described above.

(29) As determined by scheduler 216, packet .sub.2-S1 may traverse FDL 247 for a second circulation until SOA 248. SOA 248 may amplify the signal after FDL 247 to compensate for signal losses incurred in FDL 247. The amplified signal may further be passed through DM 250 to compensate for dispersion introduced by FDL 247. The output signal from DM 250, herein designated .sub.2-S1-REGEN may be reintroduced into MZI 245 at coupler 238 for regeneration and release (through SOA 252) or further circulations.

(30) FIGS. 3A-3C show an all-optical packet switch according to some embodiments. As shown in FIG. 3A, a NN optical packet switch 310 is the same as packet switch 210 described above, but additionally may include multiple all-optical buffers 220-1, 220-2 . . . 220-M and a shared FDL 347. In some embodiments, shared FDL 347 may use a single core fiber optic cable. In some embodiments, shared FDL 347 may make use of multi-core fiber optic cable. In some embodiments, up to 64 wavelengths may be transmitted per fiber optic core in shared FDL 347.

(31) As shown in FIGS. 3B and 3C, shared FDL 347 may be shared by multiple optical buffers 220 using wavelength division multiplexing (WDM). A WDM multiplexer (mux) 312 may receive a signal from splitter 246-1 of buffer 220-1 and may combines the received signal with signals received from splitters 246 of other buffers 220 for transmission over shared FDL 347. Following transmission through shared FDL 347, a WDM demultiplexer (demux) 314 may split the multiplexed signals for transmission to SOA 248 of each of buffers 220.

(32) In the claims or specification of the present application, unless otherwise stated, adjectives such as substantially and about modifying a condition or relationship characteristic of a feature or features of an embodiment of the invention, are understood to mean that the condition or characteristic is defined to within tolerances that are acceptable for operation of the embodiment for an application for which it is intended.

(33) Implementation of the method and system of the present disclosure may involve performing or completing certain selected tasks or steps manually, automatically, or a combination thereof. Moreover, according to actual instrumentation and equipment of preferred embodiments of the method and system of the present disclosure, several selected steps may be implemented by hardware (HW) or by software (SW) on any operating system of any firmware, or by a combination thereof. For example, as hardware, selected steps of the disclosure could be implemented as a chip or a circuit. As software or algorithm, selected steps of the disclosure could be implemented as a plurality of software instructions being executed by a computer using any suitable operating system. In any case, selected steps of the method and system of the disclosure could be described as being performed by a data processor, such as a computing platform for executing a plurality of instructions.

(34) Although the present disclosure is described with regard to a computing device, or a computer, it should be noted that optionally any device featuring a data processor and the ability to execute one or more instructions may be described as a computing device, including but not limited to any type of personal computer (PC), a server, a distributed server, a master control unit, a virtual server, a cloud computing platform, a cellular telephone, an IP telephone, a smartphone, a smart watch or a PDA (personal digital assistant). Any two or more of such devices in communication with each other may optionally form a network or a computer network.

(35) It should be understood that where the claims or specification refer to a or an element, such reference is not to be construed as there being only one of that element. In the description and claims of the present application, each of the verbs, comprise include and have, and conjugates thereof, are used to indicate that the object or objects of the verb are not necessarily a complete listing of components, elements or parts of the subject or subjects of the verb.

(36) While this disclosure describes a limited number of embodiments, it will be appreciated that many variations, modifications, and other applications of such embodiments may be made. The disclosure is to be understood as not limited by the specific embodiments described herein, but only by the scope of the appended claims.