Abstract
An artificial neuron for a neuromorphic chip comprises a synapse with resistive memory representative of a synaptic weight. The artificial neuron comprises a read circuit, an integration circuit and a logic circuit interposed between the read circuit and the integration circuit. The read circuit is configured to impose on the synapse a read voltage independent of the membrane voltage and to provide an analogue value representative of the synaptic weight. The logic circuit is configured to generate from the analogue value a pulse having a duration. The integration circuit comprises an accumulator of synaptic weights at the terminals of which a membrane voltage is established and a comparator configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage. Moreover, it comprises a source of current controlled by the pulse to inject a current into the accumulator of synaptic weights during this duration.
Claims
1. An artificial neuron for a neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight, the artificial neuron including: an integration circuit that comprises a synaptic weights accumulator at terminals of which a membrane voltage is established; a comparator configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage; a read circuit configured to impose on the synapse a read voltage independent of the membrane voltage and to provide an analogue value representative of the synaptic weight, said analogue value being a duration; and a logic circuit interposed between the read circuit and the integration circuit, the logic circuit being configured to generate from said analogue value a duration representative pulse having said duration, wherein the integration circuit comprises a source of current controlled by said duration representative pulse to inject a current into the synaptic weights accumulator during said duration.
2. The artificial neuron according to claim 1, wherein the read circuit comprises a synaptic current accumulator, at least one comparator that compares a voltage at terminals of the synaptic current accumulator to a threshold to provide a comparison result and wherein the logic circuit is configured to generate said duration representative pulse from the comparison result.
3. The artificial neuron according to claim 1, wherein the at least one comparator of the read circuit comprises a first comparator to a first threshold and a second comparator to a second threshold and wherein the logic circuit is configured to determine an integration sign by using a signal representative of a sign of a presynaptic pulse and a piece of information relative to a synaptic weight sign determined by that of the first and second comparators that provides a positive comparison result.
4. The artificial neuron according to claim 1, wherein the at least one comparator of the read circuit comprises a first comparator to a first threshold and a second comparator to a second threshold and the logic circuit is configured in such a way that the duration of said duration representative pulse corresponds to a duration separating the exceeding of one of the first threshold and second thresholds and then the exceeding of the other of the first threshold and second thresholds.
5. The artificial neuron according claim 1, wherein, the synapse comprising a memory synaptic weight absolute value and a memory of synaptic weight sign, the read circuit comprises a circuit for binary reading the memory of synaptic weight sign and a circuit for analogue reading the memory of synaptic weight absolute value controlled by the circuit for binary reading.
6. A neuromorphic chip comprising a plurality of synapses with resistive memory arranged in an array of transverse lines and columns, each synapse having a terminal for propagation of a synaptic signal, the propagation terminals of the synapses of the same column being connected to each other and connected to an artificial neuron according to claim 1.
7. The neuromorphic chip according to claim 6, wherein each synapse comprises an excitatory component and an inhibitory component connected in series by the propagation terminal of the synapse.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Other aspects, goals, advantages and features of the invention will be clearer upon reading the following detailed description of preferred embodiments of the latter, given as a non-limiting example, and made in reference to the following drawings above:
(2) FIG. 1 discussed above shows a known synaptic array, formed of 1T1R cells;
(3) FIG. 2 discussed above shows a known synaptic array, formed of 1S1R cells;
(4) FIG. 3 discussed above is a schematic drawing which illustrates a known implementation of an artificial neuron in the form of an integrate-and-fire neuron;
(5) FIG. 4 discussed above is a schematic drawing which shows how the voltage across a presynaptic neuron and the membrane voltage are defined;
(6) FIG. 5 is a functional diagram of an artificial neuron according to the invention;
(7) FIG. 6 illustrates an excitatory or inhibitory synapse that can be used in the context of the invention;
(8) FIG. 7 shows the impulse response of the synapse of FIG. 6;
(9) FIGS. 8 and 9 provide examples of integration of the synapse of FIG. 6 in a synaptic array;
(10) FIGS. 10 and 11 provide another example of an excitatory or inhibitory synapse that can be used in the context of the invention;
(11) FIGS. 12 and 13 are diagrams of artificial neurons having an accumulator of synaptic current in the read circuit and an accumulator of synaptic weights in the integration circuit and for which the analogue value representative of the synaptic weight provided by the read circuit to the integration circuit is a voltage;
(12) FIG. 14 shows another example of a neuron for which the analogue value is also a voltage;
(13) FIG. 15 shows a neuron according to the invention for which the analogue value is also a duration;
(14) FIG. 16 illustrates another operating mode of the neuron of FIG. 15;
(15) FIGS. 17, 18 and 20 show read circuits of an example of a neuron for which the analogue value is a current;
(16) FIG. 19 illustrates an alternative embodiment of the read circuits of FIGS. 17 and 18.
DETAILED DESCRIPTION
(17) In reference to FIG. 5, the invention relates to an artificial neuron NA for a neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight.
(18) The synapse has a terminal for activation of the synapse and a terminal for propagation of a synaptic signal. In the presence of a presynaptic activation applied onto the activation terminal, the propagation terminal propagates a synaptic signal representative of the value of the resistive memory (i.e. the synaptic weight) in the direction of the artificial neuron NA via a bit line BL.
(19) The artificial neuron comprises an integration circuit CI that comprises an accumulator of synaptic weights ACC at the terminals of which a membrane voltage V.sub.mem is established and a comparator COMP configured to emit a postsynaptic pulse SO if a threshold V.sub.seuil is exceeded by the membrane voltage V.sub.mem.
(20) The invention proposes decoupling the reading of the synaptic weight from its integration by avoiding digitising the reading of the synaptic weight. The various constraints can thus be divided up according to whether they are inherited from the technology of the resistive memory or from the operation of the analogue neuron. To do this, the invention proposes more particularly that the artificial neuron NA further include a read circuit CL configured to impose on the synapse a reading voltage independent of the membrane voltage V.sub.mem and to provide to the integration circuit CI an analogue value representative of the synaptic weight PSa.
(21) The read circuit CL thus allows to impose on the synapse a reading voltage having an identical polarisation for each reading regardless of the state of the membrane voltage V.sub.mem. This read circuit also allows to impose on the synapse a reading voltage sufficiently low to avoid any risk of parasitic writing. The result of the reading, in particular the analogue value representative of the synaptic weight PSa, is transmitted to the integration circuit. As will be seen below, this value can take various forms, such as a voltage, a current, a charge or a duration for example. The integration circuit CI, thus decoupled from the reading, can thus propose a vast range of voltage for the membrane voltage, independent of the specifications of the synapse.
(22) Implementations of resistive synapses which can be advantageously used in the context of the invention are described in detail below. It is understood, however, that the invention is not limited to these specific implementations.
(23) It can indeed be sought to have synapses which can be both excitatory and inhibitory, and which must thus be capable of both injecting and drawing current from the neuron. Since the synapses are resistive here and the current that they control depends on their resistance, two levels of voltage for supplying power to the synapse are provided, one positive and one negative. FIG. 6 provides an example of such an excitatory and inhibitory synapse, called 2R1C synapse. The synapse comprises an excitatory component CE and an inhibitory component CI arranged in series, with the propagation terminal Bp of the synapse as the midpoint, between a positive power supply voltage V.sub.read and a negative power supply voltage −V.sub.read. Each of these components can consist of n≥1 1T1R or 1S1R cells according to the encoding chosen (in the drawing, the reference Select. thus designates the access transistor or the selector of such 1T1R or 1S1R cells). If multivalued RRAMs are used, it is possible that n=1. If on the contrary binary RRAMs are used, as many cells as levels of weight desired are provided. Synapses equal to −1, 0 or +1 can also be used, in which case binary RRAMs can be used and n=1. In any case, below reference is made to the total resistance of the cells in parallel by writing R.sub.exci and R.sub.inhi to respectively designate the total resistance of the excitatory component CE and the total resistance of the inhibitory component CI. In FIG. 6, the capacitance C.sub.load is part of the read circuit of a neuron according to a possible embodiment of the invention and is therefore shared by all the synapses of the same column.
(24) The weight of the synapse is encoded as follows. If an excitatory synapse is desired, the resistance R.sub.inhi is set to its maximum level of resistance, while the resistance R.sub.exci (<R.sub.inhi) modulates the positive weight of the synapse. The lower the resistance R.sub.exci, the greater the synaptic weight, since this results in a greater synaptic current. On the contrary, if an inhibitory synapse is desired, the resistance R.sub.exci is set to its maximum level of resistance, while the resistance R.sub.inhi (<R.sub.exci) modulates the negative weight of the synapse.
(25) By neglecting the effects of the selectors or access transistors, the schema composed of the capacitance C.sub.load and of two resistances R.sub.inhi and R.sub.exci resembles a dampened resistive bridge. By applying the power supply voltages V.sub.read and −V.sub.read, the potential V.sub.load at the propagation terminal Bp thus progressively charges as shown in FIG. 7. This FIG. 7 illustrates that the integration of the synaptic weight can only be effective over a period of integration PI corresponding to a read-pulse duration lower than the time constant of the pair R.sub.syn-C.sub.load. Indeed, in the contrary case, with for example R.sub.exci<<R.sub.inhi, there is a risk of obtaining V.sub.load=V.sub.read regardless of the value of R.sub.exci.
(26) This time constant is furthermore even shorter when binary RRAMs are used to obtain multivalued synapses, the placement of these binary RRAMs in parallel indeed leading to a lower overall resistance. This problem can be circumvented by using a static reading of the synapse, that is to say the reading of a value that is a function of the weight of the synapse which is stabilised in the sense that it is independent of the duration of a read pulse. FIG. 7 indeed shows that in the static state achieved with a sufficiently long read pulse, the value of V.sub.load can effectively be modulated by the ratio between R.sub.exci and R.sub.inhi and thus by playing with the number of high-resistance (“High Resistive State”, HRS) or low-resistance (“Low Resistive State”, LRS) devices in the excitatory component and inhibitory component.
(27) Given the example of a synapse composed of 8 OxRAM devices, 4 for the excitatory component and 4 for the inhibitory component. With LRS=3 kΩ, HRS=800 kΩ and C.sub.load=50 fF, an encoding over 9 weights (including the zero weight) associated with time constants ranging from 1 ns to 250 ps can be obtained. As for a static reading, it offers more combinations (13 weights possible) and avoids having to generate brief reading pulses. However, this static reading consumes more energy because of the “prolonged” access to the RRAM.
(28) FIGS. 8 and 9 show a possible organisation of the synaptic array with 2R1C synapses corresponding to that of FIG. 6 in the case in which the components CE, CI are respectively based on 1T1R or 1S1R cells.
(29) In the 1T1R case (FIG. 8), the excitatory and inhibitory components participating in the same synapse share their activation terminals WL.sub.i, WL.sub.j. Indeed, during the reading phase, the two components are read at the same time. This sharing is welcome since the synaptic array is complicated by the necessity of having two networks of distinct source lines SL.sub.a, SL.sub.b which are used to distinguish the cells with shared BL and WL during the write phase and of polarising the synapses into V.sub.read or −V.sub.read according to whether they encode the excitatory or inhibitory component of their synapse during the read phase. In this configuration, the gates SL.sub.a, SL.sub.b are designed to remain polarised to ±V.sub.read and the write pulses between the ground and V.sub.DD are sent to the activation terminals WL.sub.i, WL.sub.j. It is noted that the access transistors of the inhibitory cells are polarised inversely.
(30) In the 1S1R case (FIG. 9), the excitatory component of a synapse is taken between a word line WL.sub.i_exci, WL.sub.j_exci and a bit line Bl.sub.u-Bl.sub.x while the inhibitory component of the same synapse is taken between a word line WL.sub.i_inhi, WL.sub.j_inhi and the bit line Bl.sub.u-Bl.sub.x. Read pulses are sent simultaneously on the word lines WL.sub.i_exci and WL.sub.i_inhi corresponding to a presynaptic spike relative to the line i. The word line WL.sub.i_exci undergoes a pulse from the ground at V.sub.read and the word line WL.sub.i_inhi undergoes a pulse from the ground at −V.sub.read.
(31) It can also be sought to implement negative spikes, in particular presynaptic pulses that invert the weight of the synapse that they trigger.
(32) Going back to the example of FIG. 9, instead of sending positive slots on WL.sub.i_exci, WL.sub.j_exci and negative slots on WL.sub.i_inhi, WL.sub.j_inhi, it suffices to invert these polarisations. Thus, an inhibitory synapse injects a current into C.sub.load and conversely an excitatory synapse removes it.
(33) Going back to the example of FIG. 8, in the case of a negative spike it is also possible to invert the polarisation of two source lines SL.sub.a, SL.sub.b. This solution is not necessarily favourable, since it is long and costly in terms of energy because of the fact that these lines are shared by the entire synaptic array. Alternatively, it is possible to use a driver per source line and the polarisation of which is toggled from V.sub.read to −V.sub.read according to the sign of the presynaptic pulse to be processed. Consequently, it is no longer necessary to charge and discharge two complete arrays but only the two source lines SL.sub.a and SL.sub.b which correspond to the synapses excited by the same presynaptic pulse. In this context, it is possible to move the voltage of these source lines only during the reading and leave them grounded otherwise. Alternatively, these source lines SL.sub.a and SL.sub.b can change the polarisation (from V.sub.read to −V.sub.read and vice versa) only when this is necessary by using for this purpose a memory in each source-line driver.
(34) FIGS. 10 and 11 illustrate another exemplary embodiment for integrating an analogue signed weight into a synaptic array according to which an analogue absolute value is associated with a binary sign via a synapse called hereinafter absolute value+sign synapse. The synaptic array is thus more conventional, provided with a single write voltage and having unidirectional read currents. According to this example, a certain number of binary RRAMs, a multivalued RRAM or a single binary RRAM in the case of a binary synapse implement(s) the absolute value R.sub.abs of the synaptic weight while another RRAM, modelled by a resistance R.sub.signe, is used binarily to encode the sign of the synaptic weight. This sign RRAM can advantageously consist of a triplet or a quintuplet of devices in which the sign of the synapse is extracted by a majority. The circuit for reading the artificial neuron thus comprises a circuit Cb for binary reading of the memory of sign of synaptic weight M.sub.signe and a circuit Ca for analogue reading of the memory of absolute value of synaptic weight M.sub.abs, said analogue read circuit Ca being controlled by the binary read circuit Cb. The binary read circuit Cb uses the sign of the presynaptic spike Sp and the sign of the synaptic weight M.sub.signe to provide to the analogue read circuit Ca an integration sign Si indicating in which direction to integrate the analogue current I.sub.abs coming from the memory of absolute value of synaptic weight M.sub.abs. Since the direction of the analogue current I.sub.abs is always the same, its inversion in the case of a negative integration sign can be carried out with a simple current mirror as shown in FIG. 11. In this FIG. 11, if the integration sign Si is equal to 1, the current I.sub.abs is injected into C.sub.load. On the contrary, if the integration sign Si is equal to 0, the current I.sub.abs is removed from C.sub.load.
(35) FIGS. 12, 13 and 14 show exemplary embodiments of an artificial neuron for which the analogue value representative of the synaptic weight provided by the read circuit to the integration circuit is a voltage. In certain embodiments, the analogue value representative of the synaptic weight can be a voltage independent of the duration of a read pulse, the neurons carrying out a static reading of the synapse.
(36) In FIGS. 12 and 13, the read circuit CL1 comprises an accumulator of synaptic current C.sub.load at the terminals of which a voltage V.sub.load is established, this voltage corresponding to the analogue value representative of the synaptic weight. Moreover, the artificial neuron comprises a circuit that is a bidirectional voltage tracker of ST1, ST2 interposed between the read circuit CL1 and the integration circuit CI1.
(37) The operation of the neuron is the following. During an operation of reading the synapse, the lower pole of C.sub.load is connected to the virtual ground Gnd by a switch rst_bot. In a first phase of the reading operation, C.sub.load is first discharged by connecting its upper pole to the virtual ground using a switch rst_top, the read circuit thus being configured to discharge the accumulator of synaptic current C.sub.load before imposing the read voltage on the synapse. The reading of the synapse is then triggered by the opening of the switch rst_top. The current coming from the bit line BL is then accumulated in C.sub.load, generating the read voltage V.sub.load. The opening of rst_bot allows to obtain a floating voltage V.sub.load. The voltage tracker ST1, ST2 is thus configured to copy the membrane voltage V.sub.mem at the lower terminal of C.sub.load. Thus the voltage at the upper terminal of C.sub.load is equal to the sum of V.sub.mem and V.sub.load. Then the voltage tracker ST1, ST2 is configured to copy this sum of voltage to the upper terminal of the membrane capacitance C.sub.mem thus providing the new membrane voltage that is compared to the threshold(s) for spike emission.
(38) The analogue addition of voltage proposed in the exemplary embodiments of FIGS. 11 and 12 allows to carry out a static reading of the 2R1C synapse. Dynamic reading is also possible under the condition that a sufficiently brief read pulse is generated. Moreover, in these examples, the maximum stimulation is limited by the read voltage of the RRAMs. It can thus be chosen that such a maximum stimulation alone allows to trigger a postsynaptic spike by a neuron, the membrane voltage of which would be at its rest potential. In this case, the range of voltage of the membrane voltage V.sub.mem is limited by the read voltage V.sub.read. Alternatively, such a stimulation feature is not provided, and the membrane voltage V.sub.mem can be spread out over a broader range of voltage.
(39) In FIG. 12, the voltage tracker ST1 comprises two operational amplifiers, one intended via the switch mem2bot to copy the membrane voltage to the lower terminals of C.sub.load and the other intended via the switch top2mem to copy the sum of voltage to the upper terminals of C.sub.mem.
(40) In FIG. 13, the voltage tracker ST2 comprises a single operational amplifier instead of the two operational amplifiers alternatingly used in FIG. 12. In order to counteract the influence of the parasitic capacitances of the switches during the transfers of charge at the input of the operational amplifier, an additional capacitance C.sub.load_bis in parallel to the switch rst_bot is provided.
(41) It is noted that the absolute value+sign synapse is adapted to the neurons of FIGS. 12 and 13.
(42) In FIG. 14, which also proposes an analogue value representative of the synaptic weight in the form of a voltage, the read circuit CL2 comprises a switch R.sub.ON/R.sub.OFF having a first terminal B1 intended to be connected to the synapse via the bit line BL and a second terminal B2 connected to the integration circuit CI2. The integration circuit CI2 comprises an integrator mounting connected to the second terminal and inside of which the accumulator of synaptic weight C.sub.mem is mounted.
(43) The reading of the synapse occurs as follows. First, the switch is left open (it has a resistance R.sub.OFF in its off state), the voltage on the bit line V.sub.BL is stabilised according to the weight of the synapse (therefore necessarily R.sub.OFF>>HRS). Then, the switch is closed (it has a resistance R.sub.ON in its on state), the voltage V.sub.BL is integrated by the integrator mounting, the time constant of which depends on R.sub.ON and C.sub.mem and not on the LRS of the RRAMs. Therefore, R.sub.ON>LRS. The neuron of FIG. 14 thus carries out a static reading of the synapse via the switch R.sub.ON/R.sub.OFF and an integration of the voltage V.sub.BL.
(44) FIGS. 15 and 16 show exemplary embodiments of an artificial neuron according to the invention for which the analogue value representative of the synaptic weight provided by the read circuit to the integration circuit is a duration. In these examples, the neuron comprises a logic circuit LOG interposed between the read circuit CL3 and the integration circuit CI3, the logic circuit being configured to generate from said analogue value a pulse Cmd_exci, Cmd_inhi presenting said duration. As for the integration circuit CI3, it comprises a source of current SI.sub.exc, SI.sub.inhi controlled by said pulse to inject a current into the accumulator of synaptic weights during said duration.
(45) Like for the neurons of FIGS. 12 and 13, the read circuit CL3 of the neuron shown in FIG. 15 comprises an accumulator of synaptic current C.sub.load at the terminals of which a voltage V.sub.load is established and a switch rst_load allowing to carry out the discharge of this accumulator before an operation of reading the synaptic weight. During a read operation, the accumulator C.sub.load is charged by the synaptic current, more or less rapidly according to the synaptic weight. The duration of this charging can be estimated very simply using an analogue comparator. In FIG. 15, synapses that are both excitatory and inhibitory are considered and two comparators Cp and Cn are thus provided, tasked with comparing the voltage at the terminals of the accumulator of synaptic current C.sub.load respectively to a first threshold Sp (for example positive) and to a second threshold Sn (for example negative). On the timing diagrams on the left in FIG. 15, the synapse is excitatory and the voltage V.sub.load at the terminals of the accumulator of synaptic current C.sub.load, after it has been discharged, progressively increases until it exceeds the first threshold Sp and switches the output Comp_exci of the comparator Cp which thus provides a piece of information on charging duration which is representative of the synaptic weight.
(46) The output Comp_exci of the comparator Cp is provided to the logic circuit LOG interposed between the read circuit CL3 and the integration circuit CI3. This logic circuit is configured to generate, from the result of the comparison, a voltage pulse having said duration, in this case the pulse Cmd_exci in the example of FIG. 15.
(47) As for the integration circuit CI2, it comprises a source of current SI.sub.exc controlled by said pulse Cmd_exci to inject a current into the accumulator of synaptic weight C.sub.mem during said duration. The duration of this injection of current thus depends on the value of the synaptic weight, so that the final value of the membrane voltage V.sub.mem also depends on the value of the synaptic weight.
(48) In the example shown with excitatory and inhibitory synapses, the integration circuit CI2 comprises another source of current SI.sub.inhi controlled by a voltage pulse Cmd_inhi to draw current from the accumulator of synaptic weights C.sub.mem during a duration representative of the synaptic weight.
(49) The neuron of FIG. 15 can further take into account the sign of the presynaptic pulse, said sign Signe_spike being provided to the logic circuit LOG which is thus configured to determine the integration sign from the sign of the spike and from a piece of information on sign of synaptic weight determined from that of the comparators Cp and Cn which switches. This logical and economical processing of the sign of the spike allows, in particular in the case of 1T1R cells, to lighten the synaptic array and its management. It is noted that the absolute value+sign synapse is particularly adapted to this neuron.
(50) An advantage of this embodiment is the reliability of the zero weights. In the case of a zero weight, all the RRAM devices of the synapse are at HRS. Thus, on the one hand, the time constant associated with a synapse having a zero weight is much greater than the others and, on the other hand, Rexci≈Rinhi. It is therefore unlikely that the voltage V.sub.load exceed one of the two thresholds Sp, Sn not only because it will not have the time for it but also because its final value is likely to be comprised between the two thresholds. Consequently the logic circuit LOG does not see switching at the output of the comparators Cp, Cn and does not trigger any injection of charge onto C.sub.mem. A true zero weight that in absolutely no way modifies the state of the neuron is thus implemented.
(51) FIG. 16 shows timing diagrams illustrating another operating mode of the neuron of FIG. 15 according to which a double reading is carried out in such a way as to be insensitive to the switching delays of the comparators Cp, Cn. Indeed, according to the RRAM and transistor technologies used and the consumption of the comparators, it is possible for the switching time T.sub.comp of the latter to be non-negligible in comparison to the charging time of the accumulator C.sub.load. In this case, the duration of the pulse transmitted to the integration circuit may vary little with the value of R.sub.syn, which can turn out to be disadvantageous. In this other operating mode, the pulse is generated from two comparator switches, its duration corresponding to a duration separating the exceeding of the threshold associated with one of the comparators then the exceeding of the threshold associated with the other of the comparators. The switching delays are thus applied at the beginning and the end of the pulse and do not therefore affect its duration.
(52) Thus, first, the synapse is read in a direction for a time sufficiently long for V.sub.load to be stopped on V.sub.read or −V.sub.read according to the sign of the synapse. Then, the polarisation of the reading is inverted, the voltage V.sub.load thus passes through the difference in potential from one polarisation of V.sub.read to the other and exceeds the two thresholds Sp, Sn in a time relative to the weight of the synapse. The logic circuit LOG is thus configured to generate a voltage pulse between these two switches of comparators.
(53) FIGS. 17 to 20 show exemplary embodiments of an artificial neuron for which the analogue value representative of the synaptic weight provided by the read circuit to the integration circuit is a current. In the example of FIGS. 17 and 18, the read circuit CL4, CL5 comprises a conveyor of current that includes an input port X intended to be connected to the synapse via the bit line, an input port Y intended to have a fixed voltage (for example the ground) imposed on it for the duration of the access to the synapse and an output port Z connected to the integration circuit.
(54) Such a current conveyor, based on an operational amplifier and two current mirrors, is such that the fixed voltage imposed on the input port Y is copied onto the input port X and the current injected into the input port X is reproduced on the output port Z (with an inversion of sign for the circuit of FIG. 17, without inversion of sign for the circuit of FIG. 18). Since a fixed voltage is imposed on the port Y, the bit-line voltage is controlled according to this fixed voltage (it is thus independent of the membrane voltage of the neuron) and the synaptic current is delivered to the output port Z. This synaptic current is provided to the integration circuit which then carries out an analogue integration.
(55) The time constant R.sub.syn-C.sub.mem can however turn out to be too brief for the operational amplifier and the current mirrors forming the current conveyor to function correctly. Thus, in an alternative embodiment, the current conveyor comprises, as shown in FIG. 19, a current mirror configured to carry out a lowering of the current between the input port X and the output port Z. In this figure, effectively
(56)
with K a factor greater than 1 which allows to use read pulses having a longer duration and thus more adapted to the operation of the active elements without saturating the capacitance of the membrane.
(57) In an alternative embodiment shown in FIG. 20, the neuron comprises a transmission gate T between the read circuit and the integration circuit. This gate allows to dissociate the time of access to the RRAMs and the integration time, which allows to wait for the voltage at the input port X to stabilise before integrating the read current and to play with a brief integration pulse without this requiring a particularly reactive operational amplifier.
(58) Moreover, in this FIG. 20 the read circuit CL6 advantageously comprises both the inverter current mirror of the read circuit CL4 and the non-inverter current mirror of the read circuit CL5 (these mirrors can carry out a lowering of the current according to FIG. 19) and a selector S controlled by a signal Signe_spike representative of the sign of the presynaptic spike to select the output of one or the other of these current mirrors.
(59) The invention is not limited to the artificial neuron described above, and extends to a neuromorphic chip comprising a plurality of synapses with resistive memory arranged in an array of transverse lines and columns. Each synapse has a propagation terminal, the propagation terminals of the synapses of the same column being connected to each other and connected to an artificial neuron according to the invention. The synapses can be excitatory or inhibitory synapses such as those presented above in relation to FIGS. 6 to 11.
