ULTRA-WIDEBAND METHOD AND APPARATUS

Abstract

An ultra-wideband (UWB) communication system comprising a transmitter and a receiver is disclosed. In one embodiment, a symbol mapper circuit in the transmitter is adapted, in a first mode, to develop symbols having the number of pulses as currently defined in the 4z Standard; and, in a second mode, to develop symbols having fewer pulses than as currently defined in the 4z Standard. In an optional third mode, each data bit is mapped to a single pulse.

Claims

1. An apparatus for higher data rate transmission, comprising: a transmitter operable to perform ultra-wideband (UWB) communication; a processor communicatively coupled to the transmitter; and a non-transitory computer readable medium including executable instructions which, when executed by the processor, causes the processor to: develop a first plurality of symbols at a first rate of 31.2 Mb/s, wherein each symbol in the first plurality of symbols comprises eight pulses and eight silent chips in a first mode of operation; and develop a second plurality of symbols at a second rate of 62.4 Mb/s, wherein each symbol in the second plurality of symbols comprises four pulses and four silent chips in a second mode of operation.

2. The apparatus of claim 1, wherein, in the first mode of operation, each symbol in the first plurality of symbols comprises a first set of the four pulses followed by a first set of the four silent chips followed by a second set of the four pulses followed by a second set of the four silent chips.

3. The apparatus of claim 2, wherein the processor is further configured to: map a first data bit (g.sub.0) to the first set of the four pulses; and map a second data bit (g.sub.1) to the second set of the four pulses.

4. The apparatus of claim 1, wherein, in the second mode of operation, each symbol in the second plurality of symbols comprises a first set of two pulses followed by a first set of two silent chips followed by a second set of the two pulses followed by a second set of the two silent chips.

5. The apparatus of claim 4, wherein the processor is further configured to: map a first data bit (g.sub.0) to the first set of the two pulses; and map a second data bit (g.sub.1) to the second set of the two pulses.

6. The apparatus of claim 1, wherein the processor is further configured to develop a third plurality of symbols at a third rate of 124.8 Mb/s, wherein each symbol in the third plurality of symbols comprises two pulses and two silent chips in a third mode of operation.

7. The apparatus of claim 6, wherein, in the third mode of operation, each symbol in the third plurality of symbols comprises a first pulse followed by a first silent chip followed by a second pulse followed by a second silent chip.

8. The apparatus of claim 7, wherein the processor is further configured to: map a first data bit (g.sub.0) to the first pulse; and map a second data bit (g.sub.1) to the second pulse.

9. The apparatus of claim 1, wherein the processor is configured to develop a fourth plurality of symbols at a fourth rate of 249.6 Mb/s, wherein each symbol in the fourth plurality of symbols comprises a first pulse and a second pulse and no silent chips in a fourth mode of operation.

10. The apparatus of claim 9, wherein the processor is further configured to: map a first data bit (g.sub.0) to the first pulse; and map a second data bit (g.sub.1) to the second pulse.

11. The apparatus of claim 1, wherein the processor comprises a K=7 convolutional encoder.

12. A method for performing an ultra-wideband (UWB) communication with a higher data rate transmission using a transmitter communicatively coupled to a processor, the method comprising: developing, with the processor, a first plurality of symbols at a first rate of 31.2 Mb/s, wherein each symbol in the first plurality of symbols comprises eight pulses and eight silent chips in a first mode of operation; and developing, with the processor, a second plurality of symbols at a second rate of 62.4 Mb/s, wherein each symbol in the second plurality of symbols comprises four pulses and four silent chips in a second mode of operation.

13. The method of claim 12, wherein, in the first mode of operation, each symbol in the first plurality of symbols comprises a first set of the four pulses followed by a first set of the four silent chips followed by a second set of the four pulses followed by a second set of the four silent chips.

14. The method of claim 13, further comprising: mapping a first data bit (g.sub.0) to the first set of the four pulses; and mapping a second data bit (g.sub.1) to the second set of the four pulses.

15. The method of claim 12, wherein, in the second mode of operation, each symbol in the second plurality of symbols comprises a first set of two pulses followed by a first set of two silent chips followed by a second set of the two pulses followed by a second set of the two silent chips.

16. The method of claim 15, further comprising: mapping a first data bit (g.sub.0) to the first set of the two pulses; and mapping a second data bit (g.sub.1) to the second set of the two pulses.

17. The method of claim 12, wherein the method further comprises developing a third plurality of symbols at a third rate of 124.8 Mb/s, wherein each symbol in the third plurality of symbols comprises two pulses and two silent chips in a third mode of operation.

18. The method of claim 17, wherein, in the third mode of operation, each symbol in the third plurality of symbols comprises a first pulse followed by a first silent chip followed by a second pulse followed by a second silent chip.

19. The method of claim 18, further comprising: mapping a first data bit (g.sub.0) to the first pulse; and mapping a second data bit (g.sub.1) to the second pulse.

20. The method of claim 17, wherein the method further comprises developing a fourth plurality of symbols at a fourth rate of 249.6 Mb/s, wherein each symbol in the fourth plurality of symbols comprises a first pulse and a second pulse and no silent chips in a fourth mode of operation.

21. The method of claim 20, further comprising: mapping a first data bit (g.sub.0) to the first pulse; and mapping a second data bit (g.sub.1) to the second pulse.

22. The method of claim 12, wherein the processor comprises a K=7 convolutional encoder.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0016] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0017] FIG. 1 illustrates, in block diagram form, an ultra-wideband (UWB) communication system adapted to practice my method;

[0018] FIG. 2 illustrates, in block diagram form, a K=3 systematic convolutional encoder set forth in the 4z Standard;

[0019] FIG. 3 illustrates, in block diagram form, a K=7 systematic convolutional encoder set forth in the 4z Standard;

[0020] FIG. 4 illustrates, in flow diagram form, one embodiment of my method;

[0021] FIG. 5 illustrates, in chart form, simulation results of range versus packet error rate (PER) in an additive-white-Gaussian-Noise (AWGN) channel for some embodiments of my method; and

[0022] FIG. 6 illustrates, in chart form, simulation results of range versus PER in an IEEE 802.15.4a CM1 multipath channel for some embodiments of my method.

[0023] In the drawings, similar elements will be similarly numbered whenever possible. However, this practice is simply for convenience of reference and to avoid unnecessary proliferation of numbers and is not intended to imply or suggest that my invention requires identity in either function or structure in the several embodiments.

DETAILED DESCRIPTION

[0024] Illustrated in FIG. 1 is an ultra-wideband (UWB) communication system 10 comprising a UWB transmitter 12 and a UWB receiver 14. In the UWB communication system 10, n data bits are received for transmission, wherein n is a selected power of 2 greater than 1 and less than or equal to m, wherein m is greater than 1. For each data bit, a respective symbol is developed by a conventional systematic convolutional encoder 16. In a first mode of operation, my improved symbol mapper 18 is configured to map each symbol to m pulses of a packet. See, e.g., the 4z Standard. In a second mode of operation, my symbol mapper 18 is configured to map each symbol to (mn) pulses of the packet. In one embodiment, I select n from a sequence [2, 4, 8], but those skilled in this art will recognize that other powers are possible. FIG. 4 is a flowchart outlining steps of a method according to one embodiment. Referring to block 30, a first step includes developing a convolutionally encoded symbol. Decision block 32 includes selection of a first mode of operation according to block 34 or a second mode of operation according to block 36. Block 34 corresponds to the first mode of operation, which includes mapping the symbol to m chips of the frame. Block 36 corresponds to the second mode of operation, which includes mapping the symbol to mn chips of the frame.

[0025] By way of example, let us first consider the following examples in which n is selected to be 2: [0026] Using the 4z Standard K=3 encoder (K3_Reference, FIG. 2) to develop symbols at a rate of 27.2 Mbps, my symbol mapper 18 is configured to: map G0 to 4 pulses; insert 4 silent chips; map G1 to 4 pulses; and insert 4 additional silent chips. [0027] Using the K3_Reference to develop symbols at a rate of 54.5 Mbps, my symbol mapper 18 is configured to: map G0 to only 2 pulses; map G1 to only 2 pulses; and insert 4 silent chips. [0028] Using the 4z Standard K=7 encoder (K7_Reference, FIG. 3) to develop symbols at a rate of 31.2 Mbps, my symbol mapper 18 is configured to: map G0 to 4 pulses; insert 4 silent chips; map G1 to 4 pulses; and insert 4 additional silent chips. [0029] Using the K7_Reference to develop symbols at a rate of 62.4 Mbps, my symbol mapper 18 is configured to: map G0 to only 2 pulses; map G1 to only 2 pulses; and insert 4 silent chips.

[0030] Now, let us consider the following examples in which n is selected to be 4: [0031] Using the K3_Reference to develop symbols at a rate of 27.2 Mbps, my symbol mapper 18 is configured to: map G0 to only 1 pulse; map G1 to only 1 pulse; and insert only 2 silent chips. The resulting symbol rate will be 109 Mbps. [0032] Using the K7_Reference to develop symbols at a rate of 31.2 Mbps, my symbol mapper 18 is configured to: map G0 to only 1 pulse; map G1 to only 1 pulse; and insert only 2 silent chips. The resulting symbol rate will be 125 Mbps.

[0033] Let us now consider the following examples in which n is selected to be 8: [0034] Using the K3_Reference to develop symbols at a rate of 27.2 Mbps, my symbol mapper 18 is configured to: map G0 to only 1 pulse; map G1 to only 1 pulse; and insert no silent chips. The resulting symbol rate will be 218 Mbps. [0035] Using the K7_Reference to develop symbols at a rate of 31.2 Mbps, my symbol mapper 18 is configured to: map G0 to only 1 pulse; map G1 to only 1 pulse; and insert no silent chips. The resulting symbol rate will be 250 Mbps.

[0036] Finally, let us consider the following example in which n is selected to be 8, and I configure my UWB transmitter 12 so as, selectively, to bypass the systematic convolutional encoder 16: [0037] By bypassing both the K3_Reference and the K7_Reference, my symbol mapper 18 can easily be configured to map an input data bit (D0) to only 1 pulse with no silent chips. The resulting symbol rate will be 436 Mbps.

[0038] I have developed and tested MATLAB simulation models to determine an estimated performance of each of these embodiments, 1.1-1.3 and 2.1-2.3. As can be seen in FIG. 5, performance appears to me to be reasonable for all of these embodiments when operating in a channel that is subject to additive-white-Gaussian-Noise (AWGN). In part, my invention avoids complexity in both the UWB transmitter 12 and the UWB receiver 14 that the proposed puncturing schemes will introduce. Further, I can anticipate that my invention will result in at least 2.4 dB better performance. For example, whereas power-per-bit is approximately the same in both schemes, puncturing reduces power-per-bit by approximately 42%, whereas my invention reduces power-per-bit by 50%. Further, as I have noted above, puncturing loses almost all of the resulting coding gain.

[0039] As can be seen in FIG. 6, multipath performance also appears to me to be reasonable for all of these embodiments. By way of contrast, I note that performance hits an error floor for many of the known and proposed schemes: 0.1% for the punctured scheme and 1% for the known 108 Mbps scheme. It can be I anticipate that this trend will continue and will worsen for the proposed 216 Mbps and 435 Mbps schemes; however, short channels with little or no multipath should still be able to use these very high bit rates. Further, using my invention appears to me to offer significantly better performance. For example, from the simulation results shown in FIG. 5, my 54.4 Mbps embodiment appears to be 5.2 dB better (twice the distance) than the proposed 54.6 Mbps punctured scheme at 1% packet error rate (PER) in a multipath channel.

[0040] I submit that, while increasing the symbol rate reduces the processing gain, my approach is a better way to increase the bit rate, at least in part due to the coding gain not decreasing. As can be seen from the simulation results summarized in my Parent Provisional, my higher symbol rate approach performs better than the puncturing scheme for approximately the same bit rate. For example, from the simulation results shown in FIG. 5 and FIG. 6, I expect that my invention, configured to operate in a 108 Mbps mode, will achieve a very useful range of 14 m in a multipath channel for a 2% PER, and an excellent 36 meters in an AWGN channel at 1% PER.

[0041] One mode in the 4z Standard has a convolutional encoder which convolutionally encodes an input data bit to give 2 coded data bits and maps the 2 coded bits to 8 pulses in a symbol to achieve 27.2 Mbps. In accordance with my invention, I can double the rate to 54.4 Mbps by simply encoding 2 input bits to 2 pairs of coded bits and mapping each pair onto (8 divided by 2)=4 pulses. This can be generalized by making the 2 be any power of 2 greater than 1 (which we can call n). The 8 pulses can be any number of pulses (call it m pulses) if m is a multiple of n.

[0042] Although I have described my invention in the context of particular embodiments, one of ordinary skill in this art will readily realize that many modifications may be made in such embodiments to adapt either to specific implementations. Further, the several elements described above may be adapted so as to be operable under either hardware or software control or some combination thereof, as is known in this art. Alternatively, the several methods of my invention as disclosed herein in the context of a special purpose receiver apparatus may be embodied in computer readable code on a suitable non-transitory computer readable medium such that, when a general or special purpose computer processor executes the computer readable code, the processor executes the respective method.

[0043] Thus, it is apparent that I have provided an improved UWB method and apparatus having a higher data transmission rate. Although I have so far disclosed my invention only in the context of a packet-based UWB communication system, I appreciate that my invention is broadly applicable to other types of wireless communication systems, whether packed-based or otherwise, that perform channel sounding. Further, I submit that my invention provides performance generally comparable to the best prior art techniques, but more efficiently than known implementations of such prior art techniques.