HIGH-SPEED I/O CIRCUIT FOR DIE-TO-DIE INTERCONNECT FOR SUPPRESSING OVERSHOOT AND UNDERSHOOT

Abstract

Disclosed herein is a high-speed I/O circuit for die-to-die interconnect for suppressing an overshoot and an undershoot. A data reception circuit includes a reception circuit configured to convert a reception signal received from an interconnect into a digital signal, a first clipper circuit configured to suppress an overshoot of the reception signal based on current extraction, and a second clipper circuit configured to suppress an undershoot of the reception signal based on current supply.

Claims

1. A data reception circuit, comprising: a reception circuit configured to convert a reception signal received from an interconnect into a digital signal; a first clipper circuit configured to suppress an overshoot of the reception signal based on current extraction; and a second clipper circuit configured to suppress an undershoot of the reception signal based on current supply.

2. The data reception circuit of claim 1, wherein the first clipper circuit comprises: a first sensing port configured to sense a voltage at an input terminal of the reception circuit; and a first current port configured to transfer a current extracted from the input terminal to a ground, wherein when the voltage at the input terminal is higher than a preset upper limit voltage, the first clipper circuit operates to extract the current from the reception signal via the first current port.

3. The data reception circuit of claim 2, wherein the first clipper circuit corresponds to any one of a type operating based on a threshold voltage, a type operating based on a level shifter, or a type operating based on an amplifier or a comparator with a reference voltage set therein.

4. The data reception circuit of claim 2, wherein the upper limit voltage corresponds to a voltage set for determining the overshoot in a preset limit range.

5. The data reception circuit of claim 1, wherein the second clipper circuit comprises: a second sensing port configured to sense a voltage at an input terminal of the reception circuit; and a second current port configured to transfer a current supplied from a power supply to the input terminal, wherein when the voltage at the input terminal is lower than a preset lower limit voltage, the second clipper circuit operates to supply the current to the reception signal via the second current port.

6. The data reception circuit of claim 5, wherein the second clipper circuit corresponds to any one of a type operating based on a threshold voltage, a type operating based on a level shifter, or a type operating based on an amplifier or a comparator with a reference voltage set therein.

7. The data reception circuit of claim 5, wherein the lower limit voltage corresponds to a voltage set for determining the undershoot in a preset limit range.

8. A data transmission/reception circuit, comprising: a transmission circuit configured to transmit a transmission signal to an interconnect; a reception circuit configured to convert a reception signal received from the interconnect into a digital signal; a first clipper circuit configured to suppress an overshoot of the reception signal based on current extraction; and a second clipper circuit configured to suppress an undershoot of the reception signal based on current supply.

9. The data transmission/reception circuit of claim 8, further comprising: a switch configured to connect the first clipper circuit and the second clipper circuit to an input terminal of the reception circuit during an operation of the reception circuit.

10. The data transmission/reception circuit of claim 9, wherein the switch is closed during the operation of the reception circuit and opened during an operation of the transmission circuit.

11. The data transmission/reception circuit of claim 8, wherein the transmission circuit adjusts an output impedance based on a resistance value when an overshoot and undershoot are not suppressible in a reception stage for receiving the transmission signal.

12. The data transmission/reception circuit of claim 8, wherein the first clipper circuit comprises: a first sensing port configured to sense a voltage at an input terminal of the reception circuit; and a first current port configured to transfer the current extracted from the input terminal to a ground, wherein when the voltage at the input terminal is higher than a preset upper limit voltage, the first clipper circuit operates to extract the current from the reception signal via the first current port.

13. The data transmission/reception circuit of claim 12, wherein the first clipper circuit corresponds to any one of a type operating based on a threshold voltage, a type operating based on a level shifter, or a type operating based on an amplifier or a comparator with a reference voltage set therein.

14. The data transmission/reception circuit of claim 12, wherein the upper limit voltage corresponds to a voltage set for determining the overshoot in a preset limit range.

15. The data transmission/reception circuit of claim 8, wherein the second clipper circuit comprises: a second sensing port configured to sense a voltage at an input terminal of the reception circuit; and a second current port configured to transfer a current supplied from a power supply to the input terminal, wherein when the voltage at the input terminal is lower than a preset lower limit voltage, the second clipper circuit operates to supply the current to the reception signal via the second current port.

16. The data transmission/reception circuit of claim 15, wherein the second clipper circuit corresponds to any one of a type operating based on a threshold voltage, a type operating based on a level shifter, or a type operating based on an amplifier or a comparator with a reference voltage set therein.

17. The data transmission/reception circuit of claim 15, wherein the lower limit voltage corresponds to a voltage set for determining the undershoot in a preset limit range.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0029] FIG. 1 is a diagram illustrating an example die-to-die interconnect RLC model;

[0030] FIG. 2 is a diagram illustrating an example in which an overshoot and an undershoot occur due to under-damping characteristics during high-speed data transmission and reception;

[0031] FIG. 3 is a diagram illustrating a data reception circuit according to an embodiment of the present disclosure;

[0032] FIGS. 4 to 6 are diagrams illustrating example first clipper circuits (logic high clippers) for suppressing an overshoot shown in FIG. 3;

[0033] FIGS. 7 to 9 are diagrams illustrating example second clipper circuits (logic low clippers) for suppressing an undershoot shown in FIG. 3;

[0034] FIG. 10 is a diagram illustrating an example in which the first clipper circuit shown in FIG. 4 and the second clipper circuit shown in FIG. 7 are applied to a reception circuit for showing an eye-diagram of FIG. 2;

[0035] FIG. 11 is a diagram illustrating an example in which the first clipper circuit shown in FIG. 6 and the second clipper circuit shown in FIG. 9 are applied to a reception circuit for showing an eye-diagram of FIG. 2;

[0036] FIG. 12 is a diagram illustrating an example in which the overshoot and the undershoot are reduced and the eye-diagram is expanded according to an application of the present disclosure;

[0037] FIG. 13 is a diagram illustrating a data transmission/reception circuit according to an embodiment of the present disclosure;

[0038] FIG. 14 is a diagram illustrating a data transmission/reception circuit including switches according to an embodiment of the present disclosure;

[0039] FIG. 15 is a diagram illustrating a data transmission/reception circuit including a transmission circuit capable of adjusting an output impedance according to an embodiment of the present disclosure; and

[0040] FIG. 16 is a diagram illustrating a data transmission/reception circuit including switches and a transmission circuit capable of adjusting an output impedance according to an embodiment of the present disclosure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] The present disclosure will be described in detail below with reference to the accompanying drawings. Repeated descriptions and descriptions of known functions and configurations which have been deemed to make the gist of the present disclosure unnecessarily obscure will be omitted below. The embodiments of the present disclosure are intended to fully describe the present disclosure to a person having ordinary knowledge in the art to which the present disclosure pertains. Accordingly, the shapes, sizes, etc. of components in the drawings may be exaggerated to make the description clearer.

[0042] In the present specification, each of phrases such as A or B, at least one of A and B, at least one of A or B, A, B, or C, at least one of A, B, and C, and at least one of A, B, or C may include any one of the items enumerated together in the corresponding phrase, among the phrases, or all possible combinations thereof.

[0043] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0044] FIG. 3 is a diagram illustrating a data reception circuit according to an embodiment of the present disclosure.

[0045] Specifically, FIG. 3 is a diagram illustrating an example data reception circuit unit in the configuration for one-directional transmission using an interconnect.

[0046] Referring to FIG. 3, the data reception circuit according to an embodiment of the present disclosure includes a reception circuit RX for converting a reception signal received from the interconnect into a digital signal, a first clipper circuit (logic high clipper) for suppressing an overshoot of the reception signal based on current extraction, and a second clipper circuit (logic low clipper) for suppressing an undershoot of the reception signal based on current supply.

[0047] Here, the first clipper circuit may include a first sensing port for sensing a voltage at an input terminal of the reception circuit and a first current port for transferring the current extracted from the input terminal to a ground.

[0048] Here, when the voltage at the input terminal is higher than a preset upper limit voltage, the first clipper circuit may operate to extract the current from the reception signal.

[0049] For example, referring to FIG. 3, if the overshoot occurs when a signal is received at a data reception circuit 300 via a transmission line (the interconnect), a logic high clipper circuit, which is the first clipper circuit, may sense the overshoot via an S port (a sense-port) that is a first sensing port. Then, a path may be provided through which the current flows from the input terminal net_RX_in to the ground (GND) of the first clipper circuit of the data reception circuit 300 via a C port (a current-port) that is the first current port.

[0050] Here, the first clipper circuit may correspond to any one of a type operating based on a threshold voltage, a type operating based on a level shifter, or a type operating based on an amplifier or a comparator with a reference voltage set therein.

[0051] Here, the upper limit voltage may correspond to a voltage set for determining the overshoot in a preset limit range.

[0052] For example, FIG. 4 is a diagram illustrating a first clipper circuit 400 using an N-type Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET), the threshold voltage of which corresponds to the preset upper limit voltage. Here, the voltage at the input terminal net_RX_in becomes higher than the threshold voltage (i.e., the preset upper limit value) of the NMOSFET, the NMOSFET may be turned on and the current may be extracted to flow from the input terminal net_RX_in to the GND via the C port (current-port) to suppress the overshoot. That is, the S port in the first clipper circuit 400 shown in FIG. 4 may be a gate of the NMOSFET and the C port may be a drain of the NMOSFET.

[0053] For another example, FIG. 5 is a diagram illustrating a first clipper circuit 500 using a level shifter. Here, the voltage at the input terminal net_RX_in of the data reception circuit becomes higher than the preset upper limit voltage, the voltage at the input terminal net_RX_in of the data reception circuit may turn on the NMOSFET via the level shifter to allow the current to be extracted to flow from the input terminal net_RX_in to the GND via the C port (current-port) to suppress the overshoot. That is, the S port in the first clipper circuit 500 shown in FIG. 5 may be an input of the level shifter and the C port may be the drain of the NMOSFET.

[0054] For another example, FIG. 6 is a diagram illustrating a first clipper circuit 600 using an amplifier or a comparator with a reference voltage VHIGHREF set therein. Here, when the voltage at the input terminal net_RX_in of the data reception circuit becomes higher than the reference voltage VHIGHREF, the NMOSFET may be turned on and the current may be extracted to flow from the input terminal net_RX_in to the GND via the C port (current-port) to suppress the overshoot. That is, the S port in the first clipper circuit 600 shown in FIG. 6 may be a positive input of the amplifier or the comparator and the C port may be the drain of the NMOSFET.

[0055] Here, the second clipper circuit may include a second sensing port for sensing the voltage at the input terminal of the reception circuit and a second current port for transferring the current supplied from a power supply to the input terminal.

[0056] Here, when the voltage at the input terminal is lower than a preset lower limit voltage, the second clipper circuit may operate to supply the current to the reception signal via the second current port.

[0057] For example, referring to FIG. 3, if the undershoot occurs when a signal is received at the data reception circuit 300 via the transmission line (the interconnect), a logic low clipper circuit, which is the second clipper circuit, may sense the undershoot via the S port (sense-port) that is the second sensing port. Then, a path may be provided through which the current may be supplied from the power supply to the input terminal net_RX_in of the data reception circuit 300 via the C port (current-port).

[0058] Here, the second clipper circuit may correspond to any one of a type operating based on a threshold voltage, a type operating based on the level shifter, or a type operating based on the amplifier or the comparator with the reference voltage set therein.

[0059] Here, the lower limit voltage may correspond to a voltage set for determining the undershoot in a preset limit range.

[0060] For example, FIG. 7 is a diagram illustrating the second clipper circuit using a P-type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOSFET), the threshold voltage of which corresponds to the preset lower limit voltage. Here, when the voltage at the input terminal net_RX_in of the data reception circuit becomes lower than the threshold voltage (i.e., the preset lower limit value) of the PMOSFET, the PMOSFET may be turned on and the current may be supplied from the power supply to the input terminal net_RX_in of the data reception circuit to suppress the undershoot. That is, the S port in the second clipper circuit shown in FIG. 7 may be a gate of the PMOSFET and the C port may be a drain of the PMOSFET.

[0061] For another example, FIG. 8 is a diagram illustrating a second clipper circuit 800 using a level shifter. Here, the voltage at the input terminal net_RX_in of the data reception circuit becomes lower than the preset lower limit voltage, the voltage at the input terminal net_RX_in of the data reception circuit may turn on the PMOSFET to allow the current to be supplied from the power supply to the input terminal net_RX_in via the C port (current-port) to suppress the undershoot. That is, the S port in the second clipper circuit 800 shown in FIG. 8 may be an input of the level shifter and the C port may be the drain of the PMOSFET.

[0062] For another example, FIG. 9 is a diagram illustrating a second clipper circuit 900 using an amplifier or a comparator with a reference voltage VLOWREF set therein.

[0063] Here, when the voltage at the input terminal net_RX_in of the data reception circuit becomes lower than the reference voltage VLOWREF, the PMOSFET may be turned on and the current may be supplied via the C port (current-port) from the power supply to the input terminal net_RX_in of the data reception circuit to suppress the undershoot. Namely, the S port in the second clipper circuit 900 shown in FIG. 9 may be a negative input of the amplifier or the comparator and the C port may be the drain of the PMOSFET.

[0064] Here, FIG. 10 is a diagram illustrating a test result of applying the first clipper circuit 400 shown in FIG. 4 and the second clipper circuit 700 shown in FIG. 7 to the reception circuit showing the eye-diagram of FIG. 2. Referring to FIG. 10, it may be confirmed that an overshoot and an undershoot respectively deviated from a high logic level and a low logic level that are the limit ranges in FIG. 2 are suppressed to be within the limit ranges. Furthermore, it may be confirmed that the eye-diagram of FIG. 10 is expanded in comparison to that of FIG. 2.

[0065] Furthermore, FIG. 11 is a diagram illustrating a test result of applying the first clipper circuit 600 shown in FIG. 6 and the second clipper circuit 900 shown in FIG. 9 to the reception circuit showing the eye-diagram of FIG. 2. Referring to FIG. 11, it may be confirmed that the overshoot and undershoot respectively deviated from a high logic level and a low logic level that are the limited ranges in FIG. 2 are suppressed to be within the limit ranges. Furthermore, it may be confirmed that the eye-diagram of FIG. 11 is expanded in comparison to that of FIG. 2.

[0066] In this way, during the high-speed data transmission and reception via high density die-to-die interconnects via the data reception circuit, the present disclosure serves a function of suppressing the overshoot and the undershoot in the I/O circuit in an IC to improve the stability of transmission signals and the reliability of the IC.

[0067] FIG. 13 is a diagram illustrating a data transmission/reception circuit according to an embodiment of the present disclosure.

[0068] Specifically, FIG. 13 is a diagram illustrating a data reception circuit unit in the configuration of a bidirectional I/O circuit in which a transmission circuit TX and a reception circuit RX are connected together to one interconnect.

[0069] Referring to FIG. 13, the data reception circuit 1300 according to an embodiment of the present disclosure includes the reception circuit RX for converting a reception signal received from the interconnect into a digital signal, a first clipper circuit (logic high clipper) 1320 for suppressing an overshoot of the reception signal based on current extraction, and a second clipper circuit (logic low clipper) 1310 for suppressing an undershoot of the reception signal based on current supply.

[0070] Here, the data reception circuit 1300 shown in FIG. 13 operates in the same way as the data reception circuit shown in FIG. 3 and thus detailed description thereof will be omitted.

[0071] FIG. 14 is a diagram illustrating a data transmission/reception circuit including switches according to an embodiment of the present disclosure.

[0072] Specifically, FIG. 14 is a diagram illustrating the data reception circuit unit in the configuration of the bidirectional I/O circuit in which the transmission circuit TX and the reception circuit RX are connected together to one interconnect.

[0073] Referring to FIG. 14, the data reception circuit 1400 according to an embodiment of the present disclosure includes the reception circuit RX for converting a reception signal received from the interconnect into a digital signal, a first clipper circuit (logic high clipper) 1420 for suppressing an overshoot of the reception signal based on current extraction, and a second clipper circuit (logic low clipper) 1410 for suppressing an undershoot of the reception signal based on current supply.

[0074] Here, during the operation of the reception circuit, the data reception circuit 1400 may further include switches 1412 and 1411 for connecting the first clipper circuit 1420 and the second clipper circuit 1410 to an input terminal of the reception circuit.

[0075] For example, when the switch 1412 is closed, the first clipper circuit 1420 may be connected to the input terminal of the reception circuit, and when the switch 1411 is closed, the second clipper circuit 1410 may be connected to the input terminal of the reception circuit.

[0076] Here, the switch may be closed during the operation of the reception circuit and opened during the operation of the transmission circuit. In this way, in an environment of the bidirectional I/O circuit in which the transmission circuit TX and the reception circuit RX are connected together, when the transmission circuit operates, a parasite element may be disconnected by opening the switches and disconnecting the first clipper circuit 1420 and the second clipper circuit 1410.

[0077] Here, when the switches are closed, the data reception circuit 1400 shown in FIG. 14 operates in the same way as the data reception circuit shown in FIG. 3 and thus detailed description thereof will be omitted.

[0078] FIG. 15 is a diagram illustrating a data transmission/reception circuit including a transmission circuit capable of adjusting an output impedance according to an embodiment of the present disclosure.

[0079] Specifically, FIG. 15 is a diagram illustrating a case in which the present disclosure may be applied to only one point in the configuration of the bidirectional I/O circuit in which the transmission circuit TX and the reception circuit RX are connected together to one interconnect.

[0080] Referring to FIG. 15, the data transmission/reception circuit 1500 according to an embodiment of the present disclosure includes a transmission circuit TX 1530 for transmitting a transmission signal to the interconnect, a reception circuit RX for converting a reception signal from the interconnect into a digital signal, a first clipper circuit (logic high clipper) 1520 for suppressing an overshoot of the reception signal based on current extraction, and a second clipper circuit (logic low clipper) 1510 for suppressing an undershoot of the reception signal based on current supply.

[0081] Here, when an overshoot and an undershoot are not suppressible in a reception stage for receiving the transmission signal, the transmission circuit 1530 may adjust an output impedance based on a resistance value.

[0082] For example, the variable output impedance transmission circuit 1530 shown in FIG. 15 may serve a function of reducing under-damping characteristics to limit the overshoot and the undershoot by increasing the resistance value.

[0083] Here, the data reception circuit shown in FIG. 15 operates in the same way as the data reception circuit shown in FIG. 3 and thus detailed description thereof will be omitted.

[0084] FIG. 16 is a diagram illustrating a data transmission/reception circuit including switches and a transmission circuit capable of adjusting an output impedance according to an embodiment of the present disclosure.

[0085] Specifically, FIG. 16 is a diagram illustrating a case in which the present disclosure may be applied to only one point in the configuration of the bidirectional I/O circuit in which the transmission circuit TX and the reception circuit RX are connected together to one interconnect.

[0086] Referring to FIG. 16, a data transmission/reception circuit 1600 according to an embodiment of the present disclosure includes a transmission circuit TX 1630 for transmitting a transmission signal to the interconnect, a reception circuit RX for converting a reception signal received from the interconnect into a digital signal, a first clipper circuit (logic high clipper) 1620 for suppressing an overshoot of the reception signal based on current extraction, and a second clipper circuit (logic low clipper) 1610 for suppressing an undershoot of the reception signal based on current supply.

[0087] Here, during the operation of the reception circuit, the data reception circuit RX may further include switches 1612 and 1611 for connecting the first clipper circuit 1620 and the second clipper circuit 1610 to an input terminal of the reception circuit.

[0088] For example, when the switch 1612 is closed, the first clipper circuit 1620 may be connected to the input terminal of the reception circuit, and when the switch 1611 is closed, the second clipper circuit 1610 may be connected to the input terminal of the reception circuit.

[0089] Here, the switch may be closed during the operation of the reception circuit and opened during the operation of the transmission circuit. In this way, in an environment of the bidirectional I/O circuit in which the transmission circuit TX and the reception circuit RX are connected together, when the transmission circuit operates, a parasite element may be disconnected by opening the switches and disconnecting the first clipper circuit 1620 and the second clipper circuit 1610.

[0090] Here, when the overshoot and the undershoot are not suppressible in a reception stage for receiving the transmission signal, the transmission circuit 1630 may adjust an output impedance based on a resistance value.

[0091] For example, the variable output impedance transmission circuit 1630 shown in FIG. 16 may serve a function of reducing under-damping characteristics to limit the overshoot and the undershoot by increasing the resistance value.

[0092] Here, when the switches are closed, the data reception circuit RX shown in FIG. 16 operates in the same way as the data reception circuit shown in FIG. 3 and thus detailed description thereof will be omitted.

[0093] According to the present disclosure, an overshoot and an undershoot caused by under-damping characteristics may be suppressed during high-speed data transmission and reception via the die-to-die interconnect.

[0094] In addition, the stability of transmission signals and the reliability of an integrated circuit may be improved by suppressing an overshoot and an undershoot in an I/O circuit of the integrated circuit.

[0095] As described above, in the high-speed I/O circuit for the die-to-die interconnect for suppressing the overshoot and the undershoot according to the present disclosure, the configurations and schemes in the above-described embodiments are not limitedly applied, and some or all of the above embodiments can be selectively combined and configured so that various modifications are possible.