Abstract
An electrically erasable programmable read only memory (EEPROM) includes a substrate, isolation structures, a row of erase gate and a row of floating gates. The isolation structures are defined in the substrate to extend in a first direction. The row of erase gate having a wave shape is disposed across the substrate. The row of floating gates having staggered islands is disposed parallel to the row of erase gate. A method of forming said electrically erasable programmable read only memory (EEPROM) is also provided.
Claims
1. A semiconductor structure with wave shaped erase gate, comprising: a substrate; isolation structures defined in the substrate to extend in a first direction; an erase gate having a wave shape disposed across the substrate when viewed from a top view, wherein the wave shape has first parts connecting to second-one parts and second-two parts, wherein the first parts, the second-one parts and the second-two parts are directly connected with each other, wherein the first parts, the second-one parts, the first parts and the second-two parts are alternatingly and repeatingly arranged, wherein the first parts extend along a second direction, the second-one parts extend along a third direction and the second-two parts extend along a fourth direction, and wherein the third direction and the fourth direction are not orthogonal to the second direction, and wherein the first parts overlap the substrate, the second-one parts and the second-two parts overlap the isolation structures, but the first parts do not overlap the isolation structures; and floating gates having staggered islands disposed parallel to the erase gate when viewed from the top view.
2. The semiconductor structure with wave shaped erase gate according to claim 1, further comprising: a word line having the wave shape disposed parallel to the erase gate and at a side of the floating gates opposite to the erase gate.
3. The semiconductor structure with wave shaped erase gate according to claim 1, wherein the second-one parts and the second-two parts extend along different directions.
4. The semiconductor structure with wave shaped erase gate according to claim 1, wherein the second direction is orthogonal to the first direction.
5. The semiconductor structure with wave shaped erase gate according to claim 1, wherein the third direction and the fourth direction have common absolute values of slope.
6. The semiconductor structure with wave shaped erase gate according to claim 1, wherein two of the first parts adjacent to each other are dislocated.
7. The semiconductor structure with wave shaped erase gate according to claim 1, wherein a length of a gap between two adjacent floating gates is defined as g, and a length of a shifting between two adjacent floating gates is defined as s, and wherein a ratio of the g and the s is between 63:45 to 45:63.
8. The semiconductor structure with wave shaped erase gate according to claim 1, further comprising: a source line located right below the erase gate.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1 schematically depicts a top view of an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.
(2) FIG. 2 schematically depicts a top view of rows of floating gates according to an embodiment of the present invention.
(3) FIG. 3 schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.
(4) FIG. 4 schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.
(5) FIG. 5 schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.
(6) FIG. 6 schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.
(7) FIG. 7 schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.
(8) FIG. 8 schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.
(9) FIG. 9 schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.
(10) FIG. 10 schematically depicts a cross-sectional view of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention.
DETAILED DESCRIPTION
(11) FIG. 1 schematically depicts a top view of an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention. As shown in FIG. 1, a substrate 110 (120) is provided. Isolation structures 12 are defined in the substrate 110, wherein the isolation structures 12 extend in a first direction D1. Rows of erase gates 20 are disposed across the substrate 120. In this present invention, the rows of erase gates 20 have wave shapes.
(12) Rows of floating gates 30 are disposed parallel to the row of erase gate 20, but the row of floating gates 30 are only disposed on and vertically overlap the substrate 120, and therefore the row of floating gates 30 are staggered islands. FIG. 2 schematically depicts a top view of rows of floating gates according to an embodiment of the present invention. The rows of floating gates 30 are staggered islands, and vertically overlap the substrate 120 completely. The adjacent floating gates of the rows of floating gates 30 are dislocated. Therefore, the spacings P of the adjacent floating gates of the rows of floating gates 30 increase, and thus the cross talk capacitance is reduced, and there is no impact on the macro size of the array of erasably programmble read only memory cells 100. In a preferred embodiment, a ratio of a gap g between the adjacent floating gates and a shifting s between the adjacent floating gates is 63:4545:63, thereby the cross talk capacitance can being reduced more than 20% while the macro size of the array of erasably programmble read only memory cells 100 only increases less than 0.4%.
(13) Please refer to FIG. 1, rows of word lines 40 are also disposed parallel to the rows of erase gates 20 and at sides of the row of floating gates 30 opposite to the rows of erase gates 20, wherein the rows of word lines 40 have the wave shapes common to the wave shapes of the rows of erase gates 20 in a preferred embodiment to improve the layout of the array of erasably programmable read only memory cells 100. In this embodiment, there is no control gate disposed in the array of electrically erasable programmable read only memory (EEPROM).
(14) The rows of erase gates 20 have the wave shapes constituted by first parts 22 and second parts 24. The first parts 22 connect to the second parts 24, and the first parts 22 and the second parts 24 are alternatively arranged. The first parts 22 overlap the substrate 120 completely, and the second parts 24 are disposed between the substrate 120. Furthermore, the second parts 24 may include second-one parts 24a and second-two parts 24b, wherein the second-one parts 24a and the second-two parts 24b connect to the first parts 22 alternatively. In this embodiment, the second-one parts 24a and the second-two parts 24b extend along different directions to constitute the wave shapes of the rows of erase gates 20. Hence, the adjacent first parts 22 are also dislocated and are distributed right next to the adjacent floating gates of the rows of floating gates 30.
(15) More precisely, the first parts 22 extend along a second direction D2, the second-one parts 24a extend along a third direction D3 and the second-two parts 24b extend along a fourth direction D4. In a preferred embodiment, the second direction D2 is orthogonal to the first direction D1, and the third direction D3 and the fourth direction D4 have common absolute values of slope for improving the layout and the macro size of the array of erasably programmable read only memory cells 100.
(16) A method of forming said array of electrically erasable programmable read only memory (EEPROM) 100 is presented as follows. FIG. 3-10 schematically depict cross-sectional views of a method of forming an array of electrically erasable programmable read only memory (EEPROM) according to an embodiment of the present invention for illustrating the present invention, wherein same symbols of FIGS. 3-10 represent same components corresponding to FIGS. 1-2.
(17) FIGS. 3-5 are the cross-sectional views along line AA of FIG. 1, and FIGS. 6-10 are the cross-sectional views along line BB of FIG. 1.
(18) Please refer to FIG. 3, which is the cross-sectional view along the line AA of FIG. 1, the substrate 110 is provided. The substrate is a silicon substrate in this embodiment. Please refer to FIGS. 4-6, the row of floating gates 30 having staggered islands are formed on the substrate 110. The row of floating gates 30 include an ONO layer (silicon oxide/silicon nitride/silicon oxide layer) 32, a polysilicon layer 34 and a cap layer 36 stacked from bottom to top, but it is not limited thereto. As shown in FIG. 4, which is the cross-sectional view along the line AA of FIG. 1, a floating gate film stack 30a is deposited on the substrate 110 blanketly, wherein the floating gate film stack 30a may include an ONO layer 32a, a polysilicon layer 34a and a cap layer 36a, but it is not limited thereto. As shown in FIG. 5, the isolation structures 12 are formed in the substrate 110 (120), and therefore the substrate 110 (120) is sandwiched by the isolation structures 12, and a floating gate film stack 30b covering the substrate 120 and sandwiched by the isolation structures 12 is also formed. As shown in FIG. 6, which is the cross-sectional view along the line BB of FIG. 1, the floating gate film stack 30b is patterned to form the row of floating gates 30 having staggered islands.
(19) As shown in FIG. 7, which is the cross-sectional view along the line BB of FIG. 1, spacers 37 are formed beside the row of floating gates 30. A source line 50 is implanted in the substrate 110 beside a side S1 of the row of floating gates 30.
(20) As shown in FIG. 8, which is the cross-sectional view along the line BB of FIG. 1, a word line well 60 is doped in the substrate 110 at a side S2 of the row of floating gates 30.
(21) As shown in FIG. 9, which is the cross-sectional view along the line BB of FIG. 1, the row of erase gate 20 having the wave shape is formed on the substrate 110 at the side S1 of the row of floating gates 30, and the row of word line 40 having the wave shape is formed on the substrate 110 at the side S2 of the row of floating gate 30 opposite to the side S1. In this case, the row of erase gate 20 and the row of word line 40 are formed at a same time, but the present invention is not restricted thereto. Thus, the source line 50 is located right below the row of erase gate 20.
(22) As shown in FIG. 10, which is the cross-sectional view along the line BB of FIG. 1, a halo implantation region 72 and a lightly doped region 76 are formed in the word line well 60 beside the row of word line 40 and a heavily doped region 78 is formed in the lightly doped region 76 beside the row of word line 40. Above all, methods of forming said components are well known in the art, and are not described.
(23) To summarize, the present invention provides an array of electrically erasable programmable read only memory (EEPROM) and forming method thereof, which includes isolation structures defined in a substrate, a row of erase gate having a wave shape disposed across the substrate, a row of floating gates having staggered islands disposed parallel to the row of erase gate, and a row of word line having the wave shape disposed parallel to the row of erase gate and at a side of the row of floating gates opposite to the row of erase gate. By doing this, floating gates of the row of floating gates are dislocated and thus the spacings of the adjacent floating gates of the rows of floating gates increase. Hence, the cross talk capacitance is reduced, and there is no impact on the macro size of the array of erasably programmble read only memory cells.
(24) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
