DIGITAL SWITCHING MATRIX

Abstract

The present invention provides the signals received from different antennas (100) in a certain frequency range with micro-miniature input connectors (101) on a printed circuit, amplified and filtered with the help of RF frontend, and then passed to digital domain (109) with analog-digital converter (107) and further then it performs the switching of the signal by transmitting the signal to the FPGA (110). The signal switched in the FPGA (110) is sent to the related digital-analog converter (107) to be routed to the related output port. The digital-analog converter (112), on the other hand, sends the signal analog to one of the micro-miniature output connectors (114) on the output, and performs the reception of the signal from that output port. In the application of the present invention, a structure with a frequency band of 4 MHz - 50 MHz (HF band) and 32 inputs and 32 outputs has been implemented specifically.

Claims

1. A digital switching matrix comprises, at least one four-channel analog-to-digital converter-ADC (107), at least 1 four-channel digital to analog converter-DAC (112), at least 1 FPGA (110) element with the logic gate cells (108) inside and at least 4 Micro Miniature Coaxial Input Connectors (101) receiving incoming analog signals (142) and at least 4 Micro Miniature Coaxial Output Connectors (114) receiving digital signals (111), at least 4 amplifiers (102), at least 8 converters (115), at least 4 RF output transformers (132) and digital domain (109).

2. A working method of the digital switching matrix according to the claim 1, characterized in that after the analog signals (142) coming to the input connectors (101) are amplified and filtered by the amplifier (102), sampling the analog signals (142) with the analog-to-digital converter (ADC) (107) the signal converted to the digital signal (111) is directly given to the FPGA (110) and switching it in the digital domain(109) with the logic gate cells (108) in the FPGA (110).

3. The working method of the digital switching matrix according to claim 1, N input connectors (101) – N output connectors (114), both in analog and digital domain(109), are switched in such a way that the inputs and outputs do not block each other.

4. The working method of the digital switching matrix according to claim 3, characterized in that N is a positive integer from 4 to 128, including 4 and 128, and multiples of 4.

5. The working method of the digital switching matrix according to claim 3, characterized in that transfering the the digital signal (111) which is switched in the digital domain (109) to the analog domainagain with the digital analog converter (DAC) (112) and converting it into a single signal with the RF output transformer (132) and routing it to the corresponding micro-miniature coaxial output connector (114) by means of digital analog converter channels (113).

6. The working method of the digital switching matrix according to claim 3, characterized in that receiving the digital signal (111), which is switched in the FPGA (110), from the relevant output port (114) with the help of the digital analog converter (DAC) (112) and giving the signal (142) converted from the digital signal (111) to the analog signal (142) with the DAC (112) directly to the desired output (114).

Description

DESCRIPTION OF FIGURES

[0009] FIG. 1 – It is a demonstration of the entire block structure of the developed digital switching matrix.

[0010] FIG. 2 – It is the illustration of the block with four-channel eight analog-to-digital converters of the developed digital switching matrix.

[0011] FIG. 3 – It is the representation of the block with programmable logic gates (FPGA) in the area where the switching mechanism of the developed digital switching matrix is realized.

[0012] FIG. 4 – It is the illustration of the output stage block with four-channel eight digital-analog converters of the developed digital switching matrix.

[0013] FIG. 5 – It is a representation of the size of the developed system.

[0014] FIG. 6a – It is a demonstration of the full fan-out switching structure of the developed system.

[0015] FIG. 6b – It is a demonstration of the non-blocking switching structure of the developed system.

[0016] FIG. 7 – It is a demonstration of the front floor structure of the developed system.

[0017] FIG. 8 – Flow diagram of the developed system.

EXPLANATION OF REFERENCES IN FIGURES

[0018] 100: Antenna

[0019] 101: Micro Miniature Coaxial Input Connector/Input port

[0020] 102: 5 MHz - 1500 MHz RF Amplifier

[0021] 103: CH1, 1. Channel

[0022] 104: CH2, 2. Channel

[0023] 105: CH3, 3. Channel

[0024] 106: CH4, 4. Channel

[0025] 107: Four Channel Analog Digital Converter

[0026] 108: Logic Gate Cells

[0027] 109: Programmable Interconnects - Digital Environment

[0028] 110: Field Programmable Logic Gates (FPGA)

[0029] 111: Digital Signal

[0030] 112: Four Channel Digital Analog Converter

[0031] 113: Digital to Analog Converter Channel

[0032] 114: Micro Miniature Coaxial Output Connector/Output port

[0033] 115: 0.4 MHz - 800 MHz RF Converter

[0034] 116: Surface Mount Capacitor

[0035] 117: Four Channel Analog Digital Converter on PCB

[0036] 118: 50 MHz Low Pass Filter

[0037] 119: DC - 7000 MHz RF Amplifier

[0038] 120: Voltage Controlled Oscillator

[0039] 121: Single Input 16 Output Signal Divider

[0040] 122: Two Input Single Output Signal Combiner

[0041] 123: Surface Mount Resistor

[0042] 124: FPGA Protective Cover

[0043] 125: FPGA Control Pins/Connectors

[0044] 126: Buffer/Line Drivers

[0045] 127: FPGA Main Power Connector

[0046] 128: FPGA External Power Connector

[0047] 129: 50 MHz Output Filter

[0048] 130: Micro Miniature Coaxial Output Connector on PCB

[0049] 131: Four Channel Digital Analog Converter on PCB

[0050] 132: RF Output Transformer

[0051] 133: Surface Mount High-Q Inductor

[0052] 134: Representative Input Connector

[0053] 135: Possible Switching Combinations

[0054] 136: Representative Input Connector Notation

[0055] 137: Micro Miniature Coaxial Input Connector on PCB

[0056] 138: Surface Mount High-Q Capacitance

[0057] 139: 5 MHz - 300 MHz RF Converter

[0058] 140: Input Signal

[0059] 141: Transferring the Analog Signal to Digital Domain with ADC

[0060] 142: Analog Signal

[0061] 143: Selection of Relevant Input Port over FPGA according to the data from the Interface

[0062] 144: Selection of Relevant Output Port over FPGA according to the data from the Interface

[0063] 145: Converting the Digital Signal to Analog Domain with DAC

[0064] 146: Output Signal

DISCLOSURE OF THE INVENTION

[0065] The present invention consists of receiving analog signals (142) coming from different antennas (100) in the 4 MHz - 50 MHz range with micro-miniature coaxial (MMCX) input connectors (101) on a printed circuit, After receiving the signals from MMCX input connectors, they are amplified with 5-1500 MHz RF amplifier (102) then filtering the signals with a filter made of surface mount high Q capacity (138) and surface mount high Q inductances (133), then the signals are converted to differential with RF converter (139) operating at between 5 - 300 MHz, then transferred to digital domain (109) with an analog to digital converter (107). It includes the ralization of switching functions of the digital signals (111) with the logic gate cells (108) located in the field programmable logic gates (FPGA) (110). The digital signal, which is switched in the digital domain (109), is converted to analog signal with a digital analog converter (112) and passed back to the analog domain (the part after DAC (112) - See FIG. 1), and it is connected with the RF output transformer (132) in the RF output stage. It is converted into a single signal and routed to the corresponding micro-miniature coaxial output connector (114) by means of digital analog converter channels (113).

[0066] Since the 5 - 1500 MHz RF amplifier (102) on the RF frontend must be present as one at each input port, the number of amplifiers (102) will increase as the number of inputs in the system increases.

[0067] The RF converter (115) used in the system also changes depending on the number of inputs. There are at least two RF converters at each input. For example, when the number of inputs and outputs is 4×4, 8 RF converters (115) will be needed and at least 4 RF output transformers (132) will be needed on the output floor.

[0068] The mentioned FPGA (110) used in the current system has 504,000 logic cells and has the ability to operate at 454 I/O, 533 MHz, 600 MHz or 1.3 GHz speeds. The FPGA (110) used in the system contains 900 pins in total.

[0069] In the application of the present invention, the matrix structure in the high frequency (HF) band with 32 inputs and 32 outputs is realized specifically. The present invention consists of at least 8 four-channel analog-to-digital converters (107) and at least 8 four-channel digital-to-analog converters (112) with at least one FPGA (110) element and 32 microminiature input connectors (101) and microminiature output connector (114). All 8 DACs (112) in the present invention are identical to each other. Each of them contains 4 channels and there are 32 channels in total. The system consists of a printed circuit containing all the components mentioned above. Printed circuit refers to all components, including input ports and output ports. Analog to digital converters (ADC) (107), digital to analog converters (DAC) (112), FPGA (110) and all other components are on the printed circuit board.

[0070] This switching matrix system can switch N inputs – N outputs in two different combinations, with N input and output ports, in a way that the inputs and outputs cannot be blocked in both analog and digital environments (non-blocking full fan-out). Here N; expresses a positive integer from 4 to 128, multiples of 4 including 4 and 128. FIGS. 6a and 6b show in which combinations the switching matrix can switch input signals to output ports. For example, for FIG. 6a (full fan-out switching structure), the user can route a single input signal to all outputs simultaneously. FIG. 6b shows that any input can be switched to any output. These switching operations are done with the logic gates in the FPGA. The present invention can do both switching, the choice belongs to the user. For example, the user may want to redirect inputs 1 and 2 to any output 1 to 32. In fact, the user can direct inputs from 1 to 32 to a single output or to different outputs separately. The user can route all signals from inputs 1 to 32 to any output from 32 outputs as desired. Likewise, it can direct these signals to different outputs. For example, it can route the 1st input signal to the 32nd output and the 2nd input signal to the 15th output. While doing these, any input does not block any output or any other signal.

[0071] The present invention does not use any RF switch, RF power combiner or RF power divider. The size of the printed circuit is rectangular and there is at least one FPGA (110) on the board that can operate at 533 MHz - 1300 MHz speeds. All switching functions are performed in a digital environment (109) within a single FPGA (110). In the present invention, an analog to digital converter (107) is used to convert the analog signal (142) to digital. Likewise, after the analog signal (142) is converted to digital and switching function is performed in the FPGA (110), the signal is given to the related digital-analog converter (DAC) (112) to be directed to the desired output.

[0072] The presented invention can also be implement in bands such as very high frequency (VHF), and L-band. The present invention can be used in high frequency (HF), in the 4 -50 MHz frequency band and has been realized in a low cost and very small size of 30×36.5 cm (FIG. 5) for the multi-antenna - multi-receiver (32 × 32) switching need. However, this size may vary depending on the amount of input-output and the designer. Since the size of the system can be designed to have at least 4 inputs and 4 outputs, the size of the system can be at least 8×10 cm. The larger the number of inputs and outputs, the larger the size will be. In the application of the present invention (32 inputs 32 outputs), 8 ADCs (107) and 8 DACs (112) are used. Other embodiments of the present invention are noted in the examples below.

Example 1

[0073] In an embodiment of the present invention, a switching matrix system comprising; at least 1 four-channel analog-to-digital converter (107) and at least 1 four-channel digital-to-analog converter (112) and at least one FPGA (110) element, 4 microminiature input connectors (101), 4 microminiature output connectors (114), at least 4 amplifiers (102) and at least 8 RF converters (115), and at least 4 RF output stage transformers (132) is disclosed. The size of the switching matrix system designed in this way 4×4 can be at least 8×10 cm.

Example 2

[0074] In an embodiment of the present invention, a switching matrix system comprising; at least 2 four-channel analog-to-digital converters (107) and at least 2 four-channel digital-to-analog converters (112) and at least one FPGA (110) element, 8 microminiature input connectors (101), 8 microminiature output connectors (114), at least 8 amplifiers (102) and at least 16 RF converters (115), and at least 8 RF output stage transformers (132) is disclosed. The size of the matrix designed in this way 8×8 can be at least 14×16 cm.

Example 3

[0075] In one embodiment of the present invention, a switching matrix system comprising; at least 16 four-channel analog-to-digital converters (107) and at least 16 four-channel digital-to-analog converters (112) and at least two FPGA (110) elements, 64 microminiature input connectors (101), 64 microminiature output connectors 114, at least 64 amplifiers 102 and at least 128 RF converters (115), and at least 64 RF output stage transformers (132) is disclosed. The size of the matrix designed as 64×64 in this way can be at least 30×36.5 cm. Since the matrix structure to be designed as 64×64 cannot be designed as a single card, a 64×64 matrix structure can be obtained by using 2 of the existing 32×32 matrix structure. However, in the system, unlike the 32×32 system, it may be necessary to have a main control card to control the FPGA(110) on each card.

Example 4

[0076] In one embodiment of the present invention, a switching matrix system comprising; at least 32 four-channel analog-to-digital converters (107) and at least 32 four-channel digital-to-analog converters (112) and at least four FPGA (110) elements, 128 microminiature input connectors (101),128 microminiature output connectors (114), at least 128 amplifiers (102) and at least 256 RF converters (115) and 128 RF output stage transformers (132) is disclosed. The size of the matrix designed as 128×128 in this way can be at least 30×36.5 cm. Since the matrix structure to be designed as 128×128 cannot be designed as a single card here, a 128×128 matrix structure can be obtained by using 4 of the existing 32×32 matrix structure. However, in the system, unlike the 32×32 system, it may be necessary to have a main control card to control the FPGA(110) on each card.

Industrial Application of the Invention

[0077] The present invention is used in design verification and production tests in the defense industry, wireless communication, aerospace industry. Switching matrices are used in multi-antenna - multi-receiver switching, TV and satellite systems, multi-port measurement setups, beaming in phased array antenna systems. With the developed method, a cost effective product has been created. In the present invention, unlike the classical switching mechanism, each input port can be connected to output ports independently of each other, and one input can be connected to more than one input at the same time. In the application presented with this invention, since the switching function is made in the FPGA (110), filtering and various mathematical operations that can be applied in the digital environment can be applied to the signal. This provides a wide application freedom for the operator.