DIFFERENTIAL CURRENT BUFFER CIRCUIT AND DC AND ALTERNATING CURRENT SOURCE COMPRISING THE SAME

Abstract

A differential current buffer circuit comprises a differential input stage supplied from a first positive and a first negative supply voltage. The input stage has a first input circuit connected between first current paths of a first current and a second mirror connected between second positive and negative supply voltages. A second input circuit is connected between first current paths of a third and a fourth current mirror connected between the second positive and negative supply voltages. The second positive voltage is higher than the first positive supply voltage, and the second negative voltage is lower than the first negative supply voltage. A first and a second output of the differential current buffer circuit are tapped off between the respective second current paths of the first and second current mirrors and the respective second current paths of the third and fourth current mirrors, respectively.

Claims

1. Differential current buffer circuit (100) comprising a differential input stage (300) that is powered from a first positive supply voltage (+V1) and a first negative supply voltage (V1), wherein the differential input stage (300) has a first input circuit whose outputs are connected between a first current path (318) of a first output current mirror connected to a second positive supply voltage (+V2) and a first current path (322) of a second mirror connected to a second negative supply voltage (V2), and a second input circuit whose outputs are connected between a first current path (310) of a third output current mirror connected to the second positive supply voltage (+V2) and a first current path (314) of a fourth output current mirror connected to the second negative supply voltage (V2), wherein, referred to a reference potential, the second positive supply voltage (+V2) is higher than the first positive supply voltage (+V1) and the second negative supply voltage (V2) is lower than the first negative supply voltage (V1), and wherein a first output (O1) of the differential current buffer circuit (100) is tapped off between the respective second current paths (320, 324) of the first and second output current mirrors, and wherein a second output (O2) of the differential current buffer circuit (100) is tapped off between the respective second current paths (312, 316) of the third and fourth output current mirrors.

2. Differential current buffer circuit (100) according to claim 1, wherein the first and the second input circuit each comprises two complementary current mirrors connected in series, and wherein the input nodes (I1, I2) are located at a connection of the two complementary current mirrors.

3. Differential current buffer circuit (100) according to claim 2, wherein the first input circuit and the second input circuit of the differential input stage (300) are connected to a shared bias leg and form a differential translinear input cell, wherein the shared bias leg is powered from the first positive supply voltage (+V1) and the first negative supply voltage (V1).

4. Differential current buffer circuit (100) according to claim 3, wherein the shared bias leg is connected to the first positive supply voltage (+V1) via a first bias current source and to the first negative supply voltage (V1) via a second bias current source.

5. Differential current buffer circuit (100) according to claim 4, wherein the first bias current source corresponds to a second current path (212) of a first bias current mirror and the second bias current source corresponds to a second current path (216) of a second bias current mirror, wherein the input stage bias current (I.sub.0) is set by a current source (220) coupled upstream and downstream, respectively, to first current paths (210, 214) of the first and the second bias current mirrors.

6. Differential current buffer circuit (100) according to claim 2, wherein the series-connected complementary current mirrors of the first input circuit and the second input circuit each comprises its own bias leg, wherein each bias leg is connected between the first positive supply voltage (+V1) and the first negative supply voltage (V1), wherein the input nodes (I1, I2) are located at the connection of the complementary current mirrors in the respective bias legs, wherein outputs of the complementary current mirrors are connected to first current paths (310, 314, 318, 322) of the associated output current mirrors, and wherein the connections of the complementary current mirrors in the output current paths are tied to a reference potential.

7. Differential current buffer circuit (100) according to claim 1, wherein the output current mirrors are cascode current mirrors, Wilson current mirrors, or improved Wilson current mirrors using bipolar or field-effect transistors.

8. DC and alternating current source (400) comprising a differential operational amplifier (10) connected in a differential Howland current source configuration, whose differential outputs are connected to the corresponding input nodes (I1, I2) of a differential current buffer circuit (100) according to claim 1, wherein first feedback signals (NF1, PF1) to the non-inverting and inverting inputs of the amplifier, respectively, are tapped off the load-side terminals of respective output resistors (R6, R7) connected between the outputs (O1, O2) of the differential current buffer circuit (100) and the load (R3), the load-side terminals representing the actual output of the alternating current source (400).

9. DC and alternating current source (400) according to claim 8, wherein the differential operational amplifier (10) is connected in a quad-feedback enhanced Howland current source configuration, wherein additional second feedback signals (NF2, PF2) to the non-inverting and inverting inputs of the operational amplifier (10), respectively, are tapped off at buffer-side terminals of the respective opposing output resistor (R6, R7).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In the following section, the invention will be described with reference to the attached drawings, in which

[0023] FIG. 1a shows a schematic circuit diagram of a known Howland current source,

[0024] FIG. 1b shows a schematic circuit diagram of a known quad-feedback enhanced Howland current source,

[0025] FIG. 2 shows a schematic circuit diagram of a translinear input cell,

[0026] FIG. 3 shows a circuit diagram of a first exemplary differential current buffer circuit in accordance with a first aspect of the invention,

[0027] FIG. 4 shows a circuit diagram of a second exemplary differential current buffer circuit in accordance with a first aspect of the invention,

[0028] FIG. 5 shows a circuit diagram of a DC and alternating current source comprising the first exemplary differential current buffer circuit of FIG. 3 connected to an operational amplifier in a quad-feedback enhanced Howland current source circuit arrangement, and

[0029] FIG. 6 shows a circuit diagram of a DC and alternating current source comprising the second exemplary differential current buffer circuit of FIG. 4 connected to an operational amplifier in a quad-feedback enhanced Howland current source circuit arrangement.

[0030] In the drawings, identical or similar elements may be referenced using the same reference designator.

DETAILED DESCRIPTION OF EMBODIMENTS

[0031] FIGS. 1a and 1b have been described in the background section and will not be addressed again.

[0032] FIG. 2 shows a schematic circuit diagram of a translinear input cell 20. The base electrodes of two pairs of transistors, T1, T2, and T3, T4, respectively, are each connected and are also connected to respective bias potentials. The bias potentials are provided from a bias leg of the translinear input cell. In the example, the bias leg comprises two current sources, each providing a current I.sub.o that are series-connected upstream and downstream, respectively, of two diodes, D1 and D2, connected in series in forward direction. Note that diode-connected transistors may also be used. The series connection is connected between a positive voltage V and a negative voltage V. To provide a proper centering of the translinear input cell, the connection between the two diodes D1 and D2 is connected to a reference potential Z, e.g., ground.

[0033] The two pairs of transistors, T1, T2, and T3, T4, respectively, are stacked upon each other such that each side of the transistor pairs is connected, i.e., the emitter electrodes of transistors T1 and T3 are connected, and the emitter electrodes of transistors T2 and T 4 are connected. Differential input signals are connected to input nodes X and Y, which are formed between the respective emitter electrode connections. Output I1 to I4 currents flow through the collector electrodes of transistors T1, T3, and T2, T4, respectively, depending on the input signals applied to the input nodes X, Y, and the further circuitry connected thereto.

[0034] FIG. 3 shows a circuit diagram of a first exemplary differential current buffer circuit 100 in accordance with a first aspect of the invention. FIG. 3 a) shows a bias power supply circuit 200, while FIG. 3 b) shows an input stage 300 and the output stages of the differential current buffer circuit.

[0035] The bias power supply circuit 200 shown in FIG. 3 a) comprises a first bias current mirror whose first current path 210 is connected to a first positive supply voltage +V1 and a first terminal of a current source 220. The bias power supply circuit 200 further comprises a second bias current mirror whose first current path 214 is connected between a second terminal of current source 220 and a first negative supply voltage V1. It is to be noted that throughout this specification, the first and second positive and negative supply voltages are referred to a reference potential, e.g., ground, and are preferably symmetrical. The second current paths 212 and 216, respectively, of the first and the second bias current mirrors, form the bias current outputs, which provide power to the differential input stage 300. The bias power supply circuit 200 advantageously requires only one current source for setting the bias current, while the bias current mirrors simply copy the set current to the positive and negative supply lines.

[0036] The differential current buffer shown in FIG. 3 b) has a differential input stage 300, which is similar to the translinear input cell 20 discussed with reference to FIG. 2. Different from the translinear input cell of FIG. 2, the emitters of transistors Q1, Q5, and Q3, Q4, respectively, are not directly connected but are connected through two resistors, R25, R30, and R27, R28, respectively, which are connected in series. The input nodes I1 and I2 are formed between the two respective resistors. Power to the differential input stage is provided from a first positive supply voltage +V1 and a first negative supply voltage V1. In the present differential input circuit, power is provided to the biasing circuit from bias power supply circuit 200. The diodes D1 and D2 of the bias leg of the circuit of FIG. 2 are replaced by diode-connected transistors Q2 and Q6, which are preferably of the same type and even more preferably from the same production lot as transistors Q1, Q3, and Q4, Q5, respectively. In addition, these diodes are not directly connected to each other but are connected through two resistors, R26, R29 connected in series, which provide emitter degeneration to stabilize the operating point of the input stage in light of transistor variation thorough a corresponding setting of the bias current I.sub.O powering the differential input stage. The connection between the two resistors R26 and R29 is connected to ground for reference potential. Transistors Q3 and Q4, together with emitter degeneration resistors R27 and R28, form a first input circuit, and transistors Q1 and Q5, together with emitter degeneration resistors R25 and R30, form a second input circuit.

[0037] Outputs of the first input circuit are connected between the first current path 318 of the first output current mirror circuit connected to a second positive supply voltage +V2 and the first current path 322 of a second output current mirror circuit connected to a second negative supply voltage V2.

[0038] Outputs of the second input circuit are connected between the first current path 310 of a third output current mirror circuit connected to a second positive supply voltage +V2 and the first current path 314 of a fourth output current mirror circuit connected to a second negative supply voltage V2.

[0039] A first output O1 of the differential buffer circuit 100 is tapped off between the respective second current paths 320, 324 of the first and second output current mirrors, which are tied together and which are powered by the second positive supply voltage +V2 and the second negative supply voltage V1, respectively.

[0040] A second output O2 of the differential buffer circuit 100 is tapped off between the respective second current paths 312, 316 of the third and fourth output current mirrors, which are tied together and which are powered by the second positive supply voltage +V2 and the second negative supply voltage V1, respectively.

[0041] The first and the second input circuit each form complementary current mirrors connected in series, which have a shared bias leg, and whose respective output current is controlled by a current applied to the respective input node I1 or I2. The input current modifies the respective currents through each of the complementary current mirrors, which are connected to the first current paths of the associated output current mirrors. The currents through the first current paths of the output current mirrors are matched in the respective second paths of the output current mirrors and are available at a corresponding output O1 and O2, respectively.

[0042] FIG. 4 shows a circuit diagram of a second exemplary differential current buffer circuit in accordance with the first aspect of the invention. The output stages of the differential current buffer circuit correspond to those described with reference to FIG. 3 b). The input stage 300 is of a different design. Here, an individual bias leg of each input circuit of the input stage 300 is directly powered from the first positive and negative supply voltages +V1, V1, respectively.

[0043] The first input circuit, comprising transistors Q2, Q3, Q4, and Q6 and resistors R26, R27, R28, R29, R30, and R31, has its input node in the bias leg, more particularly in the center point of the series connection of resistors R26 and R29 that connect diode-connected transistors Q2 and Q6. The anode of diode-connected transistor Q2 is connected to the first positive supply voltage +V1 through resistor R31, and the cathode of diode-connected transistor Q6 is connected to the first negative supply voltage V1 through resistor R30. Resistors R26, R29, R30, and R31 will set the bias current in the bias leg of the first input circuit. The ratio of R31/R26 and R30/R29 will set the gain of the current buffer, and R30=R31 and R26=R27=R28=R29 for correct operation.

[0044] Outputs of the first input circuit are connected between a first current path 318 of a first output current mirror circuit connected to a second positive supply voltage +V2 and a first current path 322 of a second output current mirror circuit connected to a second negative supply voltage V2. The outputs of the first input circuit are formed by the collector electrodes of transistors Q3 and Q4, respectively, whose emitter electrodes are connected to a reference potential, here: ground, through resistors R27 and R28, respectively.

[0045] The second input circuit, comprising transistors Q1, Q5, Q17, and Q20 and resistors R9, R10, R11, R14, R19, and R25, likewise has its input node in the bias leg, more particularly in the center point of the series connection of resistors R10 and R19 that connect diode-connected transistors Q1 and Q20. The anode of diode-connected transistor Q1 is connected to the first positive supply voltage +V1 through resistor R9, and the cathode of diode-connected transistor Q20 is connected to the first negative supply voltage V1 through resistor R25. Resistors R9, R10, R19, and R25 will set the bias current in the bias leg of the second input circuit. The ratio of R25/R19 and R9/R10 will set the gain of the current buffer, and R9=R25 and R10=R11=R14=R19 for correct operation.

[0046] Outputs of the second input circuit are connected between a first current path 310 of a third output current mirror circuit connected to a second positive supply voltage +V2 and a first current path 314 of a fourth output current mirror circuit connected to a second negative supply voltage V2. The outputs of the second input circuit are formed by the collector electrodes of transistors Q5 and Q17, respectively, whose emitter electrodes are connected to a reference potential, here: ground, through resistors R11 and R148, respectively.

[0047] The first and second input circuit each form complementary current mirrors connected in series, whose respective output current is controlled by a voltage applied to the respective input node I1 or I2. The input voltage modifies the respective currents through each of the complementary current mirrors, which are connected to the first current paths of the associated output current mirrors. The currents through the first current paths of the output current mirrors are copied in the respective second paths of the output current mirrors and are available at a corresponding output O1 and O2, respectively.

[0048] Like in the differential buffer circuit 100 discussed with reference to FIG. 3, a first output O1 of the differential buffer circuit 100 is tapped off between the respective second current paths 320, 324 of the first and second output current mirrors, which are tied together and which are powered by the second positive supply voltage +V2 and the second negative supply voltage V1, respectively. A second output O2 of the differential buffer circuit 100 is tapped off between the respective second current paths 312, 316 of the third and fourth output current mirrors, which are tied together and which are powered by the second positive supply voltage +V2 and the second negative supply voltage V1, respectively.

[0049] FIG. 5 shows a circuit diagram of a DC and alternating current source 400 comprising the first exemplary differential current buffer circuit 100 of FIG. 3 connected to a fully differential operational amplifier 10 in a quad-feedback enhanced Howland current source circuit arrangement. The differential current buffer circuit 100 comprises a bias power supply circuit 200, as shown in FIG. 3 a) and the actual buffer circuit shown in FIG. 3 b).

[0050] The first output O1 of the differential current buffer circuit 100 is connected to a load, represented by R3, via an output resistor R6, which serves as a current sensing resistor. The second output O2 of the differential current buffer circuit 100 is connected to the load via an output resistor R7, which serves as a current sensing resistor.

[0051] A first negative feedback signal NF1 is tapped off between the load R3 and load-side terminals of output resistor R6. The first negative feedback signal NF1 is fed to the inverting input of operational amplifier 10 via resistor R19. A first positive feedback signal PF1 is tapped off between the load R3 and load-side terminals of output resistor R7. The first positive feedback signal PF1 is fed to the non-inverting input of operational amplifier 10 via resistor R14.

[0052] A second negative feedback signal NF2 is tapped off between the second output O2 of the differential current buffer circuit 100 and a buffer-side terminal of output resistor R7. The second negative feedback signal NF2 is fed to the inverting input of operational amplifier 10 via a voltage divider to ground comprising resistors R15 and R16. A second positive feedback signal PF2 is tapped off between the first output O1 of the differential current buffer circuit 100 and a buffer-side terminal of output resistor R6. The second positive feedback signal PF2 is fed to the non-inverting input of operational amplifier 10 via a voltage divider comprising resistors R17 and R18 to a signal source SIG. Signal source SIG is referenced to ground and, being a voltage source, represents a ground connection for the second positive feedback signal PF2.

[0053] Operational amplifier 10 may be powered from positive and negative supply voltages Vcc and Vee, respectively, which may be independent from the first supply voltages +V1 and V1. Common mode offsets at the output may be trimmed using a corresponding trim voltage VCOM at a corresponding input of operational amplifier 10.

[0054] Resistors R10 and R11 between the outputs of operational amplifier 10 and the first input I1 and the second input I2, respectively, of the differential current buffer circuit 100 may be required for stability. However, they may require a higher output swing from the operational amplifier 10 to produce the required input current to the inputs I1 and I2 of the differential current buffer circuit 100. These resistors may need to be properly selected for optimal step response and minimal ringing or overshoot, i.e., resistors having a low parasitic inductance may be preferred.

[0055] Resistors R4 and R5 connected to ground provide a path to ground across the load R3, effectively being parts of voltage dividers that permit monitoring the output voltage. However, resistors R4 and R5 also limit the maximum output impedance of the current source 400 to the sum of the values of resistors R4 and R5. The frequency response of the current source will be limited by the input capacitance of operational amplifier 10, which will typically be a few pF only.

[0056] Closing the quad-feedback loop around the entire circuit, as shown in the figure, ensures the lowest possible distortion of the output signal applied to the load.

[0057] FIG. 6 shows a circuit diagram of an DC and alternating current source 400 comprising the second exemplary differential current buffer circuit 100 of FIG. 4 connected to an operational amplifier in a quad-feedback enhanced Howland current source circuit arrangement.

[0058] Like in the DC and AC current source of FIG. 5, feedback is applied around the whole circuit. R6 and R7 are the current sensing resistors, and the quad-feedback goes back to the input of the fully differential operational amplifier 10 drive stage. Again, applying feedback around the entire circuit ensures the lowest possible distortion.

[0059] Different from the circuit of FIG. 5, in this circuit, there are no resistors at the output of the operational amplifier as the differential buffer requires a voltage drive. Any output common-mode offset voltages can be trimmed using the VCOM input to the operational amplifier 10.

[0060] Resistors R4 and R5 connected to ground, like in the circuit of FIG. 5, provide a path to ground across the load R3, effectively being parts of voltage dividers that permits monitoring the output voltage. Likewise, resistors R4 and R5 also limit the maximum output impedance of the DC and alternating current source 400 to the sum of the values of resistors R4 and R5. The frequency response of the current source will be limited by the input capacitance of operational amplifier 10, which will typically be a few pF only. The output DC offset is controlled using the VCOM input to the fully differential operational amplifier 10.

[0061] For the highest accuracy, the differential current buffer circuit 100 is preferably operated in class-A mode, which can be achieved by properly adjusting the respective bias currents.

[0062] In this circuit, the first positive and negative supply voltages +V1, V1 of the differential current buffer circuit 100 are the same supply voltages Vcc and Vee, respectively, that power operational amplifier 10.

[0063] As shown in FIGS. 3 and 4, the output current mirrors may be implemented as cascode current mirrors. Due to the finite output resistance of the transistors, simple current mirrors exhibit a dependency of the output current from the output voltage. Cascode current mirrors may significantly reduce this dependency.

LIST OF REFERENCE NUMERALS (PART OF THE DESCRIPTION)

[0064] 10 operational amplifier [0065] 20 translinear input cell [0066] 100 differential current buffer [0067] 200 bias power supply [0068] 210 first current path of first bias current mirror [0069] 212 second current path of first bias current mirror [0070] 214 first current path of second bias current mirror [0071] 216 second current path of second bias current mirror [0072] 300 differential input stage [0073] 318 first current path of first output current mirror [0074] 320 second current path of first output current mirror [0075] 322 first current path of second output current mirror [0076] 324 second current path of second output current mirror [0077] 310 first current path of third output current mirror [0078] 312 second current path of third output current mirror [0079] 314 first current path of fourth output current mirror [0080] 316 second current path of fourth output current mirror [0081] 400 alternating current source [0082] D1, D2 Diodes [0083] I1-I4 output currents [0084] I.sub.O bias current [0085] I1 first input [0086] I2 second input [0087] NF1 first negative feedback signal [0088] NF2 second negative feedback signal [0089] O1 first output [0090] O2 second output [0091] PF1 first positive feedback signal [0092] PF2 second positive feedback signal [0093] Q1-Q36 transistors [0094] R1-R30 resistors [0095] SIG signal source [0096] T1-T4 transistors [0097] +V1 first positive supply voltage [0098] +V2 second positive supply voltage [0099] V1 first negative supply voltage [0100] V2 second negative supply voltage [0101] Vcc operation amplifier positive supply voltage [0102] VCOM common-mode trim [0103] Vee operation amplifier negative supply voltage [0104] V.sub.X output node [0105] X, Y input nodes [0106] Z reference potential [0107] Z.sub.L load