STACK STRUCTURE AND MANUFACTURING METHOD THEREOF, CAPACITOR USING THE SAME, TRANSISTOR USING THE SAME, DYE-SENSITIZED SOLAR CELL USING THE SAME, AND ARCHITECTURAL FILM FOR WINDOW GLASS COATING USING THE SAME

Abstract

Provided is a method for manufacturing a stack structure. The method for manufacturing a stack structure includes: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a high-k material layer including the high-k material. The stack structure manufactured through the above-described method may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.

Claims

1.-5. (canceled)

6. A method for manufacturing a stack structure, the method comprising: preparing a substrate; forming a channel layer including a two-dimensional (2D) semiconductor material on the substrate; and oxidizing the channel layer to form a dielectric layer including a high-k material.

7. The method of claim 6, wherein as the channel layer is oxidized, one region of the channel layer is converted into the dielectric layer including the high-k material, and the other region of the channel layer remains as the channel layer including the two-dimensional semiconductor material.

8. The method of claim 6, wherein the high-k material is formed by oxidizing the two-dimensional semiconductor material.

9. The method of claim 6, wherein the dielectric layer is formed by oxidizing the channel layer using oxygen (O.sub.2) plasma.

10. The method of claim 9, wherein a thickness of the dielectric layer is controlled according to an exposure time of the channel layer to the oxygen (O.sub.2) plasma.

11.-16. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG. 1 is a flowchart for explaining a method for manufacturing a stack structure according to an embodiment of the present invention.

[0041] FIGS. 2 and 3 are schematic views for explaining a process of manufacturing a stack structure according to the embodiment of the present invention.

[0042] FIGS. 4 to 6 are schematic views for explaining a method for manufacturing a HfO.sub.2/HfSe.sub.2 stack structure.

[0043] FIG. 7 is a schematic view for explaining a manufacturing mechanism of the HfO.sub.2/HfSe.sub.2 stack structure in more detail.

[0044] FIG. 8 is a schematic view for explaining a HfSe.sub.2 oxidation process at an appropriate oxygen concentration.

[0045] FIG. 9 is a schematic view for explaining a HfSe.sub.2 oxidation process at an excessive oxygen concentration.

[0046] FIG. 10 is a flowchart for explaining a method for manufacturing g a capacitor using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0047] FIG. 11 is a schematic view for explaining the capacitor using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0048] FIG. 12 is a flowchart for explaining a method for manufacturing a field effect transistor using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0049] FIG. 13 is a schematic view for explaining the field effect transistor using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0050] FIG. 14 is a flowchart for explaining a method for manufacturing an impact ionization super-tilt switching device using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0051] FIG. 15 is a schematic view for explaining the impact ionization super-tilt switching device using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0052] FIG. 16 is a schematic view for explaining an architectural film using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0053] FIG. 17 is a schematic view for explaining a solar cell using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0054] FIG. 18 is a schematic view for explaining a first modification example of the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0055] FIGS. 19 and 20 are schematic views for explaining a second modification example of the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0056] FIG. 21 is a schematic view for explaining a third modification example of the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0057] FIG. 22 is a TEM image of HfSe.sub.2 oxidized with oxygen plasma having power of 7 W.

[0058] FIG. 23 is a TEM image of HfSe.sub.2 oxidized with oxygen plasma having power of 8 W.

[0059] FIG. 24 is a TEM image of HfSe.sub.2 oxidized with oxygen plasma having power of 10 W.

[0060] FIG. 25 is a TEM image of HfSe.sub.2 oxidized with oxygen plasma having power of 20 W.

[0061] FIG. 26 is a TEM image of HfSe.sub.2 oxidized with oxygen plasma having power of 30 W.

[0062] FIG. 27 is a view for explaining an OM image and thickness change profile of HfSe.sub.2 before being oxidized with oxygen plasma.

[0063] FIG. 28 is a view for explaining an OM image and thickness change profile of HfSe.sub.2 oxidized with oxygen plasma for 3 minutes.

[0064] FIG. 29 is a view for explaining an OM image and thickness change profile of HfSe.sub.2 oxidized with oxygen plasma for 5 minutes.

[0065] FIG. 30 is a view for explaining a Raman analysis result for a plasma oxidation process of HfSe.sub.2.

[0066] FIG. 31 is a view for explaining a change in a thickness of HfSe.sub.2 according to plasma oxidation and a change in a thickness of HfO.sub.2 converted from HfSe.sub.2.

[0067] FIG. 32 is a view for explaining a conversion rate of HfSe.sub.2 according to plasma oxidation of HfSe.sub.2.

[0068] FIG. 33 is a schematic view for defining various parameters required for calculating the thickness of HfO.sub.2 converted from HfSe.sub.2.

[0069] FIG. 34 is a view for explaining an XPS analysis result of the HfO.sub.2/HfSe.sub.2 stack structure.

[0070] FIG. 35 is a view showing a STEM image and an FFT pattern for the HfO.sub.2/HfSe.sub.2 stack structure.

[0071] FIG. 36 is a view showing a STEM image and an EDS mapping result for the HfO.sub.2/HfSe.sub.2 stack structure.

[0072] FIG. 37 is a view showing a high-resolution STEM image for the HfO.sub.2/HfSe.sub.2 stack structure.

[0073] FIG. 38 is a view for explaining an XPS analysis result for each of HfO.sub.2 and HfSe.sub.2 in the HfO.sub.2/HfSe.sub.2 stack structure.

[0074] FIG. 39 is a view showing capacitance-voltage characteristics and a schematic view of a MOS capacitor according to Experimental Example 2.

[0075] FIG. 40 is a view showing conductance-voltage characteristics of the MOS capacitor according to Experimental Example 2.

[0076] FIG. 41 is a view for explaining a result of extracting an interface trap density of the MOS capacitor according to Experimental Example 2 by using conductance measured through FIG. 40.

[0077] FIG. 42 is a view for explaining an equivalent oxide thickness and a dielectric constant of the MOS capacitor according to Experimental Example 2.

[0078] FIG. 43 is a schematic view of a field effect transistor according to Experimental Example 3.

[0079] FIG. 44 is a view showing an ID-VG curve of the field effect transistor according to Experimental Example 3.

[0080] FIG. 45 is a view showing an ID-VG curve according to a gate voltage sweep of the field effect transistor according to Experimental Example 3.

[0081] FIG. 46 is a view showing an ID-VG curve according to a temperature of the field effect transistor according to Experimental Example 3.

[0082] FIG. 47 is a view showing a subthreshold swing value according to a temperature of the field effect transistor according to Experimental Example 3.

[0083] FIG. 48 is a view for explaining a simulation result of RC Delay characteristics according to an interface charge trap concentration of the field effect transistor according to Experimental Example 3.

[0084] FIG. 49 is a view showing electrical characteristics of the field effect transistor according to Experimental Example 3 in which a thickness ratio of HfO.sub.2:HfSe.sub.2 is 1:1.

[0085] FIG. 50 is a view showing electrical characteristics of the field effect transistor according to Experimental Example 3 in which a thickness ratio of HfO.sub.2:HfSe.sub.2 is 1:2.

[0086] FIG. 51 is a view showing electrical characteristics of the field effect transistor according to Experimental Example 3 in which a thickness ratio of HfO.sub.2:HfSe.sub.2 is 1:3.

[0087] FIG. 52 is a view for explaining a result of measuring a subthreshold swing value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 10 W is applied.

[0088] FIG. 53 is a view for explaining a result of measuring a subthreshold swing value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 15 W is applied.

[0089] FIG. 54 is a view for explaining a result of measuring a subthreshold swing value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 20 W is applied.

[0090] FIG. 55 is a view for explaining a result of measuring a subthreshold swing value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 25 W is applied.

[0091] FIG. 56 is a view for explaining a result of measuring a subthreshold swing value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 30 W is applied.

[0092] FIG. 57 is a view for explaining a result of measuring a leakage current value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having mutually different power is applied.

[0093] FIG. 58 is a schematic view of an impact ionization super-tilt switching device according to Experimental Example 4.

[0094] FIG. 59 is a view showing an ID-VG curve of the impact ionization super-tilt switching device according to Experimental Example 4.

[0095] FIG. 60 is a view showing an ID-VD curve of the impact ionization super-tilt switching device according to Experimental Example 4.

[0096] FIG. 61 is a view showing electron-hole pairs generated in a gate non-overlapping region of an impact ionization super-tilt switching device according to Experimental Example 4.

[0097] FIG. 62 is a view showing a threshold voltage according to a change in a thickness of HfO.sub.2 and a length of the gate non-overlapping region of the impact ionization super-tilt switching device according to Experimental Example 4.

[0098] FIG. 63 is a view showing channel currents according to various drain voltages and gate voltages of the impact ionization super-tilt switching device according to Experimental Example 4.

[0099] FIG. 64 is a view for explaining a change in electrical characteristics according to the change in the length of the gate non-overlapping region of the impact ionization super-tilt switching device according to Experimental Example 4.

[0100] FIG. 65 is a schematic view for explaining a process of manufacturing a transistor according to Experimental Example 5.

[0101] FIG. 66 is a view for explaining MoS.sub.2 semiconductor characteristics of the transistor according to Experimental Example 5.

[0102] FIG. 67 is a view for explaining a subthreshold swing value of the transistor according to Experimental Example 5.

[0103] FIG. 68 is a view for explaining Wse.sub.2 semiconductor characteristics of a transistor according to Experimental Example 6.

[0104] FIG. 69 is a view for explaining a subthreshold swing value of the transistor according to Experimental Example 6.

DETAILED DESCRIPTION OF THE INVENTION

[0105] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0106] In the present specification, it will be understood that when an element is referred to as being on another element, it can be formed directly on the other element or intervening elements may be present. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

[0107] In addition, it will be also understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present invention. Embodiments explained and illustrated herein include their complementary counterparts. As used herein, the term and/or includes any and all combinations of one or more of the associated listed elements.

[0108] The singular expression also includes the plural meaning as long as it does not differently mean in the context. In addition, the terms comprise, have etc., of the description are used to indicate that there are features, numbers, steps, elements, or combination thereof, and they should not exclude the possibilities of combination or addition of one or more features, numbers, operations, elements, or a combination thereof. Furthermore, it will be understood that when an element is referred to as being connected or coupled to another element, it may be directly connected or coupled to the other element or intervening elements may be present.

[0109] In addition, when detailed descriptions of related known functions or constitutions are considered to unnecessarily cloud the gist of the present invention in describing the present invention below, the detailed descriptions will not be included.

Stack Structure And Manufacturing Method Thereof

[0110] FIG. 1 is a flowchart for explaining a method for manufacturing a stack structure according to an embodiment of the present invention, and FIGS. 2 and 3 are schematic views for explaining a process of manufacturing a stack structure according to the embodiment of the present invention.

[0111] Referring to FIGS. 1 to 3, a substrate SB may be prepared (S110). According to one embodiment, the substrate SB may be a silicon semiconductor substrate. Alternatively, according to another embodiment, the substrate SB may be a compound semiconductor substrate. Alternatively, according to still another embodiment, the substrate SB may be a glass substrate. Alternatively, according to still another embodiment, the substrate SB may be a plastic substrate. The type of the substrate SB is not limited.

[0112] A channel layer 100 including a two-dimensional semiconductor material may be formed on the substrate SB (S120). According to one embodiment, the two-dimensional semiconductor material may include any one of Bi.sub.2O.sub.2Se, hafnium diselenide (HfSe.sub.2), hafnium disulfide (HfS.sub.2), and zirconium diselenide (ZrSe.sub.2). According to one embodiment, the channel layer 100 may be formed by using various deposition methods such as chemical vapor deposition (CVD) and physics vapor deposition (PVD) using precursors. Alternatively, the channel layer 100 may be formed by transferring a two-dimensional semiconductor material exfoliated from a bulk onto the substrate SB. The method for forming the channel layer 100 is not limited.

[0113] The channel layer 100 may be oxidized to form a dielectric layer 200 including a high-k material (S130). In one embodiment, as the channel layer 100 is oxidized, one region of the channel layer 100 may be converted into the dielectric layer 200 including the high-k material, and the other region of the channel layer 100 may remain as the channel layer 100 including the two-dimensional semiconductor material. That is, when the channel layer 100 is oxidized, the oxidized region in the channel layer 100 is converted into the high-k material formed by oxidizing the two-dimensional semiconductor material, and the non-oxidized region may remain as the two-dimensional semiconductor material. Therefore, the high-k material may be defined as a material formed by oxidizing two-dimensional semiconductor material.

[0114] According to one embodiment, the high-k material may include any one of Bi.sub.2SeO.sub.5, hafnium oxide (HfO.sub.x, x>0), and zirconium oxide (ZrO.sub.x, x>0). More specifically, when the two-dimensional semiconductor material includes Bi.sub.2O.sub.2Se, Bi.sub.2O.sub.2Se may be converted into a Bi.sub.2SeO.sub.5 high-k material as the two-dimensional semiconductor material is oxidized. Alternatively, when the two-dimensional semiconductor material includes hafnium diselenide (HfSe.sub.2) or hafnium disulfide (HfS.sub.2), hafnium diselenide (HfSe.sub.2) or hafnium disulfide (HfS.sub.2) may be converted into a hafnium oxide (HfO.sub.x, x>0) high-k material as the two-dimensional semiconductor material is oxidized. Alternatively, when the two-dimensional semiconductor material includes zirconium diselenide (ZrSe.sub.2), the zirconium diselenide (ZrSe.sub.2) may be converted into a zirconium oxide (ZrO.sub.x, x>0) high-k material as the two-dimensional semiconductor material is oxidized.

[0115] According to one embodiment, the channel layer 100 may be oxidized by any one of oxidation methods such as plasma oxidation, native oxidation, and an oxidation method using ultraviolet (UV) rays. Further, the channel layer 100 may be oxidized in a different manner according to the type of the two-dimensional semiconductor material.

[0116] Specifically, when the two-dimensional semiconductor material includes Bi.sub.2O.sub.2Se, the channel layer 100 may be oxidized by any one of oxidation methods such as plasma oxidation, native oxidation, and the oxidation method using ultraviolet (UV) rays. Further, when the two-dimensional semiconductor material includes Bi.sub.2O.sub.2Se, a crystal structure of the Bi.sub.2SeO.sub.5 high-k material formed by oxidizing Bi.sub.2O.sub.2Se according to the oxidation method of the channel layer 100 may be controlled. For example, when the channel layer 100 including Bi.sub.2O.sub.2Se is oxidized using oxygen (O.sub.2) plasma, an amorphous Bi.sub.2SeO.sub.5 high-k material may be formed. Alternatively, when the channel layer 100 including Bi.sub.2O.sub.2Se is oxidized by native oxidation, a crystalline Bi.sub.2SeO.sub.5 high-k material may be formed. Alternatively, when the channel layer 100 including Bi.sub.2O.sub.2Se is oxidized by the oxidation method using ultraviolet rays (e.g., UV-assisted intercalative oxidation), a single crystalline -Bi.sub.2SeO.sub.5 high-k material may be formed.

[0117] When the two-dimensional semiconductor material includes zirconium diselenide (ZrSe.sub.2), the channel layer 100 may be oxidized by native oxidation to form a zirconium oxide (ZrO.sub.x, x>0) high-k material.

[0118] When the two-dimensional semiconductor material includes hafnium diselenide (HfSe.sub.2) or hafnium disulfide (HfS.sub.2), the channel layer 100 may be oxidized by native oxidation or oxygen (O.sub.2) plasma to form hafnium oxide (HfO.sub.x, x>0).

[0119] As described above, although the high-k material may be formed by using various oxidation methods according to the type of the two-dimensional semiconductor material, except for the case in which hafnium dioxide (HfSe.sub.2) is oxidized by oxygen (O.sub.2) plasma to form hafnium oxide (HfO.sub.2), interface characteristics between the channel layer 100 and the dielectric layer 200 is low so that a subthreshold swing (SS) value is increased, thereby making it difficult to implement a low-power device.

[0120] That is, in the Bi.sub.2SeO.sub.5/Bi.sub.2O.sub.2Se stack structure formed by the oxidation methods using plasma oxidation, the native oxidation, and ultraviolet rays, the ZrO.sub.x/ZrSe.sub.2 stack structure formed by the oxidation method using the native oxidation, the HfO.sub.x/HfSe.sub.2 stack structure formed by the oxidation method using the native oxidation, and the HfO.sub.x/HfS.sub.2 stack structure formed by the oxidation method using the native oxidation and the plasma oxidation, the interface characteristics between the channel layer 100 and t the dielectric layer 200 is low so that the subthreshold swing (SS) value is increased, thereby making it difficult to implement a low-power device.

[0121] On the other hand, the HfO.sub.2/HfSe.sub.2 stack structure formed by the plasma oxidation (e.g., O.sub.2 plasma oxidation) method may have a subthreshold swing (SS) value close to a Boltzmann limit at room temperature because the interface characteristics between the channel layer 100 and the dielectric layer 200 is high, so that a low-power device is easily implemented. Hereinafter, the HfO.sub.2/HfSe.sub.2 stack structure formed by the plasma oxidation (e.g., 02 plasma oxidation) method will be described in more detail.

[0122] FIGS. 4 to 6 are schematic views for explaining a method for manufacturing a HfO.sub.2/HfSe.sub.2 stack structure, FIG. 7 is a schematic view for explaining a manufacturing mechanism of the HfO.sub.2/HfSe.sub.2 stack structure in more detail, FIG. 8 is a schematic view for explaining a HfSe.sub.2 oxidation process at an appropriate oxygen concentration, and FIG. 9 is a schematic view for explaining a HfSe.sub.2 oxidation process at an excessive oxygen concentration.

[0123] Referring to FIGS. 4 to 7, when the oxidation process is performed on the channel layer 100 including hafnium diselenide (HfSe.sub.2) through oxygen plasma (Oz plasma), layer-by-layer oxidation, that is, oxidation for each layer may be performed.

[0124] More specifically, when the oxidation process is performed on the channel layer 100 through oxygen plasma, oxygen atoms O may penetrate into the channel layer 100, in which one oxygen atom O penetrating into the channel layer 100 may replace selenium atoms Se of the hafnium diselenide (HfSe.sub.2) without an additional substitution energy barrier. In addition, the oxygen atom O replacing the selenium atom Se may form a covalent bond with three hafnium atoms (Hf). Accordingly, hafnium oxide (HfO.sub.2) formed by oxidizing hafnium diselenide (HfSe.sub.2) may be formed. That is, a region of the channel layer 100 including hafnium diselenide (HfSe.sub.2) may be converted into the dielectric layer 200 including hafnium oxide (HfO.sub.2). Thereafter, as shown in FIG. 5 and FIG. 7(a), a region of the dielectric layer 200 may be gradually increased by the continuously penetrated oxygen atoms O. That is, a thickness of the dielectric layer 200 may be gradually increased and a thickness of the channel layer 100 may be gradually decreased due to the continuously penetrated oxygen atoms O.

[0125] Meanwhile, as shown in FIGS. 5 and 7(b), the substituted selenium atoms Se generated when the penetrated oxygen atoms O substitute the selenium atoms Se of hafnium diselenide (HfSe.sub.2) may be diffused into an oxygen vacancy V.sub.o in the dielectric layer 200 and then discharged to the outside of the dielectric layer 200 through the oxygen vacancies V.sub.o in the dielectric layer 200. In addition, the substituted selenium atoms Se may form an interface between the channel layer 100 and the dielectric layer 200 before being diffused into the oxygen vacancies in the dielectric layer 200. Accordingly, the channel layer 100 and the dielectric layer 200 may be prevented from being merged by an interface formed by the substituted selenium atoms Se. Therefore, the oxidation for each layer by the continuously penetrated oxygen atoms O may be easily performed.

[0126] However, the formation of the interface by the substituted selenium atom Se may be performed under a condition of an appropriate oxygen concentration, as shown in FIG. 8. That is, when hafnium diselenide (HfSe.sub.2) is oxidized by oxygen (O.sub.2) plasma, the oxidation for each layer may be easily performed only when the appropriate oxygen concentration condition is maintained, thereby manufacturing the HfO.sub.2/HfSe.sub.2 stack structure in which hafnium diselenide (HfSe.sub.2) and hafnium oxide (HfO.sub.2) are clearly distinguished. In contrast, when hafnium diselenide (HfSe.sub.2) is oxidized under an excessive oxygen concentration condition, as shown in FIG. 9, since the interface is not formed by the substituted selenium atoms Se, there may be a problem in that the channel layer 100 and the dielectric layer 200 are merged. That is, when hafnium diselenide (HfSe.sub.2) is oxidized under the excessive oxygen concentration condition, hafnium diselenide (HfSe.sub.2) and hafnium oxide (HfO.sub.2) may not be clearly distinguished from each other, and hafnium diselenide (HfSe.sub.2) and hafnium oxide (HfO.sub.2) may be mixed.

[0127] According to one embodiment, the oxygen concentration condition may be controlled according to power of oxygen (O.sub.2) plasma provided to hafnium diselenide (HfSe.sub.2). More specifically, the power of oxygen (O.sub.2) plasma provided to the hafnium diselenide (HfSe.sub.2) may be controlled to be greater than 7 W and less than 20 W. In contrast, when the power of oxygen (O.sub.2) plasma is controlled to 20 W or greater, hafnium diselenide (HfSe.sub.2) and hafnium oxide (HfO.sub.2) may not be clearly distinguished from each other due to the excessive oxygen concentration, and hafnium diselenide (HfSe.sub.2) and hafnium oxide (HfO.sub.2) may be mixed. In addition, when the power of oxygen (O.sub.2) plasma is controlled to 7 W or less, since no penetration of the minimum amount of oxygen atoms for forming the hafnium oxide (HfO.sub.2) occurs, hafnium diselenide (HfSe.sub.2) is not oxidized, and thus hafnium oxide (HfO.sub.2) may not be formed.

[0128] As a result, the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention is manufactured by oxidizing hafnium diselenide (HfSe.sub.2) using oxygen (O.sub.2) plasma, and since the interface by the substituted selenium atoms Se is formed between the channel layers 100 (HfSe.sub.2) and the dielectric layers 200 (HfO.sub.2) during the oxidation process, the interface characteristics between the channel layer 100 (HfSe.sub.2) and the dielectric layers 200 (HfO.sub.2) may be improved. Accordingly, an electronic device using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment may have the subthreshold swing SS value close to the Boltzmann limit at room temperature, and thus, a low-power device may be easily implemented.

[0129] Hereinabove, the stack structure and the method for manufacturing the same according to the embodiment of the present invention have been described. Hereinafter, various application examples of the stack structure according to the embodiment of the present invention will be described.

Capacitor Using HfO.sub.2/HfSe.sub.2 Stack Structure

[0130] FIG. 10 is a flowchart for explaining a method for manufacturing a capacitor using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention, and FIG. 11 is a schematic view for explaining the capacitor using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0131] Referring to FIGS. 10 and 11, after a substrate SB is prepared (S210), a lower electrode BE may be formed on the substrate SB (S220). According to one embodiment, the substrate SB may be a silicon semiconductor substrate. Alternatively, according to another embodiment, the substrate SB may be a compound semiconductor substrate. Alternatively, according to still another embodiment, the substrate SB may be a glass substrate. Alternatively, according to still another embodiment, the substrate SB may be a plastic substrate. The type of the substrate SB is not limited.

[0132] A channel layer 100 including a two-dimensional semiconductor material may be formed on the lower electrode BE (S230). The two-dimensional semiconductor material may include hafnium diselenide (HfSe.sub.2). According to one embodiment, the channel layer 100 may be formed by dry-transferring hafnium diselenide (HfSe.sub.2) flakes mechanically exfoliated from a bulk crystal using polydimethylsiloxane (PDMS).

[0133] The channel layer 100 may be oxidized to form a dielectric layer 200 including a high-k material (S230). More specifically, the channel layer 100 including hafnium diselenide (HfSe.sub.2) may be oxidized with oxygen (O.sub.2) plasma to convert a partial region of the channel layer 100 into hafnium oxide (HfO.sub.2). That is, a region in which hafnium diselenide (HfSe.sub.2) is oxidized to be converted into hafnium oxide (HfO.sub.2) may be defined as the dielectric layer 200.

[0134] Finally, an upper electrode TE may be formed on the dielectric layer 200 (S250). Accordingly, a MOS capacitor to which the HfO.sub.2/HfSe.sub.2 stack structure is applied may be manufactured.

[0135] In the MOS capacitor according to the embodiment, hafnium diselenide (HfSe.sub.2) included in the channel layer 100 exhibits n-type semiconductor characteristics, and shows a behavior that is significantly unchanged in both a depletion region and an accumulation region according to various frequency ranges (1 kHz to 1 MHZ), so that the MOS capacitor may have a low level of interface trap (interface trap between the channel layer and the dielectric layer). In addition, the MOS capacitor according to the embodiment may have a constant dielectric constant k of 23 in various frequency ranges (1 kHz to 1 MHZ). That is, the MOS capacitor according to the embodiment has stable dielectric characteristics of a high-k constant, and thus may be easily applied to a low power and high frequency electronic apparatus.

Field Effect Transistor Using HfO.sub.2/HfSe.sub.2 Stack Structure

[0136] FIG. 12 is a flowchart for explaining a method for manufacturing a field effect transistor using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention, and FIG. 13 is a schematic view for explaining the field effect transistor using the HfO.sub.2/HfSe.sub.2 stack structure according embodiment of the present invention.

[0137] Referring to FIGS. 12 and 13, a source electrode S and a drain electrode D disposed to be spaced apart from each other may be prepared (S310). Thereafter, a channel layer 100 including a two-dimensional semiconductor material may be formed on the source electrode S and the drain electrode D (S320). More specifically, the channel layer 100 may be formed such that one side thereof makes contact the source electrode S and the other side thereof makes contact with the drain electrode D. Further, the two-dimensional semiconductor material may include hafnium diselenide (HfSe.sub.2). According to one embodiment, the channel layer 100 may be formed by dry-transferring hafnium diselenide (HfSe.sub.2) flakes mechanically exfoliated from a bulk crystal using polydimethylsiloxane (PDMS).

[0138] The channel layer 100 may be oxidized to form a dielectric layer 200 including a high-k material (S330). More specifically, the channel layer 100 including hafnium diselenide (HfSe.sub.2) may be oxidized using oxygen (O.sub.2) plasma to convert a partial region of the channel layer 100 into hafnium oxide (HfO.sub.2). That is, a region in which hafnium diselenide (HfSe.sub.2) is oxidized to be converted into hafnium oxide (HfO.sub.2) may be defined as the dielectric layer 200.

[0139] Finally, a gate electrode GE may be formed on the dielectric layer 200 to cover the entire upper portion of the dielectric layer 200 (S250). Accordingly, a field effect transistor (FET) using the HfO.sub.2/HfSe.sub.2 stack structure may be manufactured.

[0140] The field effect transistor according to the embodiment may have excellent electrical characteristics due to the excellent interface characteristics of the HfO.sub.2/HfSe.sub.2 stack structure. More specifically, the field effect transistor according to the embodiment may have an ideal subthreshold swing (SS) value of 61 mV/dec close to the Boltzmann limit at room temperature, a high on-off ratio of about 10.sup.8, and a low gate leakage current value of 10.sup.6 A/cm.sup.2.

Impact Ionization Super-Tilt Switching Device Using HfO.sub.2/HfSe.sub.2 Stack Structure

[0141] FIG. 14 is a flowchart for explaining a method for manufacturing an impact ionization super-tilt switching device using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention, and FIG. 15 is a schematic view for explaining the impact ionization super-tilt switching device using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0142] Referring to FIGS. 14 and 15, a source electrode S and a drain electrode D disposed to be spaced apart from each other may be prepared (S410). Thereafter, a channel layer 100 including a two-dimensional semiconductor material may be formed on the source electrode S and the drain electrode D (S420). More specifically, the channel layer 100 may be formed such that one side thereof makes contact the source electrode S and the other side thereof makes contact with the drain electrode D. Further, the two-dimensional semiconductor material may include hafnium diselenide (HfSe.sub.2). According to one embodiment, the channel layer 100 may be formed by dry-transferring hafnium diselenide (HfSe.sub.2) flakes mechanically exfoliated from a bulk crystal using polydimethylsiloxane (PDMS).

[0143] The channel layer 100 may be oxidized to form a dielectric layer 200 including a high-k material (S430). More specifically, the channel layer 100 including hafnium diselenide (HfSe.sub.2) may be oxidized using oxygen (Oz) plasma to convert a partial region of the channel layer 100 into hafnium oxide (HfO.sub.2). That is, a region in which hafnium diselenide (HfSe.sub.2) is oxidized to be converted into hafnium oxide (HfO.sub.2) may be defined as the dielectric layer 200.

[0144] Finally, a gate electrode GE may be formed on the dielectric layer 200 such that one region of the upper portion of the dielectric layer 200 is covered and the other region is exposed (S440). Accordingly, an impact ionization super-tilt switching device using the HfO.sub.2/HfSe.sub.2 stack structure may be manufactured. The impact ionization super-tilt switching device may have n-type characteristics as the HfO.sub.2/HfSe.sub.2 stack structure is applied.

[0145] According to one embodiment, the gate electrode GE may be formed to cover one region of the upper portion of the dielectric layer 200, and may be formed to be adjacent to the source electrode S between the source electrode S and the drain electrode D. That is, an upper surface of the dielectric layer 200 may be divided into a first region A.sub.1 in which the gate electrode GE overlaps and a second region A.sub.2 in which the gate electrode GE does not overlap so that the upper surface of the dielectric layer 200 is exposed to the outside.

[0146] According to one embodiment, a voltage for generating an electric field that is greater than a minimum electric field intensity (hereinafter, referred to as a threshold electric field) for generating avalanche multiplication in the second region A.sub.2 may be applied to the drain electrode D.

[0147] In addition, at the same time as a voltage is applied to the drain electrode D, the voltage may be applied to the gate electrode GE, and the voltage may be applied to be gradually increased. Therefore, an avalanche carrier multiplication phenomenon may be generated in the second region A.sub.2. That is, a gate voltage is gradually increased while a strong electric field equal to or greater than a threshold electric field is applied to the first region A.sub.1 through the voltage of the drain electrode D to generate the avalanche carrier amplification phenomenon, thereby implementing a super-tilt switching phenomenon at room temperature.

[0148] When an electric field is applied to the first region A.sub.1, charge carriers are accelerated in the second region A.sub.2. However, a charge carrier velocity is not infinitely increased, but saturates at a constant velocity due to collision with the lattice. However, when a sufficiently high electric field, that is, an electric field larger than a critical electric field, is applied, charge carriers sufficiently accelerated by the electric field collide with the lattice to raise electrons of a valence band to a conduction band, thereby generating a new electron-hole pair. The secondary electron-hole pairs acquire high energy again to continuously generate additional electron-hole pairs, and a density may be significantly accordingly, carrier increased. The avalanche multiplication means that carriers are amplified by the collision ionization, and the critical electric field means an electric field strength having a minimum magnitude at which the avalanche multiplication occurs.

[0149] The impact ionization super-tilt switching device according to the embodiment may have excellent electrical characteristics due to the excellent interface characteristics of the HfO.sub.2/HfSe.sub.2 stack structure. More specifically, the impact ionization super-tilt switching device according to the embodiment may have a very low subthreshold voltage swing (SS) value of 3.43 mV/dec by overcoming a thermionic limit (60 mV/dec) of a CMOS device. Accordingly, a supply voltage may be reduced while maintaining the high on-off ratio, thereby easily improving power consumption and reliability of the device.

[0150] Further, the impact ionization super-tilt switching device according to the embodiment may adjust a gate region through a structure in which the gate electrode GE overlaps only a portion of the channel layer 100 and the dielectric layer 200 having impact ionization characteristics, and may gradually increase the gate voltage while the strong electric field equal to or greater than the threshold electric field is applied to the channel layer 100, thereby increasing a probability of occurrence of the avalanche carrier amplification phenomenon, and as a result, the number of charge carriers generated in the channel layer 100 may be significantly increased, and as a result, a super-tilt switching device having a very low subthreshold swing (SS) value even at room temperature may be implemented.

[0151] In addition, according to the present invention, an inverter device having a high inverter gain and an ideal noise margin based on the super-tilt switching phenomenon may be implemented through a simple series connection circuit configuration with a transistor which may operate complementarily with the super-tilt switching device.

[0152] In addition, according to the present invention, the upper surface of the dielectric layer 200 may include the first region A.sub.1 in which the gate electrode GE overlaps and the second region A.sub.2 not overlapping the gate electrode GE, in which the first region A.sub.1 and the second region A.sub.2 may have a length ratio of 1:0.1 to 0.4. Accordingly, the number of charge carriers generated in the channel layer 100 may be significantly increased by increasing the probability of occurrence of the avalanche carrier amplification phenomenon occurring in the first region A.sub.1, and as a result, a super-tilt switching device having a very low (5 mv/dec or less) subthreshold swing (SS) value even at room temperature and an optimized on/off ratio may be implemented. Alternatively, when the ratio of the length of the second area A.sub.2 to the length of the first area A.sub.1 is less than 0.1, the on/off ratio decreases as an off current increases, and as a result, the SS value may increase, and the probability of occurrence of impact ionization may decrease. On the other hand, when the ratio of the length of the second area A.sub.2 to the length of the first area A.sub.1 exceeds 0.4, there may be a problem that a step-switching phenomenon does not occur.

Architectural Film Using HfO.sub.2/HfSe.sub.2 Stack Structure

[0153] FIG. 16 is a schematic view for explaining an architectural film using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0154] Passive cooling is a building design approach that focuses on heat acquisition control and heat dissipation of a building in order to improve indoor thermal comfort with little or no energy consumption, and is a technology that adjusts temperature in a building by adjusting only a convection direction without a special temperature control device. An architectural film (particularly, a film used for window coating) among technologies related to the passive cooling technology, a film in which silicon carbide (Sic) and hafnium oxide (HfO.sub.2) are alternately and repeatedly stacked (HfO.sub.2/SiC) has been conventionally used, as shown in the upper part of FIG. 16.

[0155] However, hafnium diselenide (HfSe.sub.2) may also be used instead of silicon carbide (Sic), and when hafnium diselenide (HfSe.sub.2) is used, as described above in the present invention, since the HfO.sub.2/HfSe.sub.2 stack structure may be manufactured by a simple method for oxidizing hafnium diselenide (HfSe.sub.2), process convenience may be improved compared to the conventional method, and a large area may also be easily manufactured.

Solar Cell Using HfO.sub.2/HfSe.sub.2 Stack Structure

[0156] FIG. 17 is a schematic view for explaining a solar cell using the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0157] Referring to FIG. 17, the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment may be used as a blocking layer for preventing back reaction between transparent conductive oxide (TCO) of a dye-sensitized solar cell (DSSC) and an electrolyte. When back reaction occurs between the transparent conductive oxide (TCO) and the electrolyte, efficiency of the dye-sensitized solar cell (DSSC) may be significantly reduced. Accordingly, titanium oxide (TiO.sub.2) is used as the blocking layer in the related art. However, when hafnium oxide (HfO.sub.2) having a larger energy band gap than titanium dioxide (TiO.sub.2) is used, electron recombination between the TCO and the electrolyte may be more effectively prevented, and thus, a problem of a decrease in efficiency of the DSSC may be more easily solved.

[0158] Hereinabove, various application examples of the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention have been described. Hereinafter, various modification examples of the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention will be described.

First Modification Example: Crystallization of HfO.SUB.2

[0159] FIG. 18 is a schematic view for explaining a first modification example of the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0160] Referring to FIG. 18, a stack structure in which the channel layer 100 and the dielectric layer 200 are stacked on a substrate SB, that is, a HfO.sub.2/HfSe.sub.2 stack structure, may be formed, and then a dielectric layer 200 may be post-treated to change hafnium oxide (HfO.sub.2) from an amorphous state to a crystalline state. That is, hafnium oxide (HfO.sub.2) formed by oxidizing hafnium diselenide (HfSe.sub.2) has an amorphous state, and may be post-treated to be changed into a crystalline state. According to one embodiment, the amorphous hafnium oxide (HfO.sub.2) may be changed into a crystalline state by performing post-treatment such as thermal annealing, laser exposure, and E-beam exposure.

[0161] Since the crystalline hafnium oxide (HfO.sub.2) may have relatively improved insulation characteristics compared to the amorphous hafnium oxide (HfO.sub.2), the crystalline hafnium oxide (HfO.sub.2) may be easily applied to a place where high insulation characteristics are required using the above-described method.

[0162] In addition, according to one embodiment, the amorphous hafnium oxide (HfO.sub.2) may be changed into the crystalline hafnium oxide (HfO.sub.2), and one region thereof may be changed into the crystalline hafnium oxide (HfO.sub.2), whereas the remaining region thereof may remain as the amorphous hafnium oxide (HfO.sub.2). For example, by post-treating only an upper surface of the amorphous hafnium oxide (HfO.sub.2), an upper region of the dielectric layer 200 may be changed into the crystalline hafnium oxide (HfO.sub.2), whereas a lower region, that is, a region in which the dielectric layer 200 is adjacent to the channel layer 100 may remain as the amorphous hafnium oxide (HfO.sub.2). In this case, even gate leakage current reduction characteristics of the crystalline hafnium oxide (HfO.sub.2) may be exhibited while maintaining excellent interface characteristics between the channel layer 100 and the dielectric layer 200, and thus the structure may be easily applied to various fields.

Second Modification Example Formation of HfZrO.SUB.2 .Through Zr Doping

[0163] FIGS. 19 and 20 are schematic views for explaining a second modification example of the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0164] Referring to FIG. 19, after hafnium diselenide (HfSe.sub.2) and zirconium diselenide (ZrSe.sub.2) are sequentially stacked on a substrate, oxygen (O.sub.2) plasma may be provided to zirconium diselenide (ZrSe.sub.2). In this case, zirconium diselenide (ZrSe.sub.2) is decomposed to generate a zirconium (Zr) atom, and in this case, HfZrO.sub.2 may be formed using the generated zirconium (Zr) atom. More specifically, when oxygen (O.sub.2) plasma is continuously provided to zirconium diselenide (ZrSe.sub.2), the zirconium (Zr) atom decomposed from zirconium diselenide (ZrSe.sub.2) may be bonded to an oxygen (O) atom, and the zirconium-oxygen bond (ZrO) may penetrate into the hafnium diselenide (HfSe.sub.2). Thereafter, the penetrated zirconium-oxygen bond (ZrO) may substitute a selenium (Se) atom of hafnium diselenide (HfSe.sub.2) to form HfZrO.sub.2. Further, the formed HfZrO.sub.2 may be thermally annealed to crystallize HfZrO.sub.2.

[0165] Referring to FIG. 20, After hafnium diselenide (HfSe.sub.2) and zirconium diselenide (ZrSe.sub.2) are sequentially stacked on the substrate, oxygen (O.sub.2) plasma may be continuously provided to zirconium diselenide (ZrSe.sub.2). In this case, the zirconium (Zr) atom decomposed from zirconium diselenide (ZrSe.sub.2) may be bonded to the oxygen (O) atom, and the zirconium-oxygen bond (ZrO) may penetrate into the hafnium diselenide (HfSe.sub.2). Thereafter, the penetrated zirconium-oxygen bond (ZrO) may substitute the selenium (Se) atom of hafnium diselenide (HfSe.sub.2), so that hafnium diselenide (HfSe.sub.2) may be fully converted into HfZrO.sub.2. In addition, the formed HfZrO.sub.2 may be thermally annealed to crystallize the HfZrO.sub.2, and various transition metal dichalcogenides (TMDCs) may be inserted between the HfZrO.sub.2 and the substrate.

Third Modification Example Full Oxidation of HfSe.SUB.2 .to Convert HfSe.SUB.2 .into HfO.SUB.2

[0166] FIG. 21 is a schematic view for explaining a third modification example of the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention.

[0167] Referring to FIG. 21, after the channel layer 100 is formed on the substrate SB, oxygen (O.sub.2) plasma may be continuously provided, thereby converting the entire channel layer 100 into the dielectric layer 200. That is, hafnium diselenide (HfSe.sub.2) may be fully converted into hafnium oxide (HfO.sub.2).

[0168] According to one embodiment, the above-described third modification example may be used as a method for integrating a gate dielectric on various two-dimensional semiconductors. For example, hafnium diselenide (HfSe.sub.2) may be stacked on molybdenum disulfide (MoS.sub.2), and then oxygen (O.sub.2) plasma may be continuously provided to hafnium diselenide (HfSe.sub.2), thereby fully converting the hafnium diselenide (HfSe.sub.2) into hafnium oxide (HfO.sub.2). Accordingly, a structure in which a gate dielectric (HfO.sub.2) is integrated on a two-dimensional semiconductor (MoS.sub.2) may be formed. More specifically, the above-described method may be performed by stacking hafnium diselenide (HfSe.sub.2) on the two-dimensional semiconductor (MoS.sub.2) and using the van der Waals (vdW) gap formed between the two-dimensional semiconductor (MoS.sub.2) and hafnium diselenide (HfSe.sub.2) as a defect free vdW interface.

[0169] Hereinafter, various modification examples of the stack structure according to the embodiment of the present invention have been described. Hereinafter, specific experimental examples and characteristic evaluation results of the HfO.sub.2/HfSe.sub.2 stack structure according to the embodiment of the present invention will be described.

Experimental Example 1: Confirmation of HfO.SUB.2./HfSe.SUB.2 .Stack Structure Characteristics

[0170] Hafnium diselenide (HfSe.sub.2) was formed on a substrate, and then hafnium diselenide (HfSe.sub.2) was subjected to plasma oxidation to convert one region of hafnium diselenide (HfSe.sub.2) into hafnium oxide (HfO.sub.2). In addition, two protection layers having a thickness of 5 nm were formed on hafnium oxide (HfO.sub.2). More specifically, the plasma oxidation of hafnium diselenide (HfSe.sub.2) was performed by a method for providing oxygen (O.sub.2) plasma at a flow rate of 5 sccm and a pressure of 470 mTorr.

[0171] FIG. 22 is a TEM image of HfSe.sub.2 oxidized with oxygen plasma having power of 7 W.

[0172] Referring to FIG. 22, it shows a transmission electron microscopy (TEM) image of HfSe.sub.2 oxidized with oxygen plasma having power of 7 W. As can be seen from FIG. 22, HfSe.sub.2 is not oxidized due to low plasma power.

[0173] FIG. 23 is a TEM image of HfSe.sub.2 oxidized with oxygen plasma having power of 8 W.

[0174] Referring to FIG. 23, it shows a transmission electron microscopy (TEM) image of HfSe.sub.2 oxidized with oxygen plasma having power of 8 W. As can be seen from FIG. 23, one region of HfSe.sub.2 is converted into HfO.sub.2.

[0175] FIG. 24 is a TEM image of HfSe.sub.2 oxidized with oxygen plasma having power of 10 W.

[0176] Referring to FIG. 24, it shows a transmission electron microscopy (TEM) image of HfSe.sub.2 oxidized with oxygen plasma having power of 8 W. As can be seen from FIG. 24, one region of HfSe.sub.2 is converted into HfO.sub.2, and HfSe.sub.2 and HfO.sub.2 are clearly distinguished due to an interface.

[0177] FIG. 25 is a TEM image of HfSe.sub.2 oxidized with oxygen plasma having power of 20 W.

[0178] Referring to FIG. 25, it shows a transmission electron microscopy (TEM) image of HfSe.sub.2 oxidized with oxygen plasma having power of 20 W. As can be seen from FIG. 25, one region of HfSe.sub.2 is converted into HfO.sub.2, but collapse of the interface occurs.

[0179] FIG. 26 is a TEM image of HfSe.sub.2 oxidized with oxygen plasma having power of 30 W.

[0180] Referring to FIG. 26, it shows a transmission electron microscopy (TEM) image of HfSe.sub.2 oxidized with oxygen plasma having power of 20 W. As can be seen from FIG. 26, one region of HfSe.sub.2 is converted into HfO.sub.2, but the collapse of the interface occurs more clearly.

[0181] As a result, as can be seen from FIGS. 22 to 26, when the HfO.sub.2/HfSe.sub.2 stack structure is manufactured, power of the oxygen plasma is necessarily controlled during the plasma oxidation process of HfSe.sub.2. Specifically, it can be seen that plasma power exceeding at least 7 W is required to convert HfSe.sub.2 into HfO.sub.2, and maximum plasma power of less than 20 W is required to prevent the interface between HfSe.sub.2 and HfO.sub.2.

TABLE-US-00001 TABLE 1 Plasma power HfO.sub.2/HfSe.sub.2 state 7 W No HfO.sub.2 is formed 8 W HfO.sub.2 is formed and interface is formed between HfO.sub.2 and HfSe.sub.2 10 W HfO.sub.2 is formed and interface is formed between HfO.sub.2 and HfSe.sub.2 20 W HfO.sub.2 is formed, but interface between HfO.sub.2 and HfSe.sub.2 is collapsed 30 W HfO.sub.2 is formed, but interface between HfO.sub.2 and HfSe.sub.2 is collapsed

[0182] FIG. 27 is a view for explaining an OM image and thickness change profile of HfSe.sub.2 before being oxidized with oxygen plasma.

[0183] Referring to FIG. 27, an optical microscopy (OM) image and a thickness variation profile for HfSe.sub.2 before being oxidized with oxygen plasma (0 min oxidation). As can be seen from FIG. 27, only HfSe.sub.2 is observed before HfSe.sub.2 is oxidized with oxygen plasma.

[0184] FIG. 28 is a view for explaining an OM image and thickness change profile of HfSe.sub.2 oxidized with oxygen plasma for 3 minutes.

[0185] Referring to FIG. 28, an optical microscopy (OM) image and a thickness variation profile for HfSe.sub.2 oxidized with oxygen plasma for 3 minutes (3 min oxidation). As can be seen from FIG. 28, HfSe.sub.2 is partially converted into HfO.sub.2.

[0186] FIG. 29 is a view for explaining an OM image and thickness change profile of HfSe.sub.2 oxidized with oxygen plasma for 5 minutes.

[0187] Referring to FIG. 29, an optical microscopy (OM) image and a thickness variation profile for HfSe.sub.2 oxidized with oxygen plasma for 5 minutes (5 min oxidation). As can be seen from FIG. 29, HfSe.sub.2 is fully converted into HfO.sub.2.

[0188] In addition, considering a molecular mass (336.41/210.5) and density (6.54/9.68 g/cm.sup.3) of HfO.sub.2/HfSe.sub.2, it can be seen from the measurements of FIGS. 27 to 29 that a volume of HfO.sub.2 converted from HfSe.sub.2 is estimated to be 1:2.3.

[0189] FIG. 30 is a view for explaining a Raman analysis result for a plasma oxidation process of HfSe.sub.2.

[0190] Referring to FIG. 30, it shows Raman spectra of HfO.sub.2, HfO.sub.2/HfSe.sub.2, and the remaining HfSe.sub.2 formed as HfSe.sub.2 is subjected to plasma oxidation. As can be seen in FIG. 30, the reduced A.sub.1g Raman peak (red curve) that is seen even after 3 minutes of plasma treatment shows that there is still an unconverted single crystal HfSe.sub.2 layer below HfO.sub.2 converted after the plasma treatment, whereas the A.sub.1g Raman peak that disappeared after 5 minutes of the plasma treatment shows that the HfSe.sub.2 is converted to completely amorphous HfO.sub.2 (blue curve).

[0191] FIG. 31 is a view for explaining a change in a thickness of HfSe.sub.2 according to plasma oxidation and a change in a thickness of HfO.sub.2 converted from HfSe.sub.2.

[0192] Referring to FIG. 31, it shows a change in total thickness of HfSe.sub.2 over a plasma oxidation time (Total thickness) and a change in thickness of HfO.sub.2 converted from HfSe.sub.2 (Converted HfO.sub.2 thickness). As can be seen from FIG. 31, as the plasma oxidation time increases, the thickness of HfSe.sub.2 is reduced, whereas the thickness of HfO.sub.2 changed from the HfSe.sub.2 increases.

[0193] FIG. 32 is a view for explaining a conversion rate of HfSe.sub.2 according to plasma oxidation of HfSe.sub.2.

[0194] Referring to FIG. 32, a change in HfO.sub.2 thickness (nm) of HfSe.sub.2 over a plasma oxidization time (Plasma time, min) of HfO.sub.2 is measured, and a conversion rate of HfO.sub.2, that is, an oxidation rate, is derived from the measurement and shown. More specifically, HfSe.sub.2 was subjected to plasma oxidation through oxygen plasma at a power of 10 W, a flow rate of 5 sccm, and a pressure of 470 mTorr. As can be seen from FIG. 32, the conversion rate of HfO.sub.2, that is, the oxidation rate, is derived as about 2.1 nm/min.

[0195] FIG. 33 is a schematic view for defining various parameters required for calculating the thickness of HfO.sub.2 converted from HfSe.sub.2.

[0196] Since the thicknesses measured in FIGS. 27 to 31 include both the thickness of the unconverted HfSe.sub.2 and the thickness of the converted HfO.sub.2, the thickness of HfO.sub.2 may not be directly determined through an atomic force microscope (AFM). Therefore, an indirect approach was applied to determine the thickness of the converted HfO.sub.2 and as indicated by the black arrow in FIG. 33, the relevant factors were defined as follows.

TABLE-US-00002 TABLE 2 Parameter Description t.sub.0 Thickness of initial HfSe.sub.2 t.sub.1 Thickness of HfO.sub.2 converted from HfSe.sub.2 t.sub.2 Thickness of HfSe.sub.2 converted from HfO.sub.2 t.sub.3 Overall thickness of HfO.sub.2/HfSe.sub.2 stack structure

[0197] A quantitative relationship between the above-described parameters may be expressed as follows. A difference between the thickness to of the initial HfSe.sub.2 and the total thickness ty of the HfO.sub.2/HfSe.sub.2 stack structure may be the same as a difference between the thickness t.sub.2 of HfSe.sub.2 converted into HfO.sub.2 and the thickness t.sub.1 of HfO.sub.2 converted from HfSe.sub.2, and may be summarized as shown in the following <Equation 1>.

[00001]$\begin{array}{cc}{t}_0-t_3=t_2-t_1& .Math.\mathrm{Equation}1.Math.\end{array}$

[0198] In addition, as described above, since the thickness t2 of HfSe.sub.2 converted into HfO.sub.2 is 2.3 times larger than the thickness t1 of HfO.sub.2 converted from HfSe.sub.2, it may be summarized as shown in the following <Equation 2>.

[00002]$\begin{array}{cc}{t}_2=1.8t_1& .Math.\mathrm{Equation}2.Math.\end{array}$

[0199] The following <Equation 3> is derived in consideration of <Equation 1> and <Equation 2> described above, and since the thickness to of the initial HfSe.sub.2 and the total thickness t3 of the HfO.sub.2/HfSe.sub.2 stack structure may be confirmed using the AFM, the thickness t1 of HfO.sub.2 converted from HfSe.sub.2 may be derived through <Equation 3>. In addition, as shown in FIG. 32, an oxidation rate of 2.1 nm/min was derived from the thickness t1 of HfO.sub.2 converted from HfSe.sub.2, and a constant oxidation rate was also confirmed from various HfSe.sub.2 flakes. Accordingly, the high controllability of the plasma oxidation process may be confirmed.

[00003]$\begin{array}{cc}{t}_0-t_3=1.8t_1-t_1=0.8t_1& .Math.\mathrm{Equation}3.Math.\end{array}$

[0200] FIG. 34 is a view for explaining an XPS analysis result of the HfO.sub.2/HfSe.sub.2 stack structure.

[0201] Referring to FIG. 34, it shows an X-ray photoelectron spectroscopy (XPS) depth profile that is analyzed by reducing a thickness by 2.5 nm through sputtering at a speed of 0.5 nm/min after the HfO.sub.2/HfSe.sub.2 stack structure is manufactured. As can be seen from FIG. 34, a clear Se 3d peak and a disappearing O 1s peak (HfO) may be confirmed when the thickness is reduced by 10 nm. Accordingly, the thickness is reduced through the above-described thickness control conditions, and the accuracy of the oxidation rate may be confirmed once again.

[0202] FIG. 35 is a view showing a STEM image and an FFT pattern for the HfO.sub.2/HfSe.sub.2 stack structure.

[0203] Referring to FIG. 35, a scanning transmission electron microscopy (STEM) image for the HfO.sub.2/HfSe.sub.2 stack structure is shown on the right side, and a fast Fourier transform (FFT) pattern for each of HfO.sub.2 and HfSe.sub.2 of the HfO.sub.2/HfSe.sub.2 stack structures is shown on the left side.

[0204] As can be seen from the STEM image of FIG. 35, a clear interface in which no visible defect is shown even in a wide range may be confirmed. In addition, as can be seen from the FFT pattern of FIG. 35, an amorphous structure of HfO.sub.2 and the crystal structure of HfSe.sub.2 may be confirmed. More specifically, it can be seen that an interplanar distance of the unconverted HfSe.sub.2 of (001) is estimated to be about 0.614 nm, and accordingly, the unconverted HfSe.sub.2 maintains the original crystal structure.

[0205] FIG. 36 is a view showing a STEM image and an EDS mapping result for the HfO.sub.2/HfSe.sub.2 stack structure.

[0206] Referring to FIG. 36, a scanning transmission electron microscopy (STEM) image of the HfO.sub.2/HfSe.sub.2 stack structure is shown on the left side, and an energy dispersive spectrometer mapping (EDS) result is shown on the right side. As can be seen from the EDS mapping result of FIG. 36, hafnium (Hf) is confirmed in both HfO.sub.2 and HfSe.sub.2, selenium (Se) is confirmed only in HfSe.sub.2, and oxygen (O) is confirmed only in HfO.sub.2 and the substrate.

[0207] FIG. 37 is a view showing a high-resolution STEM image for the HfO.sub.2/HfSe.sub.2 stack structure.

[0208] As can be seen from FIG. 37, an atomically clean interface between HfO.sub.2 and HfSe.sub.2 may be confirmed again, and thus the merging of unconverted HfSe.sub.2 and HfO.sub.2 converted from HfSe.sub.2 is limited due to the formation of HfO.sub.2. In addition, it can be seen that due to the limitation, the process of forming the HfO.sub.2 is performed by layer-by-layer oxidation.

[0209] FIG. 38 is a view for explaining an XPS analysis result for each of HfO.sub.2 and HfSe.sub.2 in the HfO.sub.2/HfSe.sub.2 stack structure.

[0210] Referring to FIG. 38, it shows an X-ray photoelectron spectroscopy (XPS) analysis result for each of HfO.sub.2 and HfSe.sub.2 in the HfO.sub.2/HfSe.sub.2 stack structure. As shown in FIG. 38, a peak of Hf 4f at 16.01 eV and a peak of O 1s at 532.4 eV show the same results as those of a general HfO.sub.2 dielectric.

Experimental Example 2: Confirmation of Characteristics of MOS Capacitor to Which HfO.SUB.2./HfSe.SUB.2 .Stack Structure Is Applied

[0211] After a lower electrode having a thickness of 10 nm is formed on a substrate, hafnium diselenide (HfSe.sub.2) mechanically exfoliated from a bulk crystal was dry transferred using PDMS. Thereafter, hafnium diselenide (HfSe.sub.2) was subjected to plasma oxidation to convert one region of hafnium diselenide (HfSe.sub.2) into hafnium oxide (HfO.sub.2), and an upper electrode having a thickness of 30 nm was formed on hafnium oxide (HfO.sub.2) to manufacture a MOS capacitor to which the HfO.sub.2/HfSe.sub.2 stack structure was applied. More specifically, hafnium diselenide (HfSe.sub.2) was formed to have a thickness of 15 nm, and hafnium oxide (HfO.sub.2) was formed to have a thickness of 10 nm.

[0212] FIG. 39 is a view showing capacitance-voltage characteristics and a schematic view of a MOS capacitor according to Experimental Example 2.

[0213] Referring to FIG. 39, a capacitance (nF/cm.sup.2) according to a gate voltage VG (V) of the MOS capacitor is measured and shown. As shown in FIG. 39, the capacitance accumulated as the gate voltage increases shows that HfSe.sub.2 is a typical n-type semiconductor. In addition, it can be seen that there is a low level of interface trap through the unchanging behavior in both the depletion region and the accumulation region according to the frequency (1 kHz to 1 MHZ).

[0214] FIG. 40 is view showing conductance-voltage characteristics of the MOS capacitor according to Experimental Example 2.

[0215] Referring to FIG. 40, a conductance G.sub.P/W (nF/cm.sup.2) according to the gate voltage V.sub.G (V) of the MOS capacitor is measured and shown. As can be seen from FIG. 40, there is a substantially constant change in various frequencies (1 kHz to 1 MHZ).

[0216] FIG. 41 is a view for explaining a result of extracting an interface trap density of the MOS capacitor according to Experimental Example 2 by using conductance measured through FIG. 40.

[0217] Referring to FIG. 41, it can be confirmed that a conduction method using the conductivity of FIG. 40 is used to evaluate an interface charge trap density D.sub.it that determines a performance of the HfO.sub.2/HfSe.sub.2 stack structure, and as can be seen from FIG. 41, a very low interface charge trap density D.sub.it (5.710.sup.10 cm.sup.2 eV.sup.1) is obtained. More specifically, the interface charge trap density D.sub.it was derived through the following <Equation 4>, and Samples 1 to 3 (Sample #1, Sample #2, and Sample #3) shown in FIG. 41 represent MOS capacitors manufactured by the same process, respectively.

[00004]$\begin{array}{cc}{D}_{\mathrm{it}}=\frac{2.5}{Aq}{\left(\frac{G_p}{}\right)}_{\mathrm{peak}}& .Math.\mathrm{Equation}4.Math.\end{array}$

[0218] (D.sub.it: Interface charge trap density, (Gp/).sub.peak: Maximum value of normalized conductance peak, q: Basic charge, A: Area of MOS capacitor)

[0219] FIG. 42 is a view for explaining an equivalent oxide thickness and a dielectric constant of the MOS capacitor according to Experimental Example 2.

[0220] Referring to FIG. 42, it shows an equivalent oxide thickness (EOT) and a dielectric constant (k) according to a frequency calculated from a conductance-voltage curve of the MOS capacitor. As can be seen from FIG. 42, the MOS capacitor shows a constant dielectric constant (k) of 23 in all frequency ranges, and it can be confirmed that HfO.sub.2 chemically converted through the oxidation process is a dielectric having a stable high dielectric constant for low-power and high-frequency electronic apparatuses. In addition, the equivalent oxide thickness (EOT, 1.6 nm) was derived from the above-described dielectric constant (k) value.

Experimental Example 3: Confirmation of Characteristics of Field Effect Transistor to Which HfO.SUB.2./HfSe.SUB.2 .Stack Structure Is Applied

[0221] Hafnium diselenide (HfSe.sub.2) mechanically exfoliated from the bulk crystal was dry-transferred onto the source electrode and the drain electrode using PDMS. Thereafter, hafnium diselenide (HfSe.sub.2) was subjected to plasma oxidation to convert one region of hafnium diselenide (HfSe.sub.2) into hafnium oxide (HfO.sub.2), and a gate electrode having a thickness of 50 nm was formed on hafnium oxide (HfO.sub.2) to manufacture a field effect transistor (FET) to which the HfO.sub.2/HfSe.sub.2 stack structure was applied. More specifically, the gate electrode was formed to cover the entire upper surface of hafnium oxide (HfO.sub.2).

[0222] FIG. 43 is a schematic view of a field effect transistor according to Experimental Example 3.

[0223] Referring to FIG. 43, it shows the field effect transistor according to Experimental Example 3 to which the HfO.sub.2/HfSe.sub.2 stack structure is applied. As shown in FIG. 43, HfSe.sub.2 is formed such that one side thereof makes contact with the source electrode (Source) and the other side thereof makes contact with the drain electrode (Drain), and the gate electrode is formed to cover the entire upper surface of HfO.sub.2.

[0224] FIG. 44 is a view showing an ID-VG curve of the field effect transistor according to Experimental Example 3.

[0225] Referring to FIG. 44, I.sub.DS (A) according to Vas (V) of the field effect transistor according to Experimental Example 3 is measured and shown. As shown in FIG. 44, the field effect transistor has an ideal subthreshold swing (SS) value of 61 mV/dec close to the Boltzmann limit at room temperature, a high on-off ratio I.sub.on/off (10.sup.8) and a low gate leakage current value of 10.sup.6 A/cm.sup.2. Accordingly, it can be seen that the HfO.sub.2/HfSe.sub.2 stack structure of the field effect transistor has excellent interface characteristics.

[0226] FIG. 45 is a view showing an ID-VG curve according to a gate voltage sweep of the field effect transistor according to Experimental Example 3.

[0227] Referring to FIG. 45, it shows hysteresis observed during a forward/reverse sweep. As can be seen in FIG. 45, the field effect transistor exhibits a small hysteresis of about 11 mV during a gate voltage sweep. Accordingly, it can be seen that the HfO.sub.2/HfSe.sub.2 stack structure of the field effect transistor includes a small trap concentration at the interface and inside the HfO.sub.2.

[0228] FIG. 46 is a view showing an ID-VG curve according to a temperature of the field effect transistor according to Experimental Example 3.

[0229] Referring to FIG. 46, it shows a change in a subthreshold swing (SS) value according to a temperature (100 K to 300 K) of the field effect transistor according to Experimental Example 3. As can be seen from FIG. 46, as the temperature decreases from 300 K to 100 K, the subthreshold swing (SS) value also decreases from 61 mV/dec to 26 mV/dec.

[0230] FIG. 47 is a view showing a subthreshold swing value according to a temperature of the field effect transistor according to Experimental Example 3.

[0231] Referring to FIG. 47, it shows a change in the subthreshold swing (SS) value (mV/dec) as the temperature of the field effect transistor is changed from 50 K to 300 K. As can be seen from FIG. 47, as the temperature increases, the subthreshold swing also increases, which is value substantially identical to experimental data.

[0232] FIG. 48 is a view for explaining a simulation result of RC Delay characteristics according to an interface charge trap concentration of the field effect transistor according to Experimental Example 3.

[0233] Referring to FIG. 48, it shows a simulation result of RC Delay characteristics according to HfO.sub.2/HfSe.sub.2 interface charge trap density D.sub.it of the field effect transistor according to Experimental Example 3. As can be seen from FIG. 48, the significance of the low interface charge trap concentration D.sub.it can be seen through a simulation evaluation of RC Delay that may appear in a circuit according to the increase in the interface charge trap concentration D.sub.it.

[0234] FIG. 49 is a view showing electrical characteristics of the field effect transistor according to Experimental Example 3 in which a thickness ratio of HfO.sub.2:HfSe.sub.2 is 1:1.

[0235] Referring to FIG. 49, a subthreshold swing (SS) value, an operation current value (On current), and a threshold voltage V.sub.TH of the field effect transistor according to Experimental Example 3 in which the thickness ratio of HfO.sub.2:HfSe.sub.2 is 1:1 are measured and shown. More specifically, each of the thickness of HfO.sub.2 and the thickness of HfSe.sub.2 is 10 nm. As can be seen from FIG. 49, the subthreshold swing (SS) value is measured to 61.5 mV/dec, the operating current value (On current) was measured to be about 10.sup.5 A, and the threshold voltage value V.sub.TH was measured to be about 0.75 V.

[0236] FIG. 50 is a view showing electrical characteristics of the field effect transistor according to Experimental Example 3 in which a thickness ratio of HfO.sub.2:HfSe.sub.2 is 1:2.

[0237] Referring to FIG. 50, a subthreshold swing (SS) value, an operation current value (On current), and a threshold voltage V.sub.TH of the field effect transistor according to Experimental Example 3 in which the thickness ratio of HfO.sub.2:HfSe.sub.2 is 1:2 are measured and shown. More specifically, the thickness of HfO.sub.2 and the thickness of HfSe.sub.2 are 10 nm and 20 nm, respectively.

[0238] As can be seen from FIG. 50, the subthreshold swing (SS) value is measured to be about 80.7 mV/dec, the operating current value (On current) was measured to be about 10.sup.7 A, and the threshold voltage value V.sub.TH was measured to be about 1.1 V.

[0239] FIG. 51 is a view showing electrical characteristics of the field effect transistor according to Experimental Example 3 in which a thickness ratio of HfO.sub.2:HfSe.sub.2 is 1:3.

[0240] Referring to FIG. 51, a subthreshold swing (SS) value, an operation current value (On current), and a threshold voltage V.sub.TH of the field effect transistor according to Experimental Example 3 in which the thickness ratio of HfO.sub.2:HfSe.sub.2 is 1:3 are measured and shown. More specifically, the thickness of HfO.sub.2 and the thickness of HfSe.sub.2 are 10 nm and 30 nm, respectively.

[0241] As can be seen from FIG. 51, the subthreshold swing (SS) value is measured to be about 103.2 mV/dec, the operating current value (On current) was measured to be about 10.sup.8 A, and the threshold voltage value V.sub.TH was measured to be about 1.6 V.

TABLE-US-00003 TABLE 3 Classification SS On current V.sub.TH Thickness ratio ~61.5 mV/dec ~10.sup.5 A ~0.75 V of HfO.sub.2:HfSe.sub.2 1:1 Thickness ratio ~80.7 mV/dec ~10.sup.7 A ~1.1 V of HfO.sub.2:HfSe.sub.2 1:2 Thickness ratio ~103.2 mV/dec ~10.sup.8 A ~1.6 V of HfO.sub.2:HfSe.sub.2 1:3

[0242] As a result, as can be seen from FIGS. 49 to 51, when the thickness of HfSe.sub.2 is increased compared to the thickness of HfO.sub.2, the subthreshold swing (SS) value increases, and the operation current value (On current) and the threshold voltage value V.sub.TH decreases, thereby deteriorating electrical characteristics. In addition, electrical characteristics were measured even when the ratio of the thickness of the HfSe.sub.2 to the thickness of the HfO.sub.2 was reduced, but when the ratio of the thickness of the HfSe.sub.2 to the thickness of the HfO.sub.2 was reduced to less than 1, it was confirmed that there was no substantial change compared to the case where the ratio of the thickness of the HfSe.sub.2 to the thickness of the HfO.sub.2 was 1. Accordingly, it can be seen that, when the field effect transistor using the HfO.sub.2/HfSe.sub.2 stack structure is manufactured, the ratio of the thickness of the HfSe.sub.2 to the thickness of the HfO.sub.2 is necessarily controlled to be 1 or less.

[0243] FIG. 52 is a view for explaining a result of measuring a subthreshold swing value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 10 W is applied.

[0244] Referring to FIG. 52, a subthreshold swing value SS was derived by measuring I.sub.DS (A) according to Vas (V) for the field effect transistor according to Experimental Example 3 to which the HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 10 W was applied. As can be seen from FIG. 52, a subthreshold swing (SS) value (65 mV/dec) is obtained when the power of 10 W is applied.

[0245] FIG. 53 is a view for explaining a result of measuring a subthreshold swing value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 15 W is applied.

[0246] Referring to FIG. 53, a subthreshold swing value SS was derived by measuring I.sub.DS (A) according to V.sub.GS (V) for the field effect transistor according to Experimental Example 3 to which the HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 15 W was applied. As can be seen from FIG. 53, a subthreshold swing (SS) value of equal to or less than 98 mV/dec is obtained when the power of 15 W is applied.

[0247] FIG. 54 is a view for explaining a result of measuring a subthreshold swing value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 20 W is applied.

[0248] Referring to FIG. 54, a subthreshold swing value SS was derived by measuring I.sub.DS (A) according to Vas (V) for the field effect transistor according to Experimental Example 3 to which the HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 20 W was applied. As can be seen from FIG. 54, a subthreshold swing (SS) value of equal to or less than 130 mV/dec is obtained when the power of 20 W is applied.

[0249] FIG. 55 is a view for explaining a result of measuring a subthreshold swing value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 25 W is applied.

[0250] Referring to FIG. 55, a subthreshold swing value SS was derived by measuring I.sub.DS (A) according to V.sub.GS (V) for the field effect transistor according to Experimental Example 3 to which the HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 25 W was applied. As can be seen from FIG. 55, a subthreshold swing (SS) value of equal to or less than 192 mV/dec is obtained when the power of 25 W is applied.

[0251] FIG. 56 is a view for explaining a result of measuring a subthreshold swing value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 30 W is applied.

[0252] Referring to FIG. 56, a subthreshold swing value SS was derived by measuring I.sub.DS (A) according to Vas (V) for the field effect transistor according to Experimental Example 3 to which the HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having power of 30 W was applied. As can be seen from FIG. 56, a subthreshold swing (SS) value (250 mV/dec) is obtained when the power of 30 W is applied.

TABLE-US-00004 TABLE 4 Subthreshold swing (SS) Oxygen plasma power value 10 W ~65 mV/dec 15 W ~98 mV/dec 20 W ~130 mV/dec 25 W ~192 mV/dec 30 W ~250 mV/dec

[0253] As can be seen from FIGS. 52 to 56, as the oxygen plasma power increases from 10 W to 30 W, the subthreshold swing value increases from about 65 mV/dec to about 250 mV/dec. In addition, an equation capable of calculating the subthreshold swing (SS) value according to oxygen plasma power (W) is derived based on the results measured in FIGS. 52 to 56, and the derived equation is summarized through the following <Equation 5>.

[00005]$\begin{array}{cc}y=y_0+A1\exp \left(-\frac{x}{t_1}\right)& .Math.\mathrm{Equation}5.Math.\end{array}$

[0254] (x: Oxygen plasma power (based on W, only the numbers other than W is applied), y: Subthreshold swing value, y.sub.0: 25.79881, A1: 50.00735, t.sub.1: 16.5733)

[0255] As described above, since the field effect transistor to which the HfO.sub.2/HfSe.sub.2 stack structure is applied may derive the subthreshold swing value through only oxygen plasma power for oxidation of HfSe.sub.2, the field effect transistor may be easily applied to various fields through prediction of the subthreshold swing value.

[0256] FIG. 57 is a view for explaining a result of measuring a leakage current value of the field effect transistor according to Experimental Example 3 to which a HfO.sub.2/HfSe.sub.2 stack structure oxidized with oxygen plasma having mutually different power is applied.

[0257] Referring to FIG. 57, leakage current values (Gate leakage current density, A/cm.sup.2) according to Vas (V) are measured and shown for the field effect transistor according to Experimental Example 3 to which the HfO.sub.2/HfSe.sub.2 stack structure oxidized with the oxygen plasma having different powers (10 W, 15 W, 20 W, 25 W, and 30 W) is applied. As can be seen from FIG. 57, as the oxygen plasma power is increased from 10 W to 30 W, the leakage current value is also increased.

Experimental Example 4: Confirmation of Characteristics of Impact Ionization Super-Tilt Switching Device to Which HfO.SUB.2./HfSe.SUB.2 .Stack Structure Is Applied

[0258] Hafnium diselenide (HfSe.sub.2) mechanically exfoliated from the bulk crystal was dry-transferred onto the source electrode and the drain electrode using PDMS. Thereafter, hafnium diselenide (HfSe.sub.2) was subjected to plasma oxidation to convert one region of hafnium diselenide (HfSe.sub.2) into hafnium oxide (HfO.sub.2), and a gate electrode having a thickness of 50 nm was formed on hafnium oxide (HfO.sub.2) to manufacture a field effect transistor (FET) to which the HfO.sub.2/HfSe.sub.2 stack structure was applied. More specifically, the gate electrode was formed to cover a portion of an upper surface of hafnium oxide (HfO.sub.2) and expose the remaining part thereof to the outside.

[0259] FIG. 58 is a schematic view of an impact ionization super-tilt switching device according to Experimental Example 4.

[0260] Referring to FIG. 58, it shows the impact ionization super-tilt switching device according to Experimental Example 4 to which the HfO.sub.2/HfSe.sub.2 stack structure is applied. In addition, it shows a band structure diagram according to the gate voltage and drain voltage and an illustration representing an impact ionization phenomenon.

[0261] As can be seen from FIG. 58, HfSe.sub.2 is formed such that one side thereof makes contact with the source electrode (Source) and the other side thereof makes contact with the drain electrode (Drain), in which HfSe.sub.2 is divided into a region L.sub.gated in which the gate electrode overlaps HfO.sub.2 and a region L.sub.ungated in which the gate electrode does not overlap HfO.sub.2 and an upper surface of HfO.sub.2 is exposed to the outside.

[0262] In addition, it can be confirmed that when a sufficiently high drain voltage V.sub.BR and a gate voltage are applied, an impact ionization phenomenon occurs in the region L.sub.ungated in which the gate electrode does not overlap HfO.sub.2.

[0263] FIG. 59 is a view showing an ID-VG curve of the impact ionization super-tilt switching device according to Experimental Example 4.

[0264] Referring to FIG. 59, it shows transmission characteristics showing a rapid increase in current due to the impact ionization phenomenon occurring in the impact ionization super-tilt switching device according to Experimental Example 4. Further, a portion inserted in FIG. 59 shows a portion where super-tilt switching occurs in an enlarged manner. As can be seen from FIG. 59, the impact ionization super-tilt switching device according to Experimental Example 4 has a very low subthreshold swing (SS) value of 3.43 mV/dec by overcoming a thermionic limit (60 mV/dec) of the CMOS device.

[0265] FIG. 60 is a view showing an ID-VD curve of the impact ionization super-tilt switching device according to Experimental Example 4.

[0266] Referring to FIG. 60, it shows output characteristics showing a rapid increase in current due to the impact ionization phenomenon occurring in the impact ionization super-tilt switching device according to Experimental Example 4.

[0267] FIG. 61 is a view showing electron-hole pairs generated in a gate non-overlapping region of an impact ionization super-tilt switching device according to Experimental Example 4. Referring to FIG. 61, it shows a simulation result of an impact ionization rate and a generated electron-hole density in a region (ungated region) in which the gate electrode of the super gradient switching device according to Experimental Example 4 does not overlap HfO.sub.2. As can be seen from FIG. 61, a sufficient number of electron-hole pairs are generated by impact ionization in the region (ungated region) in which the gate electrode does not overlap HfO.sub.2.

[0268] FIG. 62 is a view showing a threshold voltage according to a change in a thickness of HfO.sub.2 and a length of the gate non-overlapping region of the impact ionization super-tilt switching device according to Experimental Example 4.

[0269] Referring to FIG. 62, it shows a change in a threshold voltage V.sub.BR (V) through the adjustment of the HfO.sub.2 thickness (nm) of the impact ionization super-tilt switching device according to Experimental Example 4 and a length of the region L.sub.ungated (nm) in which the gate electrode does not overlap HfO.sub.2. As can be seen from FIG. 62, the super-tilt switching may be implemented under a lower driving voltage. FIG. 63 is a view showing channel currents according to various drain voltages and gate voltages of the impact ionization super-tilt switching device according to Experimental Example 4.

[0270] Referring to FIG. 63, it is possible to confirm a correlated precondition of the gate voltage and the drain voltage the super-tilt switching in the impact ionization super-tilt switching device according to Experimental Example 4.

[0271] FIG. 64 is a view for explaining a change in electrical characteristics according to the change in the length of the gate non-overlapping region of the impact ionization super-tilt switching device according to Experimental Example 4.

[0272] Referring to FIG. 64, it shows simulation results for a threshold voltage V.sub.TH, a threshold voltage V.sub.BR, and a on-off ratio according to the length L.sub.ungated (nm) of the region in which the gate electrode and HfO.sub.2 of the impact ionization super-tilt switching device according to Exemplary Embodiment 4 do not overlap.

[0273] As can be seen from FIG. 64, when the length L.sub.ungated (nm) of the region in which the gate electrode does not overlap HfO.sub.2 is reduced, the threshold voltage V.sub.TH and the threshold voltage V.sub.BR may be additionally reduced. Accordingly, it can be seen that power consumption and device reliability may be improved by reducing the supply voltage while maintaining a high on-off ratio.

Experimental Example 5: Confirmation of Characteristics of Transistor Integrated with Gate Dielectric on MoS.SUB.2 .Two-Dimensional Semiconductor

[0274] FIG. 65 is a schematic view for explaining a process of manufacturing a transistor according to Experimental Example 5.

[0275] Referring to FIG. 65, MoS.sub.2 was formed on a substrate as a two-dimensional semiconductor, and a source electrode S and a drain electrode D were formed on one side and the other side of the MoS.sub.2, respectively. Thereafter, HfSe.sub.2 was formed on MoS.sub.2, and oxygen plasma was continuously provided to the HfSe.sub.2 to fully convert HfSe.sub.2 into HfO.sub.2. Finally, a gate electrode was formed on HfO.sub.2 to manufacture the transistor according to Experimental Example 5.

[0276] FIG. 66 is a view for explaining MoS.sub.2 semiconductor characteristics of the transistor according to Experimental Example 5.

[0277] Referring to FIG. 66, semiconductor characteristics of MoS.sub.2 were confirmed by measuring I.sub.DS (A) according to V.sub.BG/TG (V) of the transistor according to Experimental Example 5. As can be seen from FIG. 66, MoS.sub.2 has n-type semiconductor characteristics. In addition, it can be confirmed that the transistor according to Experimental Example 5 exhibits small hysteresis.

[0278] FIG. 67 is a view for explaining a subthreshold swing value of the transistor according to Experimental Example 5.

[0279] Referring to FIG. 67, a subthreshold swing (SS) value was derived by measuring I.sub.DS (A) according to V.sub.TG (V) of the transistor according to Experimental Example 5. As can be seen from FIG. 67, the transistor according to Experimental Example 5 has a low subthreshold swing value (60.5 mV/dec).

[0280] That is, as can be seen from FIGS. 66 and 67, the transistor according to Experimental Example 5 has a very low subthreshold swing value and a small hysteresis, and thus, it can be seen that the transistor has excellent interface characteristics between MoS.sub.2 and HfO.sub.2, and it can be predicted that the interface characteristics are caused by a high-quality van der Waals (vdW) interface.

Experimental Example 6: Confirmation of Characteristics of Transistor Integrated with Gate Dielectric on WSe.SUB.2 .Two-Dimensional Semiconductor

[0281] WSe.sub.2 was formed on a substrate as a two-dimensional semiconductor, and a source electrode S and a drain electrode D were formed on one side and the other side of the WSe.sub.2, respectively. Thereafter, HfSe.sub.2 was formed on WSe.sub.2, and oxygen plasma was continuously provided to the HfSe.sub.2 to fully convert HfSe.sub.2 into HfO.sub.2. Finally, a gate electrode was formed on HfO.sub.2 to manufacture the transistor according to Experimental Example 6.

[0282] FIG. 68 is a view for explaining Wse.sub.2 semiconductor characteristics of a transistor according to Experimental Example 6.

[0283] Referring to FIG. 68, semiconductor characteristics of WSe.sub.2 were confirmed by measuring I.sub.DS (A) according to V.sub.BG/TG (V) of the transistor according to Experimental Example 6. As can be seen from FIG. 68, WSe.sub.2 has p-type semiconductor characteristics. In addition, it can be confirmed that the transistor according to Experimental Example 6 exhibits small hysteresis.

[0284] FIG. 69 is a view for explaining a subthreshold swing value of the transistor according to Experimental Example 6.

[0285] Referring to FIG. 69, a subthreshold swing (SS) value was derived by measuring I.sub.DS (A) according to V.sub.TG (V) of the transistor according to Experimental Example 6. As can be seen from FIG. 69, the transistor according to Experimental Example 6 has a low subthreshold swing value (61.3 mV/dec).

[0286] That is, as can be seen from FIGS. 68 and 69, the transistor according to Experimental Example 6 has a very low subthreshold swing value and a small hysteresis, and thus, it can be seen that the transistor has excellent interface characteristics between WSe.sub.2 and HfO.sub.2, and it can be predicted that the interface characteristics are caused by a high-quality van der Waals (vdW) interface.

[0287] While the present invention has been described in connection with the embodiments, it is not to be limited thereto but will be defined by the appended claims. In addition, it is to be understood that those skilled in the art can substitute, change or modify the embodiments in various forms without departing from the scope and spirit of the present invention.