Methods for providing a pulse-width modulated power signal, node and system

Abstract

The invention relates to methods for providing a pulse-width modulated power signal in which control signals are used to define phase states and duration. The invention further relates to a corresponding node and to a corresponding system.

Claims

1. A method for providing a pulse-width modulated power signal with one or more phases at a node having a timer, the method comprising the following steps: receiving, from a central unit, a control signal, the control signal comprising a state for each of the phases and a time stamp, applying the control signal such that each phase is controlled according to the phase's state, until the timer reaches the time stamp, and when the timer reaches the time stamp, applying a further control signal received after the control signal.

2. The method according to claim 1, wherein the step of applying is repeated consecutively with consecutively received control signals.

3. The method according to claim 1, wherein three phases are controlled by the node.

4. The method according to claim 1, wherein the timer is driven by a clock of the node.

5. The method according to claim 1, wherein the timer is synchronized by receiving a timer synchronization signal from another node and putting the timer to a value being determined by the timer synchronization signal and a delay time.

6. The method according to claim 1, wherein the time stamp is given as an absolute value, or as a duration.

7. The method according to claim 1, wherein the phases are controlled using respective Insulated Gate Bipolar Transistors or Silicon Carbide MOSFETs of the node.

8. A method for providing a pulse-width modulated power signal using a plurality of nodes and the central unit, wherein each node performs a method according to claim 1, wherein the central unit sends control signals according to a required pulse-width modulation scheme to the nodes, and wherein corresponding phases of the nodes are electrically coupled in parallel.

9. The method according to claim 8, further comprising a timer synchronization, the timer synchronization comprising the following steps: sending, from at least one first node to at least one second node, a synchronization signal, the synchronization signal comprising a current timer value of the first node, and receiving, at least at the second node, the synchronization signal, and setting the timer of the second node to a value calculated as the current timer value comprised in the synchronization signal plus a delay value.

10. The method according to claim 9, wherein the timer synchronization is performed in specified time intervals during operation.

11. The method according to claim 10, wherein the time interval is at least 10 μs, at least 20 μs, at least 100 μs, or at least 500 μs; and/or at most 100 μs, at most 500 μs, or at most 1 ms; or 50 μs.

12. The method according to claim 9, further comprising a delay value determination, the delay value determination comprising the following steps: sending, from at least one first node to at least one second node, a first determination signal, receiving, at least at the second node, the first determination signal, and immediately after receiving the first determination signal sending, from at least the second node, a second determination signal back to at least the first node, and calculating the delay value based on a round-trip time of the determination signals.

13. The method according to claim 12, wherein the delay value determination is performed with startup and/or during run-time of the nodes and the central unit.

14. The method according claim 12, wherein the delay value is calculated by calculating a sum of the round-trip time and a previous delay value, and dividing the sum by two.

15. A node for providing a pulse width modulated power signal being configured to perform a method according to claim 1.

16. A system for providing a pulse-width modulated power signal comprising a plurality of nodes and a central unit, the nodes and the central unit being configured to perform a method according to claim 8.

17. The method according to claim 2, wherein three phases are controlled by the node.

18. The method according to claim 3, wherein the timer is driven by a clock of the node.

19. The method according to claim 2, wherein the timer is synchronized by receiving a timer synchronization signal from another node and putting the timer to a value being determined by the timer synchronization signal and a delay time.

20. The method according to claim 3, wherein the timer is synchronized by receiving a timer synchronization signal from another node and putting the timer to a value being determined by the timer synchronization signal and a delay time.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will now be described with respect to the enclosed drawing, in which

(2) FIG. 1 shows a system for providing a pulse-width modulated power signal,

(3) FIG. 2 shows typical signal flows,

(4) FIG. 3 shows an implementation of control signals, and

(5) FIG. 4 shows a further implementation of control signals.

DETAILED DESCRIPTION

(6) FIG. 1 shows a system 5 for providing a pulse-width modulated power signal according to a typical implementation.

(7) The system 5 comprises a central unit 10 and three nodes 21, 22, 23 which are connected by a communication network 7. Each node controls three phases U, V, W in a way that it may relay each phase to a power consuming entity that is not shown in FIG. 1. The power consuming entity may be regarded as a power sink. Alternatively, the flow of power may be reversed. For example, also a power source may be connected to the phases U, V, W.

(8) Each node 21, 22, 23 has its own internal timer 31, 32, 33. They provide for timer values that are increased continuously and are used in order to control switching of the phases U, V, W. This will be explained further below.

(9) FIG. 2 shows typical signal flow between a MASTER node and a SLAVE node for timer synchronization. The MASTER node may either be the central unit 10, or it may be one of the nodes 21, 22, 23. Also the SLAVE node may either be the central unit 10, or it may be one of the nodes 21, 22, 23. The scheme of FIG. 2 just shows possible communication between two entities. It is noted that frames or signals for timer synchronization may especially be separate to frames or signals defining pulse width modulation. However, they may also be combined.

(10) At first, there may by a synchronization signal SYNC sent from the MASTER to the SLAVE. This synchronization signal SYNC comprises a current timer value t1.sub.master of the MASTER's internal timer. The slave uses this information in order to synchronize its own internal timer, namely by adding, to the timer value t1.sub.master, a delay value and by setting its own internal timer to the thus calculated value.

(11) The next two steps show how to determine the delay value. At first, a first determination signal TREQ is sent from the SLAVE to the MASTER, containing an identifier ID. Immediately afterwards, a second determination signal TRESP with the identifier ID and a timer value t2.sub.master of the MASTER is sent back from the MASTER to the SLAVE. The SLAVE is now able to calculate a round-trip time and thus to calculate the delay value. As a rule, the round-trip time minus processing times is twice the delay value. In order to smoothly adapt the delay value, the previous delay value may be added to the currently determined delay value, and the sum may be divided by 2 in order to get the new delay value.

(12) At later times t1.sub.master, a respective synchronization signal SYNC may be sent from the MASTER to the SLAVE in order to perform timer synchronization.

(13) FIG. 3 shows three phases U, V, W and four corresponding control signals, which are denoted by CS1, CS2, CS3, CS4. Each control signal CS comprises state values for each phase U, V, W and a timestamp in form of an absolute value Tstamp. If a state signal is 0, the respective phase should be off when the control signal CS is applied. If a state signal is 1, the respective phase should be on when the control signal CS is applied.

(14) At the beginning, all phases are off. When the first control signal CS1 is applied, this does not change. After the internal timer of the node, whose values are shown below the phases, has reached the absolute value Tstamp of the first control signal CS1, i.e. a value of 4000, the second control signal CS2 is applied, switching the phase V to on.

(15) After the absolute value Tstamp of the second control signal CS2 has been reached, the third control signal CS3 is applied, switching also phase U to on. After the absolute value Tstamp of the third control signal CS3 has been reached, the fourth control signal CS4 is applied, switching all phases U, V, W to off.

(16) The implementation of FIG. 4 shows the same functionality, i.e. an identical switching of phases, but with a slightly different implementation of the second control signal CS2 and the third control signal CS3. These control signals CS2, CS3 do not have absolute values Tstamp, but durations, for the time stamp. They set the intended duration of application of the respective control signal CS2, CS3 starting from the end of application of the previous control signal. As is shown, both implementations of time stamps can be combined, increasing flexibility.

(17) It should be noted that while FIGS. 3 and 4 show an implementation with only two possible values for the phase states, also more than two values can be used in other implementations. For example, each phase state may have three possible values.

(18) In summary, a new approach to providing a pulse-width modulated signal has been disclosed, which allows for a high accuracy and easy implementation.

(19) While the present disclosure has been illustrated and described with respect to a particular embodiment thereof, it should be appreciated by those of ordinary skill in the art that various modifications to this disclosure may be made without departing from the spirit and scope of the present disclosure.