Voltage level shifter applicable to very-low voltages

Abstract

Some embodiments provide a voltage-level shifter circuit comprising a cross-coupled transistor pull-up network that includes a plurality of diode-connected transistors configured to cause the state of the cross-coupled transistor network to switch at a low current through a pull-down network coupled thereto, such as a current corresponding to near-threshold voltage or sub-threshold voltage operation of the pull-down network.

Claims

1. A voltage level shifter circuit, comprising: a cross-coupled transistor network comprising (i) a first field-effect transistor (FET) of a first conductivity type having a source coupled to a first supply conductor that is configured to be electrically connected to a first supply voltage, (ii) a first plurality of series-connected diode-connected FETs of the first conductivity type, including a first diode-connected FET having a source electrically connected to a drain of the first FET, and a third diode-connected FET (iii) a second FET of the first conductivity type having a source coupled to the first supply conductor and having a gate coupled to the gate and drain of the third diode-connected FET, and (iv) a second plurality of series-connected diode-connected FETs of the first conductivity type, including a second diode-connected FET having a source electrically connected to a drain of the second FET, and a fourth diode-connected FET having a gate and a drain coupled to a gate of the first FET; a first input FET of a second conductivity type opposite to the first conductivity type, the first input FET having a source coupled to a second supply conductor that is configured to be electrically connected to a second supply voltage, a drain coupled to the drain of the third diode-connected FET, and a gate configured to receive an input logic signal having an input voltage swing that ranges from the second supply voltage to a third supply voltage that is between the second supply voltage and the first supply voltage; a second input FET of the second conductivity type, the second input FET having a source coupled to the second supply conductor, a drain coupled to the drain of the fourth diode-connected FET, and a gate configured to receive a second input logic signal having said input voltage swing and being complementary to the first input logic signal; and an output buffer transistor circuit coupled to the first supply conductor, to the second supply conductor, and to at least one node of the cross-coupled transistor network, and configured to provide an output logic signal corresponding to the input logic signal and having an output voltage swing that ranges from the second supply voltage to the first supply voltage.

2. The voltage level shifter circuit according to claim 1, wherein the cross-coupled transistor network includes no more than six transistors consisting of said first and second FETs and said first, second, third, and fourth diode-connected FETs, and is not directly coupled to any additional transistors except for the first and second input FETs and one or more transistors of the output buffer transistor circuit.

3. The voltage-level shifter circuit according to claim 2, wherein each of said first and second input FETs is not directly coupled to any additional transistors except for (i) the drains of said first and second input FETs being directly coupled respectively to the third and fourth diode-connected FETS, and (ii) the gates of the first and second input FETs being directly coupled to one or more transistors of an inverter that is coupled to the second supply conductor and to a third supply conductor that is configured to be electrically connected to the third supply voltage, such that the first input logic signal is one of an input signal and an output signal of the inverter and the second input logic signal is the other of the input signal and the output signal of the inverter.

4. The voltage level shifter circuit according to claim 3, wherein the voltage level shifter circuit comprises said inverter.

5. The voltage level shifter circuit according to claim 1, wherein the first input logic signal is one of an input signal and an output signal of an inverter, and the second input logic signal is the other of the input signal and the output signal of the inverter, wherein the inverter comprises a plurality of FETs and is coupled to the second supply conductor and to a third supply conductor that is configured to be electrically connected to the third supply voltage.

6. The voltage level shifter circuit according to claim 5, wherein the voltage level shifter circuit comprises said inverter.

7. The voltage level shifter circuit according to claim 1, wherein the output buffer transistor circuit comprises: a split-input inverter comprising (i) a first output buffer FET of the first conductivity type having a source coupled to the first supply conductor, a gate coupled to the drain of the second FET, and a drain, and (ii) a second output buffer FET of the second conductivity type having a drain coupled to the drain of the first output buffer FET, a source coupled to the second supply conductor, and a gate coupled to the drain of the fourth input FET; and a single-input output inverter comprising (i) a third output buffer FET of the first conductivity type having a source coupled to the first supply conductor, a gate coupled to the drain of the second output buffer FET, and a drain, (ii) a fourth output buffer FET of the second conductivity type having a drain coupled to the drain of the first output buffer FET, a source coupled to the second supply conductor, and a gate coupled to the gate of the third output buffer FET, and (iii) a node, coupled to the drains of the third and fourth output buffer FETs, at which the output logic signal is provided.

8. The voltage level shifter circuit according to claim 1, wherein each of the FETs of the voltage level shifter circuit, including said first and second FETS, said first, second, third, and fourth diode-connected FETs, and each transistor of the output buffer transistor circuit, are core transistors.

9. The voltage level shifter circuit according to claim 8, wherein each of the FETs of the first conductivity type are configured to have substantially the same first threshold voltage, and each of the FETs of the second conductivity type are configured to have substantially the same second threshold voltage.

10. The voltage level shifter circuit according to claim 9, wherein each of the FETs of the first conductivity type and each of the FETs of the second conductivity type has a gate having a gate length and a gate width, wherein the gate lengths of the FETs of the first and second conductivity types are configured to be substantially equal, and the gate widths of the FETs of the first and second conductivity types are configured to be substantially equal.

11. The voltage level shifter circuit according to claim 10, wherein for a given technology node at which the voltage-level shifter circuit is fabricated, the gate length is a minimum gate length for the technology node, and the gate width is a minimum gate width for the technology node.

12. The voltage level shifter according to claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type, the first and second FETs and the first, second, third, and fourth diode-connected FETs are p-channel insulated gate FETs, and the first and second input FETS are n-channel insulated gate FETs.

13. The voltage level shifter according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type, the first and second FETs and the first, second, third, and fourth diode-connected FETs are n-channel insulated gate FETs, and the first and second input FETS are p-channel insulated gate FETs.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Aspects, features, and advantages of some embodiments of the invention, both as to structure and operation, will be understood and will become more readily apparent in view of the following description of non-limiting and non-exclusive embodiments in conjunction with the accompanying drawings, in which like reference numerals designate the same or similar parts throughout the various figures, and wherein:

(2) FIG. 1 schematically depicts a known level-up shifter;

(3) FIG. 2 schematically depicts an illustrative voltage-level shifter circuit, in accordance with some embodiments;

(4) FIGS. 3, 4, 5, 6A, and 6B schematically depict alternative embodiments of the illustrative voltage-level shifter circuit of FIG. 2, in accordance with some embodiments;

(5) FIG. 7 schematically depicts an illustrative voltage-level shifter circuit incorporating additional diode-connected transistors, in accordance with some embodiments; and

(6) FIG. 8 schematically depicts an illustrative voltage-level shifter circuit corresponding to a complementary implementation of the illustrative voltage-level shifter circuit of FIG. 2, in accordance with some embodiments.

DETAILED DESCRIPTION OF SOME ILLUSTRATIVE EMBODIMENTS

(7) Throughout the description and claims, the following terms take at least the meanings explicitly associated herein, unless the context dictates otherwise. The meanings identified below do not necessarily limit the terms, but merely provide illustrative examples for the terms.

(8) The phrase “an embodiment” as used herein does not necessarily refer to the same embodiment, though it may. In addition, the meaning of “a,” “an,” and “the” include plural references; thus, for example, “an embodiment” is not limited to a single embodiment but refers to one or more embodiments. Similarly, the phrase “one embodiment” does not necessarily refer the same embodiment and is not limited to a single embodiment. As used herein, the term “or” is an inclusive “or” operator, and is equivalent to the term “and/or,” unless the context clearly dictates otherwise. The term “based on” is not exclusive and allows for being based on additional factors not described, unless the context clearly dictates otherwise.

(9) In addition, as used herein, unless the context clearly dictates otherwise, the term “coupled” refers to directly connected or to indirectly connected through one or more intermediate components and, in some contexts, may also denote or include electrically coupled, such as conductively coupled, capacitively coupled, and/or inductively coupled. Further, “conductively coupled (connected),” “electrically coupled (connected),” and “galvanically coupled (connected),” and similar variants, each refer to being coupled (connected) via one or more intermediate components that permit energy transfer via conduction current, which is capable of including direct current as well as alternating current, while “capacitively coupled” refers to being electrostatically coupled through one or more dielectric media, and possibly also via one or more intervening conductors (e.g., via a series of capacitive components), that permit energy transfer via displacement current and not via direct current between the coupled (connected) components. Those skilled in the art will further understand that elements may be capacitively coupled intentionally or unintentionally (e.g., parasitically) and that in some contexts, elements said to be capacitively coupled may refer to intentional capacitive coupling. In addition, those skilled in the art will also understand that in some contexts the term “coupled” may refer to operative coupling, through direct and/or indirect connection. For instance, a conductor (e.g., control line) said to be coupled to the gate of a transistor may refer to the conductor being operable to control the gate potential so as to control the operation of the transistor (e.g., switching the transistor between “on” and “off” states), regardless of whether the conductor is connected to the gate indirectly (e.g., via another transistor, etc.) and/or directly.

(10) For clarity, it is noted that the term MOS (metal-oxide-semiconductor), including its use in connection with PMOS (p-channel MOS), NMOS (n-channel MOS), and CMOS (complementary metal-oxide-semiconductor), as understood by those skilled in the art and as used herein, is not limited to technologies requiring a metal-oxide gate stack but may include, for example, gate conductors that comprise polysilicon or other non-metal materials (and that, in some implementations, may not include a metal) and/or gate dielectrics that comprise non-oxide materials (and that, in some implementations, may not include an oxide). As such, a MOSFET (MOS field effect transistor), whether a PMOS transistor or an NMOS transistor, more generally refers to an insulating gate field effect transistor, where the gate insulator may or may not comprise an oxide (e.g., silicon dioxide and/or hafnium oxide). Also for clarity, it is noted that the terms PMOS transistor, PMOS FET, p-type FET, p-channel FET, and p-type insulating gate FET, or similar variations, are used herein interchangeably, and, likewise, the terms NMOS transistor, NMOS FET, n-type FET, n-channel FET, and n-type insulating gate FET, or similar variations, are used herein interchangeably.

(11) FIG. 2 schematically depicts an illustrative voltage-level shifter circuit 10 in accordance with some embodiments according to the present disclosure. As shown, voltage-level shifter circuit 10 comprises a primary voltage-level shifter 12 coupled to an output buffer 16, with primary voltage-level shifter 12 having an input node V.sub.IN, output buffer 16 having an output node V.sub.OUT, and both primary voltage-level shifter 12 and output buffer 16 being supplied by a first supply voltage V.sub.DDH and a second supply voltage V.sub.SS, where V.sub.DDH is greater than V.sub.SS.

(12) As shown, voltage-level shifter circuit 10 according to the illustrative embodiment of FIG. 2 has its input node V.sub.IN coupled to V.sub.DDL core logic circuitry 5 and its output node V.sub.OUT coupled to V.sub.DDH circuitry 13. V.sub.DDH circuitry 13 is supplied at the same voltage levels as voltage-level shifter circuit 10 and output buffer 16; namely, V.sub.DDH and V.sub.SS. V.sub.DDL core logic circuitry 5 is supplied by the second supply voltage V.sub.SS and by a third supply voltage V.sub.DDL, wherein voltage V.sub.DDH is greater than voltage V.sub.DDL, which is greater than voltage V.sub.SS (i.e., V.sub.DDH>V.sub.DDL>V.sub.SS).

(13) Briefly, as further described hereinbelow following a further description of the circuit components and topology, in operation voltage level shifter circuit 10 (i) receives at input node V.sub.IN from V.sub.DDL core logic circuitry 5 an input logic signal having a voltage swing between voltage V.sub.SS and voltage V.sub.DDL and (ii) outputs at output node V.sub.OUT an output logic signal logically equivalent to the input logic signal and having a voltage swing between voltage V.sub.SS and voltage V.sub.DDH, wherein (as described) V.sub.DDH is greater than V.sub.DDL which is greater than V.sub.SS. More specifically, the logic level (e.g., “High” or logic 1, assuming positive logic) represented by voltage V.sub.DDL for the input logic signal is represented by voltage V.sub.DDH for the output logic signal, while the logic level represented by voltage V.sub.SS (e.g., “Low” or logic 0, assuming positive logic) is also represented by voltage V.sub.SS for the output logic signal.

(14) As will be understood, voltage V.sub.SS is a common reference potential with respect to voltage-level shifter circuit 10, V.sub.DDL core logic circuitry 5, and V.sub.DDH circuitry 13, and may be considered as being ground potential (i.e., V.sub.SS=0 V) for such an associated on-chip circuitry referenced to the same V.sub.SS rail voltage. In some embodiments, a system may comprise such an associated on-chip circuitry referenced to the same V.sub.SS rail as a circuit sub-system together with additional circuit sub-systems or modules (whether on the same chip, on different chips, and/or on different printed circuit boards, etc.) that, for example, may be supplied in series by a main power supply, so that different subsystems each may have respective rail voltages (e.g., V.sub.DDH, V.sub.DDL, V.sub.SS) at different voltages relative to the overall system ground.

(15) V.sub.DDL core logic circuitry 5 may comprise high-speed digital circuitry implemented using core transistors for the given process or technology node used to fabricate an integrated circuit comprising the circuitry schematically depicted in the illustrative embodiment of FIG. 2.

(16) For instance, as will be understood by those skilled in the art, foundry processes and technology nodes generally or typically specify core transistors and input/output (I/O) transistors. Such core transistors generally correspond to and are based on the minimum dimension (e.g., minimum gate length), highest speed transistors that may be fabricated using that technology node (e.g., in accordance with its specification and design rules, etc.), and thus are provided for implementing the high-density, high-speed logic circuitry of a given monolithic integrated circuit (e.g., “IC,” “chip,” or “die”). For clarity, as also understood by those skilled in the art, it is noted that core transistors employed within core circuitry are not necessarily all configured as minimum gate length devices (nor, e.g., as minimum gate width devices). The scale of the core transistors typically requires operation at lower voltage compared to, for example, I/O transistors. In this regard, operating core transistors above their nominal operating voltage range, such as at a higher I/O voltage range, generally not only degrades their performance (e.g., increased leakage current) while operating at that higher voltage, but also may degrade or damage the devices themselves, and may result in device failure (e.g., such as due to punch-through, avalanche breakdown, or gate dielectric breakdown, etc.), including possibly catastrophic (irreversible) failure.

(17) In contrast, the I/O transistors of a given technology node are provided for interfacing core circuitry with external (e.g., off-chip) circuits or components having generally high capacitance and typically operating at higher voltages than the core circuitry, thus requiring the I/O transistors and associated I/O circuitry to have higher current carrying and drive capacity and higher operating voltage than the core transistors. As used herein, the term I/O generally refers to such higher current-drive transistors and/or circuitry, unless the context clearly dictates otherwise. For instance, it is noted that some types of core circuitry may include certain input/output circuitry, such as high-speed memory input/output, so the term I/O used in connection with intra-core I/O functionality and circuitry (e.g., such as on-chip memory I/O) would be understood as not referring to I/O transistors and circuitry used for interfacing core circuitry with off-chip circuits or components.

(18) In some embodiments, V.sub.DDH circuitry 13 may comprise I/O circuitry and/or other non-core (and non-I/O) circuitry operating at so-called rail voltages of V.sub.DDH and V.sub.SS. In some embodiments, V.sub.DDH circuitry 13 may comprise core circuitry with the V.sub.DDH voltage level being the nominal voltage for high performance operation of the core transistors and circuitry (e.g., at or near lowest latency, optimal performance), and with the lower V.sub.DDL rail voltage supplied to V.sub.DDL core logic circuitry 5 to reduce power dissipation while being suitable for lower performance (e.g., lower speed) operation of core circuitry. For instance, such V.sub.DDL core logic circuitry 5 may comprise non-critical circuitry, such as circuitry that includes neither critical signal paths nor functional blocks or cells requiring the V.sub.DDH voltage level to attain the necessary and/or desired high speed operation. In other words, some embodiments may be directed to employing multi-supply voltage domain technology to partition core circuitry into different voltage supply domains to facilitate reduced and/or low power dissipation (e.g., compared to using a single voltage level for all core circuitry on the chip). In some such embodiments, I/O circuitry may be implemented at V.sub.DDH but at higher power (i.e., higher current drive), or alternatively at yet a further supply voltage greater than V.sub.DDH.

(19) In other words, this illustrative embodiment of voltage-level shifter 10 is schematically depicted as being implemented as a level-up converter between core circuitry and any of I/O circuitry, other core circuitry, and other non-I/O circuitry (e.g., which may not comprise core circuitry). Those skilled in the art will also understand that while FIG. 2 schematically depicts a single instance of a voltage-level shifter 10 on an integrated circuit, an integrated circuit typically may comprise numerous instances of such a voltage-level shifter 10.

(20) Referring again to FIG. 2, the depicted illustrative embodiment of primary voltage-level shifter 12 comprises (i) a pull-up network comprising PMOS transistors MP0, MP1, MD0, and MD1 configured as a cross-coupled transistor network 14, and (ii) a pull-down network comprising NMOS transistors MN0 and MN1. As shown, MP0, MD0, and MN0 are connected in series, with the source of MP0 connected to a conductor (e.g., a so-called rail) that is supplied at voltage V.sub.DDH, while the drain of MP0 is connected to the source of MD0, which in turn has its drain connected to the drain of pull-down transistor MN0, which has its source connected to a conductor (rail) that is supplied at voltage V.sub.SS. Likewise, MP1, MD1, and MN1 are connected in series, with the source of MP1 connected to the rail supplied at voltage V.sub.DDH, while the drain of MP1 is connected to the source of MD1, which in turn has its drain connected to the drain of pull-down transistor MN0, which has its source connected to a conductor (rail) that is supplied at voltage V.sub.SS.

(21) In this illustrative embodiment, both the gate of transistor MN0 and the gate of transistor MN1 are directly connected to respective complementary signals from core logic circuitry 5, which is depicted as comprising inverter 7 and inverter 9 connected in series, with inverter 9 providing an output logic signal (corresponding to the signal at input node N5 of inverter 7) to input node V.sub.IN, and with the output of inverter 7 connected to the input of inverter 9 and to the gate of transistor MN1. As such, in this illustrative embodiment, inverters 7 and 9 are not components of voltage level shifter circuit 10, but rather are components of core logic circuitry 5.

(22) Each of PMOS transistors MD0 and MD1 has its drain connected to its gate and to the gate of PMOS transistors MP1 and MP0, respectively. As known by those skilled in the art, the gate-to-drain connection in each of PMOS transistors MD0 and MD1 configures each of these transistors as a diode-connected PMOS transistor. As also known by those skilled in the art, such a diode-connected transistor is in saturation when operational (i.e., when ON due to the gate-to-source voltage being approximately at or below the gate-to-source threshold voltage), exhibiting a drain current that is a quadratic function of the difference between the drain-to-source voltage (equivalent to gate-to-source voltage) and the threshold voltage. In other words, upon conducting current, each diode-connected transistor MD0 and MD1 will have a source-to-drain voltage drop of at least about the magnitude of its threshold voltage.

(23) The source and drain of diode-connected PMOS transistor MD1 are connected to respective inputs of output buffer 16, which in this illustrative embodiment comprises a split-input inverter 18 coupled to a single-input inverter 20. More specifically, split-input inverter 18 includes series-connected pull-up PMOS transistor MP2 and pull-down NMOS transistor MN2 having their respective source terminals connected to conductors coupled to V.sub.DDH and V.sub.SS, respectively, and their respective gate terminals conductively coupled to the respective drains of pull-up transistor MP1 and pull-down transistor MN1.

(24) The output of split-input inverter 18 at node N2 is conductively coupled to the input of single-input inverter 20. More specifically, single-input inverter 20 includes series-connected pull-up PMOS transistor MP3 and pull-down NMOS transistor MN3 having their respective source terminals connected to conductors coupled to V.sub.DDH and V.sub.SS, respectively, and their respective gate terminals conductively coupled to each other and to the drains of pull-up transistor MP2 and pull-down transistor MN2. The output V.sub.OUT of single-input inverter 20, which is the output of the voltage-level shifter circuit 10, is input to V.sub.DDH circuitry 13.

(25) In some embodiments, such as that of FIG. 2, all transistors of primary voltage-level shifter 12, and optionally also all transistors of output buffer 16, may be implemented as core transistors. And depending on, for example, the relative current-voltage characteristics of the p-channel and n-channel transistors for the given technology node and process, each such core transistor of primary voltage-level shifter 12, and optionally also all transistors of output buffer 16, may be of minimum dimension (e.g., minimum gate width) for the technology node, in accordance with some embodiments. In addition, in some embodiments, such as that of FIG. 2, no additional transistors are connected to primary voltage shifter 12 other than as indicated (e.g., other than transistors of core logic circuitry 5 that provide a signal to V.sub.IN, and the output buffer 16 transistors that are connected to V.sub.OUT).

(26) Operation of voltage-level shifter circuit 10, and particularly operation of primary voltage-level shifter 12, according to the illustrative embodiment of FIG. 2 may be understood as follows, wherein for this illustrative embodiment all transistors are enhancement mode, all n-channel transistors have the same nominal threshold voltage V.sub.TN, all p-channel transistors have the same nominal threshold voltage V.sub.TP (V.sub.TP<0), V.sub.DDL is greater than V.sub.TN, and (V.sub.DDH−|V.sub.TP|) is greater than V.sub.TN. Those skilled in the art will understand that in describing certain aspects of circuit operation, for ease of discussion and convenience, transistors may be described in idealized or near-idealized manner such that, for example, subthreshold current or weak inversion may be ignored (e.g., the drain current is considered zero when the transistor is in the “off” state). In view of the present disclosure, however, those skilled in the art will understand that in some implementations, non-ideal characteristics (e.g., subthreshold current as a function of gate-source voltage and drain-source voltage) should be considered for fully understanding operation of the circuit and/or for advantageously implementing a voltage level shifter according to some embodiments.

(27) Assuming positive logic and arbitrarily assuming an initial state (during operation) in which the input V.sub.IN to the gate of transistor MN0 is low (i.e., MN0 is off; e.g., V.sub.IN=V.sub.SS) and the complementary input to the gate of transistor MN1 is high (i.e., MN1 is on, with a voltage of, e.g., V.sub.DDL input to its gate), then in this state the voltage at node NL1 is pulled down to V.sub.SS by MN1, so that transistor MP0 is on and node NL0 is pulled up to a nominal voltage in the inclusive range of (V.sub.DDH−|V.sub.TP|) to V.sub.DDH, as the drain current through MP0 and MD0 is nominally zero so the drain-to-source voltage (V.sub.DS) drop across MP0 is nominally zero and the source-to-drain voltage (V.sub.SD) drop across MD0 is nominally in the inclusive range of |V.sub.TP| to zero. MP1 is thus nominally off (VSG is nominally in the inclusive range of |V.sub.TP| to zero) and the voltage at node NH1 is nominally in the inclusive range of (V.sub.SS+|V.sub.TP|) to V.sub.SS, as the drain current through MN1 and MD1 is nominally zero so the drain-to-source voltage (V.sub.DS) drop across MN1 (which is on) is nominally zero and the source-to-drain voltage (V.sub.SD) drop across MD1 is nominally in the inclusive range of |V.sub.TP| to zero.

(28) In this state, with indicated nominal voltages at nodes NH1 and NL1, transistors MP2 and MN2 are on and off, respectively, so that node N2 is pulled up to voltage V.sub.DDH. Thus, transistors MP3 and MN3 are off and on, respectively, so that V.sub.OUT is pulled down to V.sub.SS. In other words, V.sub.OUT is low, the same logic level as V.sub.IN.

(29) For a low-to-high V.sub.IN transition from this initial state, as V.sub.IN transitions from V.sub.SS to V.sub.DDL, as MN0 begins conducting current (sinking current from node NL0) such that diode-connected transistor MD0 begins conducting concomitant current, the voltage drop across diode-connected transistor MD0 increases above |V.sub.TP|, thus turning on transistor MP1, thereby pulling up the node NH1 voltage and concomitantly pulling up the node NL1 voltage as transistor MN1 turns off as its gate voltage transitions from V.sub.DDL to V.sub.SS in complement to V.sub.IN. As node NL1 is pulled up to a nominal voltage in the inclusive range of (V.sub.DDH−|V.sub.TP|) to V.sub.DDH, transistor MP0 is turned off, eliminating any pull-up contention, as node NL0 is pulled down to V.sub.SS and node NH0 to a nominal voltage in the inclusive range of V.sub.SS to (V.sub.SS+|V.sub.TP|), as the state of the pull-up network (latch) 14 switches (e.g., toggles or inverts) from the above-assumed initial state to its other state.

(30) In accordance with the foregoing operation of the primary voltage level shifter 12 during such low-to-high V.sub.IN transition, it will be understood that as nodes NH1 and NL1 are respectively pulled up to the indicated voltages, transistors MP2 and MN2 are turned off and on, respectively, thus pulling down node N2 to V.sub.SS. Thus, transistors MP3 and MN3 are turned on and off, respectively, so that V.sub.OUT is pulled up to voltage V.sub.DDH. In other words, V.sub.OUT transitions from low to high logic level, following the same logic level transition as V.sub.IN.

(31) Based on the foregoing operational description of a low-to-high Vin transition, the operation of voltage level shifter 10 under a high-to-low V.sub.IN transition may be readily understood as follows. As V.sub.IN transitions from V.sub.DDL to V.sub.SS and the complementary gate input signal of MN1 transitions from low-to-high (i.e., from V.sub.SS to V.sub.DDL), as MN1 begins conducting current (sinking current from node NL1) such that diode-connected transistor MD1 begins conducting concomitant current, the voltage drop across diode-connected transistor MD1 increases above |V.sub.TP|, thus turning on transistor MP0, thereby pulling up the node NH0 voltage and concomitantly pulling up the node NL0 voltage as transistor MN0 turns off as its gate voltage transitions from V.sub.DDL to V.sub.SS. As node NL0 is pulled up to a nominal voltage in the inclusive range of (V.sub.DDH−|V.sub.TP|) to V.sub.DDH, transistor MP1 is turned off, eliminating any pull-up contention at node NL1, as node NL1 is pulled down to V.sub.SS and node NH1 to a nominal voltage in the inclusive range of (V.sub.SS+|V.sub.TP|) to V.sub.SS, as the state of the cross-coupled pull-up network (latch) 14 switches (e.g., toggles or inverts) from the above-referenced other state to the above-assumed initial state. Accordingly, it will be understood that during such a high-to-low Vin transition, as nodes NL1 and NH1 are pulled down to the indicated voltages, transistors MN2 and MP2 are turned off and on, respectively, thus pulling up N2 to V.sub.DDH. Thus, transistors MP3 and MN3 are turned off and on, respectively, so that V.sub.OUT is pulled down to voltage V.sub.SS. In other words, V.sub.OUT transitions from high to low logic level, following the same logic level transition as V.sub.IN.

(32) In view of the foregoing description of an illustrative embodiment of a voltage level shifter 10, it will be understood by those skilled in the art that configuring the cross-coupled pull-up network 14 of the primary voltage level shifter 12 to include diode-connected transistors MD0 and MD1 mitigates or effectively eliminates contention between the pull-up network 14 and the pull-down network (comprising transistors MN0 and MN1), such as compared to the conventional level shifter of FIG. 1. For instance, as described, in accordance with some embodiments, a voltage drop across MD0 (MD1) sufficient to turn off pull-up transistor MP1 (MP0) can be developed at a very low current through pull-down transistor MN0 (MN1) as the gate voltage of MN0 (MN1) increases from V.sub.SS to V.sub.DDL. In other words, in accordance with some embodiments, the load characteristic of diode-connected transistor MD0 (MD1) causes the cross-coupled latch network 14 to initiate and effect a state change at a low current as V.sub.IN transitions from V.sub.SS to V.sub.DDL (V.sub.DDL to V.sub.SS) such that pull-down NMOS transistor NM0 (NM1) need not be oversized (e.g., compared to the size that would be used for implementing a high speed inverter in core logic) for sinking sufficient current to overcome pull-up contention. The capability to effect state change at low current levels (e.g., such that the pull-down transistors need not be oversized) due to the operation of the diode-connected transistors concomitantly renders voltage level shifter 10 well-suited for shifting low or very low V.sub.DDL levels.

(33) For example, in various alternative embodiments, for a given technology node (e.g., of a commercial foundry process), such a drain-to-source current level through pull-down transistor MN0 (MN1) at which sufficient voltage develops across diode-connected transistor MD0 (MD1) so as to turn off pull-up transistor MP1 (MP0) may be the drain-to-source current of an n-channel core transistor of minimum dimension when the gate-to-source voltage of MN0 (MN1) is nominally equal to or greater than but near (e.g., within about 300 mV) the threshold voltage V.sub.TN (e.g., referred to as “near-threshold” voltage, and the corresponding current as near-threshold current), or, alternatively, is less than the threshold voltage V.sub.TN (e.g., referred to as “sub-threshold” voltage, and the corresponding current as sub-threshold current).

(34) As described, in some embodiments such as that depicted in FIG. 2, primary voltage-level shifter 12 may be configured for coupling to V.sub.DDL core logic circuitry 5 that is appropriately configured to provide both an input logic signal at node V.sub.IN to the gate of MN0 and a complement of the input logic signal to the gate of MN1. As such, primary voltage-level shifter 12 need not itself comprise an inverter configured to receive a logic signal from V.sub.DDL core logic circuitry 5 and generate a complementary logic signal, such that an input logic signal and its complement are input to MN0 and MN1, respectively.

(35) In various alternative embodiments, however, such as depicted in FIGS. 3 and 4, primary voltage-level shifter 12 may comprise such an inverter 8 (thus requiring an additional two transistors). In FIG. 3, V.sub.DDL core logic circuitry 5 outputs a logic signal to be level-shifted, and this output of V.sub.DDL core logic circuitry 5 is connected to both the inverter 8 input and node V.sub.IN, and the inverter 8 output is connected to the gate of MN1. In FIG. 4, V.sub.DDL core logic circuitry 5 outputs the complement of a logic signal to be level-shifted, and this output of V.sub.DDL core logic circuitry 5 is connected to both the inverter 8 input and the gate of MN1, and the inverter 8 output is connected to node V.sub.IN.

(36) Various alternative embodiments may employ different configurations of output buffer circuit 16, including various alternative dual-stage configurations as well as single-stage configurations. For instance, FIG. 5 schematically depicts a voltage level converter circuit comprising voltage converter stage 12 configured with a single-stage split-input inverter 18 that provides the level-shifted output V.sub.OUT, in accordance with some embodiments. As shown, the respective gates of pull-up PMOS transistor MP3 and pull-down NMOS transistor MN3 of split-input inverter 18 are conductively coupled to nodes NH0 and NL0, respectively.

(37) Also by way of example, FIGS. 6A and 6B schematically depict alternative embodiments of a voltage-level converter circuit comprising voltage converter stage 12 configured with a single-stage single-input inverter 16 that provides the level-shifted output V.sub.OUT. As shown, the gates of pull-up PMOS transistor MP3 and pull-down NMOS transistor MN3 of single-input inverter 16 are conductively coupled to node NH0 in FIG. 6A and to node NL0 in FIG. 6B.

(38) FIG. 7 schematically depicts an alternative embodiment in which each branch of the cross-coupled pull-up network includes two series-connected diode-connected transistors. More specifically, one branch comprises diode-connected PMOS transistors MD0 and MD2 connected in series with each other and with pull-up transistor MP0, while the other branch comprises diode-connected PMOS transistors MD1 and MD3 connected in series with each other and with pull-up transistor MP0. Compared to the embodiment of FIG. 2, for example, the additional diode-connected transistor in each branch of the pull-up network provides additional voltage drop to further facilitate initiating and effecting turn-on of the pull-up PMOS transistor in the opposing branch of the pull-up network at low current (and concomitantly, low voltage at V.sub.IN) as the pull-down transistor of the same branch turns on. It will be understood that various alternative embodiments may employ more than two series-connected diode-connected transistors in each branch of the pull-up network.

(39) FIG. 8 schematically depicts an illustrative alternative embodiment of a voltage level-shifter 30 corresponding to the complementary circuit of the embodiment of FIG. 2. As shown, voltage level shifter circuit 30 comprises a primary voltage level shifter 22 and output buffer 16 being supplied by a first supply voltage V.sub.DDH and a second supply voltage V.sub.SS (indicated as being at ground potential) where V.sub.DDH is greater than V.sub.SS. V.sub.DLL core logic circuitry 15 is supplied by the first supply voltage V.sub.DDH and by a third supply voltage V.sub.DLL, wherein voltage V.sub.DDH is greater than voltage V.sub.DLL, which is greater than voltage V.sub.SS (i.e., V.sub.DDH>V.sub.DLL>V.sub.SS).

(40) Primary voltage-level shifter 22 comprises (i) a pull-down network comprising NMOS transistors MN4, MN5, MD4, and MD5 configured as a cross-coupled transistor network, and (ii) a pull-up network comprising PMOS transistors MP4 and MP5. MD4 and MD5 are configured as diode-connected NMOS transistors. Briefly, in operation voltage level shifter circuit 30 (i) receives at input node V.sub.IN from V.sub.DLL core logic circuitry 15 an input logic signal having a voltage swing between voltage V.sub.DDH and voltage V.sub.DLL and (ii) outputs at output node V.sub.OUT an output logic signal logically equivalent to the input logic signal and having a voltage swing between voltage V.sub.DDH and voltage V.sub.SS. More specifically, the logic level represented by voltage V.sub.DLL for the input logic signal is represented by voltage V.sub.SS for the output logic signal, while the logic level represented by voltage V.sub.DDH for the input logic signal is also represented by voltage V.sub.DDH for the output logic signal. In view of the foregoing detailed disclosure of the operation of the illustrative embodiment of FIG. 2, operation of voltage level shifter 30, including the operation effect of including the diode-connected transistors MD4 and MD5, may be readily understood and therefore is not described in detail.

(41) In some embodiments, voltage level shifters (such as level shifters 10 and 30) may be designed with each of the PMOS transistors specified as having the same PMOS threshold voltage and each of the NMOS transistors as having the same NMOS threshold voltage. As will be understood by those skilled in the art, however, upon fabrication of such voltage level shifter 10 and 30, the actual threshold voltages of the PMOS transistors will vary somewhat as will the actual threshold voltage of the NMOS transistors (e.g., due to process-related and/or geometry-related variations), so that the PMOS transistors may be said to have substantially the same PMOS threshold voltage and, likewise, the NMOS transistors may be said to have substantially the same NMOS threshold voltage. In some embodiments, however, a voltage level shifter (such as level shifter 10 or 30) may be designed according to multi-threshold voltage design to further optimize, e.g., power dissipation, timing, and operation. For instance, various commercial CMOS technology nodes provide for transistors (e.g., FinFETs) of each type (i.e., PMOS and NMOS) within the same chip to be selectively designed to have any of at least two different threshold voltages (e.g., normal, high, and low threshold voltages).

(42) Embodiments in accordance with the present disclosure, such as the hereinabove described illustrative embodiments, are not limited to a particular FET technology or CMOS process or technology node. By way of non-limiting example, FETs may be implemented as planar FETs, FinFETs, or gate-all-around (GAA) FETs, and technology nodes may include commercial foundry. As may be appreciated, however, embodiments in accordance with the present disclosure are particularly well-suited for overcoming pull-up versus pull-down contention limitations.

(43) Accordingly, in view of the foregoing disclosure, it may be understood that by incorporating diode-connected transistors into the cross-coupled latch network so as to cause the state of the cross-coupled latch to be switched at a low current (e.g., at a subthreshold or near-threshold current), the current contention problem is mitigated or averted in a way that does not require transistor over-sizing, thus allowing the level shifter to be implemented with core transistors, and concomitantly providing for low propagation delay, low power dissipation, and reduced chip real estate requirements (e.g., compared to at least the known level-shifter of FIG. 1).

(44) By way of non-limiting example and simply for purposes of illustration, various simulations of a level shifter 10 in accordance with some embodiments, have demonstrated very low-propagation delay, very low power dissipation level-shifting of input signals ranging from 0.23 V to 0.35 V, over V.sub.DDH ranging from 0.6 V to 0.85 V, with V.sub.SS set as ground potential (i.e, zero volts), an NMOS threshold voltage of 0.18 V, and a PMOS threshold voltage of −0.18 V.

(45) It may be further appreciated that by dropping a portion of the rail-to-rail voltage, the diode-connected transistors also reduce the voltage drop—and hence stress—on the pull-up the pull-down transistors, which further facilitates or enables implementing the transistors as core transistors, which typically are specified with (and can sustain) lower maximum drain-to-source voltage than, for example, I/O transistors.

(46) It may be further understood that a primary voltage level shifter 12 in accordance with some embodiments, such as that illustrated in FIG. 2, requires no more than six transistors, and each transistor may be implemented as a core transistor. Likewise, in accordance with some embodiments, such as those illustrated in FIGS. 6A and 6B, wherein primary voltage level shifter 12 may also comprise an inverter coupled between the gates of pull-down transistors MN0 and MN1, primary voltage level shifter 12 requires no more than eight transistors. As such, voltage level shifters in accordance with embodiments of the present disclosure occupy a small region of chip real estate.

(47) In view of the present disclosure, those skilled in the art will further understand that various alternative embodiments are not limited to incorporating into the latch network diode-connected FETs of the same conductivity type as the pull-up (or pull-down) latch transistors to which they are coupled. For instance, various alternative embodiments may be provided by substituting diode-connected NMOS transistors for diode-connected PMOS transistors MD0, MD1, MD2, MD3 in the foregoing embodiments of FIGS. 2-5, 6A, 6B and 7. Likewise, an illustrative alternative embodiment may be provided by substituting diode-connected PMOS transistors for diode-connected NMOS transistors MD4 and MD5 in the embodiment of FIG. 8. Likewise, those skilled in the art will understand in view of the foregoing disclosure that various alternative embodiments are not limited to diode-connected insulating gate FETs being incorporated into the latch network, and may alternatively or additionally employ any appropriate rectifying device, such as a diode-connected junction field effect transistor (JFET), a two-terminal p-n junction diode, and/or a metal-semiconductor junction (e.g., Schottky diode).

(48) Although the above description of illustrative embodiments of the present invention, as well as various illustrative modifications and features thereof, provides many specificities, these enabling details should not be construed as limiting the scope of the invention, and it will be readily understood by those persons skilled in the art that the present invention is susceptible to many modifications, adaptations, variations, omissions, additions, and equivalent implementations without departing from this scope and without diminishing its attendant advantages. For instance, the structure and/or function of a component may be combined into a single component or divided among two or more components. In addition, it is specifically contemplated that a particular feature described, either individually or as part of an embodiment, can be combined with other individually described features, or parts of other embodiments. It is further noted that the terms and expressions have been used as terms of description and not terms of limitation. There is no intention to use the terms or expressions to exclude any equivalents of features shown and described or portions thereof. Additionally, the present invention may be practiced without necessarily providing one or more of the advantages described herein or otherwise understood in view of the disclosure and/or that may be realized in some embodiments thereof. It is therefore intended that the present invention is not limited to the disclosed embodiments but should be defined in accordance with claims that are based on the present disclosure, as such claims may be presented herein and/or in any patent applications claiming priority to, based on, and/or corresponding to the present disclosure.