METHOD OF MAKING MEMORY CELLS, TRANSISTOR DEVICES AND LOGIC DEVICES ON SILICON-ON-INSULATOR SUBSTRATE

Abstract

A method of forming a semiconductor device by providing a substrate having bulk silicon, an insulation layer over the bulk silicon, and a silicon layer over the insulation layer. The silicon and insulation layers are removed from first and second areas, while maintained in a third area. A memory cell is formed in the first area having a floating gate over a first portion of a memory cell channel region and a control gate over a second portion of the memory cell channel region. A transistor device is formed in the second area having a transistor gate over a transistor channel region. A logic device is formed in the third area having a logic device gate over a logic device channel region. The memory cell channel region and the transistor channel region are disposed in the bulk silicon. The logic device channel region is disposed in the silicon layer.

Claims

1. A method of forming a semiconductor device, comprising: providing a substrate that includes bulk silicon, an insulation layer over the bulk silicon, and a silicon layer over the insulation layer; performing an etch process to remove the silicon layer and the insulation layer from a first area and a second area of the substrate to expose the bulk silicon in the first area and the second area of the substrate, while maintaining the insulation layer and the silicon layer in a third area of the substrate; forming a memory cell in the first area by: forming a memory cell source region and a memory cell drain region in the bulk silicon, with a memory cell channel region of the bulk silicon extending between the memory cell source region and the memory cell drain region, forming a floating gate disposed over and insulated from a first portion of the memory cell channel region, and forming a control gate disposed over and insulated from a second portion of the memory cell channel region; forming a transistor device in the second area by: forming a transistor source region and a transistor drain region in the bulk silicon, with a transistor channel region of the bulk silicon extending between the transistor source region and the transistor drain region, and forming a transistor gate disposed over and insulated from the transistor channel region; and forming a logic device in the third area by: forming a logic device source region and a logic device drain region in the silicon layer, with a logic device channel region of the silicon layer extending between the logic device source region and the logic device drain region, and forming a logic gate disposed over and insulated from the logic device channel region.

2. The method of claim 1, wherein: the transistor gate is insulated from the transistor channel region by a first insulation; and the logic gate is insulated from the logic device channel region by a second insulation; wherein the first insulation has a thickness that is greater than a thickness of the second insulation.

3. The method of claim 1, wherein the control gate has a first portion laterally adjacent to and insulated from the floating gate and over and insulated from the second portion of the memory cell channel region, and a second portion that extends up and over the floating gate.

4. A semiconductor device, comprising: a substrate of bulk silicon and having a first area, a second area and a third area, an insulation layer disposed over the bulk silicon, and a silicon layer disposed over the insulation layer, in the third area of the substrate, wherein the silicon layer and the insulation layer are not present in the first area and the second area of the substrate; a memory cell in the first area comprising: a memory cell source region and a memory cell drain region in the bulk silicon, with a memory cell channel region of the bulk silicon extending between the memory cell source region and the memory cell drain region, a floating gate disposed over and insulated from a first portion of the memory cell channel region, and a control gate disposed over and insulated from a second portion of the memory cell channel region; a transistor device in the second area comprising: a transistor source region and a transistor drain region in the bulk silicon, with a transistor channel region of the bulk silicon extending between the transistor source region and the transistor drain region, and a transistor gate disposed over and insulated from the transistor channel region; and a logic device in the third area comprising: a logic device source region and a logic device drain region in the silicon layer, with a logic device channel region of the silicon layer extending between the logic device source region and the logic device drain region, and a logic gate disposed over and insulated from the logic device channel region.

5. The semiconductor device of claim 4, wherein: the transistor gate is insulated from the transistor channel region by a first insulation; and the logic gate is insulated from the logic device channel region by a second insulation; wherein the first insulation has a thickness that is greater than a thickness of the second insulation.

6. The semiconductor device of claim 4, wherein the control gate has a first portion laterally adjacent to and insulated from the floating gate and over and insulated from the second portion of the memory cell channel region, and a second portion that extends up and over the floating gate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG. 1 is a side cross sectional view illustrating a silicon on insulator (SOI) substrate.

[0034] FIG. 2 is a side cross sectional view illustrating the removal of the silicon layer and the insulation layer from a portion of the silicon on insulator (SOI) substrate of FIG. 1.

[0035] FIG. 3 is a side cross sectional view illustrating the memory cell area, the transistor device area, and the logic device area of the silicon on insulator (SOI) substrate of FIG. 2.

[0036] FIG. 4A is a side cross sectional view illustrating memory cells formed in the memory cell area of the silicon on insulator (SOI) substrate.

[0037] FIG. 4B is a side cross sectional view illustrating transistor devices formed in the transistor device area of the silicon on insulator (SOI) substrate.

[0038] FIG. 4C is a side cross sectional view illustrating logic devices formed in the logic device area of the silicon on insulator (SOI) substrate.

DETAILED DESCRIPTION OF THE INVENTION

[0039] The present example is a process of forming a semiconductor device, in which split gate non-volatile memory cells and transistor devices are formed alongside logic devices on a silicon on insulator substrate, also referred to herein as an SOI substrate. The process begins by providing an SOI substrate 10, as illustrated in FIG. 1. The SOI substrate includes three portions: bulk silicon 10a, an insulation layer 10b (e.g. an oxide layer) over the bulk silicon 10a, and a silicon layer 10c over the insulation layer 10b. Forming SOI substrates is well known in the art as described above and in the U.S. patents identified above, and therefore is not further described herein. As a non-limiting example, the silicon layer 10c can have a thickness of 30-500 (Angstroms), and the insulation layer 10b can have a thickness of 200 .

[0040] A photolithography process is performed which includes forming a photo-resist material 11 on silicon layer 10c, selective exposure of the photo-resist material 11, followed by selective removal of portions of the photo-resist material 11 to expose portions of silicon layer 10c in a first region 12 of the substrate 10. An etch process with one or more etches is then performed in the first region 12 to remove silicon layer 10c and insulation layer 10b from the first region 12 leaving the bulk silicon 10a exposed (and leaving silicon layer 10c and insulation layer 10b intact in a second region 14 of the substrate 10), as shown in FIG. 2. After photo-resist material 11 is removed, the substrate 10 can be considered to have three areas: memory cell area 16 (first area) and a transistor device area 18 (second area) (both of which are in the first region 12 in which silicon layer 10c and insulation layer 10b were removed), and a logic device area 20 (in the second region 14 in which the silicon layer 10c and insulation layer 10b were maintained), as shown in FIG. 3.

[0041] Split gate memory cells 24 are formed in the memory cell area 16, as illustrated in FIG. 4A. A respective split gate memory cell 24 includes a memory cell source region 26 and a memory cell drain region 28 formed in the bulk silicon 10a, with a memory cell channel region 30 of the bulk silicon 10a extending there between. A floating gate 32 is formed over (i.e., vertically over and laterally overlapping), and insulated from (for directly controlling the conductivity of), a first portion of the memory cell channel region 30 and partially over and insulated from the memory cell source region 26. A control gate 34 is formed having a first portion laterally adjacent to, and insulated from, the floating gate 32 and disposed over, and insulated from (for directly controlling the conductivity of), a second portion of the memory cell channel region 30. Control gate 34 includes a second portion that extends up and over the floating gate 32. As a non-limiting example, the bulk silicon 10a can be P-type, with the memory cell source and drain regions 26/28 being N-type. The floating gate 32 is formed of a conductive material such as polysilicon, and has a concave upper surface that terminates in a sharp edge facing the control gate 34. The control gate 34 is formed of a conductive material such as polysilicon.

[0042] Transistor devices 40 are formed in the transistor device area 18, as illustrated in FIG. 4B. Transistor device 40 includes a transistor source region 42 and a transistor drain region 44 formed in the bulk silicon 10a, with a transistor channel region 46 of the bulk silicon 10a extending there between. A transistor gate 48 is formed over (for directly controlling the conductivity of) the transistor channel region 46, and is insulated from the transistor channel region 46 by insulation 54. As a non-limiting example, the bulk silicon 10a can be P-type and include a P-type well region 50, with the transistor source and drain regions 42/44 being N-type. However, other transistor devices 40 in the same transistor device area 18 can be formed where the bulk silicon 10a includes an N-Type well 52, in which case the transistor source/drain regions 42/44 can be P-Type. Insulation 54 can be an oxide. Transistor devices 40 can be insulated from each other by shallow trench isolation (STI) 56, which can be insulation material such as oxide disposed in trenches formed into the substrate surface.

[0043] Logic devices 60 are formed in the logic device area 20, as illustrated in FIG. 4C. Logic device 60 includes a logic device source region 62 and a logic device drain region 64 formed in the silicon layer 10c, with a logic device channel region 66 of the silicon layer 10c extending there between. A logic gate 68 is formed over (for directly controlling the conductivity of) the logic device channel region 66, and is insulated from the logic device channel region 66 by insulation 70. Logic devices 60 can be insulated from each other by shallow trench isolation (STI) 56.

[0044] The above technique of removing the silicon layer 10c and insulation layer 10b from the memory cell area 16 (also referred to as first area 16) and transistor device area 18 (also referred to as second area 18) while maintaining these layers in the logic device area 20 (also referred to as third area 20), and thereby forming the memory cells and the transistor devices on the bulk silicon (i.e., forming their source/drain regions in the bulk silicon), means they can be operated at higher voltages without suffering from junction breakdowns that can result if the memory cells and transistor devices were formed on silicon layer 10c. Forming the logic devices on the silicon layer 10c has the benefit of reduced silicon geometries while simplifying the manufacturing process, while providing tight electrostatic control of the logic device and reduced power consumption. To accommodate higher operational voltages for the transistor device 40 relative to the logic device 60, the insulation 54 (first insulation) under the transistor gate 48 can have a thickness that is greater than the thickness of insulation 70 (second insulation) under the logic gate 68.

[0045] It is to be understood that the present disclosure is not limited to the example(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of any claims. For example, references to the present disclosure or invention or examples herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method operations need be performed in the exact order illustrated or claimed, but rather in any order (unless there is an explicitly recited limitation on any order) that allows the proper formation of the devices described herein. Single layers of material could be formed as multiple layers of such or similar materials, and vice versa. Lastly, the terms forming and formed as used herein shall include material deposition, material growth, or any other technique in providing the material as disclosed or claimed.

[0046] It should be noted that, as used herein, the terms over and on both inclusively include directly on (no intermediate materials, elements or space disposed therebetween) and indirectly on (intermediate materials, elements or space disposed therebetween). Likewise, the term adjacent includes directly adjacent (no intermediate materials, elements or space disposed therebetween) and indirectly adjacent (intermediate materials, elements or space disposed there between). For example, forming an element over a substrate can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.