CIRCUITS AND METHODS TO CALIBRATE MIRROR DISPLACEMENT

Abstract

A method includes setting first and second capacitor plates of a capacitive structure to an initial displacement position; applying a known control voltage to at least one of the first and second capacitor plates to generate a first displacement; measuring a first capacitance of the capacitive structure at the first displacement; setting the first and second capacitor plates to a second displacement; measuring a second capacitance of the capacitive structure at the second displacement; determining the difference between the first and second capacitances to determine the difference between the first and second displacements; and adjusting the control voltage based on results of the determining operation.

Claims

1. A method comprising: applying, by a circuit, a first voltage to at least one of a first capacitor and a second capacitor of a capacitive structure, to produce a first displacement of the first capacitor with respect to the second capacitor; measuring, by the circuit, a first capacitance of the capacitive structure after applying the first voltage; applying, by the circuit, a second voltage to at least one of the first capacitor or the second capacitor to produce a second displacement of the first capacitor with respect to the second capacitor; measuring, by the circuit, a second capacitance of the capacitive structure after applying the second voltage; determining a difference between the first capacitance and the second capacitance to determine a difference between the first displacement and the second displacement; and determining a third control voltage responsive to the difference between the first displacement and the second displacement.

2. The method of claim 1, wherein determining the third control voltage comprises comparing the difference between the first displacement and second displacement to a reference displacement.

3. The method of claim 1, wherein applying the first voltage comprises applying a digital code to electrodes of the second capacitor.

4. The method of claim 3, further comprises applying a third voltage to the first capacitor.

5. The method of claim 1, wherein measuring the first capacitance of the capacitive structure comprises: applying a fourth voltage to the first capacitor to charge the capacitive structure for a first time period; connecting a constant current source to the first capacitor during a second time period while the capacitive structure discharges; generating a fifth voltage responsive to the fourth voltage; and determining a time for a discharging voltage to decrease to the fifth voltage.

6. The method of claim 1, wherein measuring the first capacitance comprises: in response to receiving, by a timer from a controller, a first signal, beginning counting to produce a count value; and in response to receiving, by the timer from a comparator, a second signal, outputting the count value to the controller.

7. The method of claim 1, wherein the first capacitor is a mirror and the second capacitor is an electrode.

8. A method comprising: transmitting, by a circuit, a first code to a capacitive structure to set a first displacement of a first capacitive plate of the capacitive structure with respect to a second capacitive plate of the capacitive structure; measuring, by the circuit, a first capacitance of the capacitive structure after transmitting the first code; transmitting, by the circuit, a second code to the capacitive structure to set a second displacement of the first capacitive plate with respect to the second capacitive plate; measuring, by the circuit, a second capacitance of the capacitive structure after transmitting the second code; and determining a difference between the first displacement and the second displacement responsive to a difference between the first capacitance and the second capacitance.

9. The method of claim 8, further comprising: comparing the difference between the first displacement and the second displacement with a target displacement.

10. The method of claim 9, further comprising: transmitting a third code to the capacitive structure responsive to the comparison of the difference between the first displacement and the second displacement to the target displacement.

11. The method of claim 8, wherein the first capacitive plate is a mirror and the second capacitive plate is an electrode.

12. A method comprising: transmitting, by a controller, a first control word to a voltage generator; setting, by the voltage generator, a first voltage of a mirror responsive to the first control word; measuring, by the controller, a first capacitance of the mirror after setting the mirror to the first voltage; transmitting, by the controller, a second control word to the voltage generator; setting, by the voltage generator, a second voltage of a mirror responsive to the second control word; measuring, by the controller, a second capacitance of the mirror after setting the mirror to the second voltage; and determining, by the controller, a difference between the first capacitance and the second capacitance to determine a difference between a first distance of the mirror at the first voltage and a second distance of the mirror at a second voltage.

13. The method of claim 12, wherein measuring the first capacitance comprises generating, by a timer, a count indicating a time to discharge the mirror responsive to comparing, by a comparator, a voltage across the mirror to a reference voltage.

14. The method of claim 12, wherein the mirror is a mirror of a phase light modulator.

15. The method of claim 12, further comprising determining a third voltage responsive to the difference between the first distance and the second distance.

16. The method of claim 15, wherein determining the third voltage comprises comparing the difference between the first distance and second distance to a reference displacement.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Features of the disclosure may be understood from the following figures taken in conjunction with the detailed description.

[0011] FIGS. 1A, 1B and 1C illustrate an example of a pixel structure including a mirror and an electrostatic actuator.

[0012] FIG. 2 illustrates an example of an array of mirrors, which may be employed in a PLM or other suitable device.

[0013] FIG. 3 is a block diagram of an example of a calibration circuit that may be used to calibrate one or more mirrors.

[0014] FIG. 4 is a diagram illustrating an exemplary capacitance measurement sequence using the calibration circuit of FIG. 3.

[0015] FIG. 5 is a flow diagram of an example method of calibrating one or more mirrors.

[0016] FIG. 6 is a flow diagram of an example method of calibrating one or more mirrors.

[0017] FIG. 7 is a block diagram of an example device including a calibration circuit and mirrors that may be calibrated according to examples described herein.

DETAILED DESCRIPTION

[0018] Specific examples are described below in detail with reference to the accompanying figures. These examples are not intended to be limiting. In the drawings, corresponding numerals and symbols generally refer to corresponding parts unless otherwise indicated. The objects depicted in the drawings are not necessarily drawn to scale.

[0019] The terms connected, coupled and derivatives thereof, as used herein, include direct connection or coupling between two elements, indirect connection or coupling through one or more intervening elements, as well as contactless or wireless communication. Relative terms such as top, bottom, base and the like indicate relative position with respect to the orientation being described or as shown in the drawing under discussion; such terms do not indicate absolute position or orientation. Directional terms, i.e., downwardly and the like are also relative to the context of what is being described. These terms do not require that any device or structure be constructed or operated in a particular orientation.

[0020] In example arrangements, a mirror (or group of mirrors) in a device may be calibrated to establish and/or maintain a specific relationship between each of multiple displacement targets of a mirror and its corresponding control parameter(s) to accommodate different operating wavelengths, to compensate for process, voltage, temperature variations, and/or to adjust for drift associated with age. Calibration can be conveniently performed when the device is powered up and/or periodically during operation. Calibration can be done at the device level in which all mirrors are calibrated together, or at a finer level, e.g., different groups of mirrors are calibrated differently, to accommodate for variation across the array of mirrors or provide different displacement target-control parameter(s) relationships for different groups of mirrors.

[0021] In an example, the voltage applied to a mirror being calibrated is set to its minimum value and a voltage applied to the address electrode(s) of the mirror's associated base plate is set to its expected operating voltage. The capacitance of the mirror structure is measured at one setting of the address electrode(s). The setting of the address electrode(s) is then changed, and the capacitance of the mirror structure is measured again at the new setting. The difference in the two capacitance measurements corresponds to the difference in displacement between the two settings. If the difference in displacement is less than desired, the difference in the applied voltages is increased to increase electrostatic force and hence increase displacement. If the difference in displacement is greater than desired, the voltage differential may be decreased. After adjustment of the voltage differential in either direction, the process may be repeated until the difference in displacement is as desired.

[0022] All mirrors in an array of mirrors may be calibrated together. In another example, different groups of mirrors within the array may be calibrated differently. In that scenario, the above-described process may be applied to each mirror in a given group to calibrate those mirrors a particular way. The process may then be applied to each mirror of a different group using different control parameters, i.e., different voltages and electrode address settings, to calibrate those mirrors in a different way. Calibration may be done in situ, i.e., by circuits and components in the device, e.g., PLM, in which the mirror(s) reside, thereby avoiding the need for additional overhead for calibration.

[0023] FIGS. 1A, 1B and 1C (collectively, FIG. 1) are diagrams showing example structures and electrostatic actuator design. FIG. 1A illustrates an example structure 100 (e.g., pixel structure) of a parallel-plate electrostatic actuator (e.g., which may be used to implement a MEMS PLM). FIG. 1B shows an example electrode pattern 120 that may be employed in structure 100. FIG. 1C shows an example plate or pixel geometry 130 that may be used to implement structure 100.

[0024] Referring to FIG. 1A, structure 100 includes a mirror 102, structure plate 103, mirror attachments 104 (e.g., mirror vias), a top plate 106, flexural beams 107, support posts 108, base plate 110, and electrode voltage controller 112. Mirror 102 reflects a beam of light in two or more directions depending on the position of the mirror. For example, mirror 102 may be extended in a first position (e.g., a neutral position when no voltage is applied to base plate 110) to reflect light in a first direction and be retracted to a second position to reflect light in a second direction. Different voltages may be applied to base plate 110 to change the distance (displacement) between it and mirror 102. In an arrangement of many mirrors 102, their movements result in directional beam steering based on a summation of the positions of the mirrors 102. Each individual mirror displacement results in a fractional change in the phase of the light incident on it.

[0025] Mirror 102 may be supported by (e.g., hosted within) structural plate 103. Mirror 102 is attached to top plate 106 by coupling structural plate 103 to mirror attachments 104, which are coupled to top plate 106. In another example construction, structural plate 103 may be omitted, in which case mirror 102 may be directly coupled to mirror attachments 104. Mirror 102 and structural plate 103 (when used) are configured to be larger than top plate 106, such that mirror 102 and structural plate 103 (when used) overlap support posts 108. In this manner, support posts 108 act as a mechanical stop to mirror 102 (and structural plate 103) past a preset position corresponding to the height of support posts 108. Although example structure 100 includes three mirror attachments, structure 100 may include any suitable number of mirror attachment(s).

[0026] Top plate 106 is an electrode that includes flexural beams 107. Flexural beams 107 correspond to a mechanical spring constant that, when stretched, applies a mechanical force in the opposite direction of the stretching. Flexural beams 107 are attached to support posts 108. In this manner, when an electrostatic force is applied to top plate 106 to move it downwardly, flexural beams 107 extend toward base plate 110, causing top plate 106 to lower to a different position. Top plate 106 and flexural beams 107 may be made of the same material. Mirror attachments 104 may provide rigidity to top plate 106 to ensure that it does not flex as the electrostatic force increases. Support posts 108 may be longer in length than mirror attachments 104, i.e., S1>S2, to prevent top plate 106 from getting too close to base plate 108.

[0027] The amount of voltage applied to base plate 110 determines how much top plate 106 is displaced. In a PLM, base plate 110 has a digital-style electrode design, in which multiple electrode segments can be selectively energized by loading data into an underlying memory array, e.g., an SRAM memory array. In an example, as shown in FIG. 1B, base plate 110 includes an electrode pattern 120 that includes three electrode segments: an inner electrode 122, a middle electrode 124 and an outer electrode 126. Each of these electrodes can be held at 0 V (off state) or driven to a set non-zero voltage (V.sub.OFFSET), e.g., 10 V (on state), enabling eight different combinations. Thus, these three electrodes form a 3-bit cell capable of 8 unique addressable states, each specified by a unique 3-digit code. The electrode areas may be designed so that four of the addressable states will produce an approximately linear displacement profile. Top plate 106 (and mirror 102) is connected to a mirror bias signal that is typically held at a 0 V reference state, although the mirror bias signal can be trimmed to a non-zero value for performance adjustment and calibration. V.sub.OFFSET can also be changed during calibration. When one or more of electrodes 122, 124 and 126 are activated, a potential difference between top plate 106 and base plate 110 is generated. This creates an electrostatic force that deflects top plate 106 (and mirror 102) until an equilibrium state is reached with the spring restoration force. This design operates in a non-contact mode with displacements up to about one third the initial electrostatic gap. Each electrode address state has a target displacement at the 0 V reference state of the mirror bias signal.

[0028] FIG. 1C shows an example plate geometry 130 (e.g., pixel geometry) that may be used to implement pixel structure 100. Plate geometry 130 is square-based. Thus, mirror 102, top plate 106 and base plate 110 each has a square shape. In the illustrated example, plate geometry 130 includes five mirror attachments 104 to couple top plate 106 to mirror 102, although any suitable number of mirror attachments 104 may be used.

[0029] In this example, the structure includes extended flexural beams 137 which attach to support posts 108 and top plate 106. Extended flexural beams 137 work in a similar manner to flexural beams 107. Extended flexural beams 137, however, are longer, thereby providing more spring/flexibility than flexural beams 107. More spring allows top plate 106 to move with less electrostatic force, and hence less voltage need be applied. Alternatively, flexural beam 107 of FIG. 1A may be used to attach support posts 108 to top plate 106.

[0030] FIG. 1C represents one possible plate geometry, i.e., square-based geometry. The calibration features described herein, however, are not limited to square-based geometry. The calibration may be performed with any suitable geometry, including rectangle-based, triangle-based, circle-based, hexagonal-based, etc.

[0031] FIG. 2 is a schematic view of an array of mirrors 200, i.e., multiple mirrors, one of which is identified by reference numeral 202. All mirrors 202 of array 200 may be calibrated together. Alternatively, two or more groups of mirrors may be calibrated differently. To that end, FIG. 2 illustrates a group of mirrors 204, which is a subset of the mirrors in array 200. Each mirror 206 in group 204 may be calibrated together, and these mirrors 206 may be calibrated differently than the other mirrors of array 200.

[0032] FIG. 3 is a block diagram of an example of a calibration circuit 300 that may be used to calibrate a movable mirror structure, i.e., pixel structure 100, in a device such as a PLM. Calibration circuit 300, which is electrically coupled to pixel structure 100, includes a programmable voltage generator 302 and a capacitance measurement circuit 304.

[0033] Pixel structure 100 may be constructed as described in connection with FIG. 1. As shown in FIG. 3, pixel structure 100 includes a top capacitor plate 306 and a bottom capacitor plate 308. Top capacitor plate 306 may correspond to the assembly of mirror 102, structure plate 103 and mirror attachments 104 of FIG. 1. Bottom capacitor plate 308 may correspond to base plate 110 of FIG. 1. Bottom capacitor plate 308 includes one or more electrodes, as shown in FIG. 1. Pixel structure 100 also includes a spring 307 that provides a restoring force to top capacitor plate 306. Spring 307, shown schematically in FIG. 3, may correspond to flexural beams 107/137 of FIG. 1.

[0034] Programmable voltage generator 302 may include a digital-to-analog converter (DAC) 310 that has a digital input at which DAC 310 receives a control word or code from capacitance measurement circuit 304. Based on that code, DAC 310 generates an analog signal that is applied to the input of a voltage regulator 312 of the programmable voltage generator 302. Voltage regulator 312, under the control of DAC 310, generates different values of a voltage (VDAC) that is supplied to top capacitor plate 306.

[0035] Capacitance measurement circuit 304 includes two switches: switch 314 that, when closed, connects the output of voltage regulator 312 to top capacitor plate 306, and switch 316 that, when closed, connects a constant current source 318 of circuit 304 to top capacitor plate 306. Constant current source 318 generates constant current I.sub.REF.

[0036] A reference voltage generator (A Voltage Reference) 320 of capacitance measurement circuit 304 is coupled to the output of voltage regulator 312 and generates a reference voltage (V.sub.REF) that is a fixed difference from VDAC, i.e., the voltage generated by voltage regulator 312. Capacitance measurement circuit 304 further includes a comparator 322. The positive input of comparator 322 is coupled to top capacitance plate 306, and the negative input of comparator 322 is coupled to the output of reference voltage generator 320. Thus, during a capacitance measurement sequence when the capacitor (first and second capacitance plates 306 and 308) is discharging, comparator 322 compares the discharging voltage V.sub.BIAS to V.sub.REF and outputs a digital signal when the sign of (V.sub.BIAS-V.sub.REF) changes.

[0037] Capacitance measurement circuit 304 also includes a digital counter/timer 324 and a digital controller 326, both of which are clocked components. To that end, each of digital counter/timer 324 and digital controller 326 has an input at which a clock signal received. Digital counter/timer 324 receives a start input signal from digital controller 326 at the start of a capacitance measurement sequence to begin counting and receives a stop input signal from comparator 322 to stop counting at substantially the same time that comparator 322 outputs the digital signal to digital controller 326, which marks the end of that capacitance measurement sequence. In response to receiving the stop signal from comparator 322, digital counter/timer 324 outputs the count to digital controller 326. Digital controller 326, which may correspond to electrode voltage controller 112 of FIG. 1, also resets the counter after the current capacitance measurement sequence is completed and before the next capacitance measurement sequence is performed.

[0038] Digital controller 326, which may operate as a state machine, is configured to perform numerous functions in addition to controlling start and reset of digital counter/timer 324. Digital controller 326 also controls the sequence of each of the capacitance measurements. For each measurement (or set of measurements) to be made with the mirror(s) at a specific state or displacement, digital controller 326 generates a code (control word) and transmits the code to the digital input of DAC 310 for generation of a value of VDAC to be applied to top capacitor plate 306. Digital controller 326 also generates a code or address bits that are transmitted to bottom capacitor plate 308 to drive each of its electrodes to a specific state.

[0039] Digital controller 326 also calculates capacitance across top and bottom capacitor plates 306 and 308 based on the count received from digital counter/timer 324, the sign change output of comparator 322, I.sub.REF, which represents the current across the capacitance plates 306 and 308. I.sub.REF is stored in, or otherwise made known to, digital controller 326. After such calculation, digital controller 326 is able to store the calculation, and over the course of the overall measurement process store multiple capacitance measurements.

[0040] An exemplary capacitance measurement sequence is illustrated in FIG. 4. A clock signal is supplied to counter/timer 324 and digital controller 326. With top and bottom capacitor plates 306 and 308 spaced apart by a first unknown distance, switch 314 (indicated by .sub.1 in FIG. 4) is closed to supply the voltage VDAC to charge the capacitive structure (represented by plates 306 and 308 in FIG. 3). Switch 316 is closed while switch 314 is open. Initially, V.sub.BIAS, which is the voltage of the capacitive structure, is the same as VDAC. In response to a command from digital controller 326, counter/timer 324 is started to begin generating a count. Switch 314 is opened, and switch 316 (indicated by .sub.2 in FIG. 4) is closed to apply I.sub.REF to the capacitive structure and begin discharge. Switches 314 and 316 may be controlled by digital controller 326.

[0041] As the voltage across the capacitive structure (V.sub.BIAS) drops, counter/timer 324 provides an indication of the time it takes for V.sub.BIAS to drop to V.sub.REF (V in FIG. 4) and outputs a count indicative of such time to digital controller 326. Digital controller 326 also receives from comparator 322 a digital signal when V.sub.BIAS becomes less than V.sub.REF (V) indicating that sign change. The slope of the decrease of V.sub.BIAS during discharge is indicative of the ratio of the current (I.sub.REF) across the capacitive structure to its capacitance, e.g., I.sub.REF/C. From this information and based on the relationship I=Cdv/dt, where I is I.sub.REF, digital controller 326 can calculate capacitance (C) across top and bottom capacitor plates 306 and 308.

[0042] This measurement sequence may then be repeated with plates 306 and 308 spaced apart by a second unknown distance, different from the first unknown distance. Before performing the next measurement sequence, digital controller 326 updates the control word sent to DAC 310 and resets counter/timer 324.

[0043] From these capacitance measurements and knowing the area of overlap between the top and bottom capacitors plate 306 and 308 (A), the difference between the first and second distances (displacement difference) may be determined using the capacitance formula: C=A/d, where d is the distance between the capacitor plates and is the dielectric constant. Rearranging gives: d=A/C. Inputs A and are stored in, or made available to, digital controller 326. In an example configuration in which all pixel structures 100 have the same configuration, A may be a single value representing the area of each mirror.

[0044] If the displacement difference is not what is desired, one or both of the control voltages, e.g., VDAC and V.sub.OFFSET, may be adjusted and the process repeated. In an example, if the displacement difference is less than that desired, the voltage(s) may be adjusted such that the voltage differential applied to capacitor plates 306 and 308 is increased to increase electrostatic force and hence increase displacement; and if the displacement difference is greater than that desired, the voltage differential may be decreased to decrease electrostatic force and hence decrease displacement.

[0045] FIG. 5 is a flow diagram of an example method 500 of calibrating one or more mirrors of a PLM. For each mirror or pixel structure 100 to be calibrated, at operation 502 the capacitance of that mirror is measured at a first setting of the address electrodes of the bottom capacitor plate and known control voltage(s), e.g., V.sub.BIAS and/or V.sub.OFFSET, are applied. Then, at operation 504, with the setting of the address electrodes changed to a second setting and known control voltage(s) are applied, the capacitance of each mirror is measured again. At operation 506, for each mirror being calibrated, the difference in displacement between that mirror and its bottom capacitor plate for the two measurements is determined. At operation 508, that difference in displacement is compared with a desired or target displacement. If the displacement difference is greater than desired, the difference between the control voltages is decreased in operation 510 and the process repeated. If the displacement difference is less than desired, the difference between the control voltages is increased in operation 512 and the process repeated. If the displacement difference is as desired, the process ends.

[0046] FIG. 6 is a flow diagram of an example method 600 of calibrating one or more mirrors of a device with an array of mirrors, such as a PLM. Initially, at operation 602, one or more mirrors that are to be calibrated are selected. For each mirror selected, a voltage V.sub.BIAS is applied to top capacitor plate 306 and/or a voltage V.sub.OFFSET is applied to electrodes of bottom capacitor plate 308 in operation 604. In operation 606, a first code is transmitted to the electrodes of each bottom capacitor plate 308 to set the top and bottom capacitor plates 306 and 308 of each mirror in a first state of displacement (d.sub.1). In this first state of displacement, in operation 608, for each selected mirror, the capacitance of the capacitive structure is measured to obtain a first capacitance measurement (C.sub.1). Then, in operation 610, a second code is transmitted to the electrodes of bottom capacitor plates 308 to set the top and bottom capacitor plates 306 and 308 of each mirror in a second state of displacement (d.sub.2). In operation 612, for each selected mirror, capacitance of the capacitive structure is again measured at this second state of displacement to obtain a second capacitance measurement (C.sub.2). In operation 614, (d.sub.1-d.sub.2) is determined based on (C.sub.1-C.sub.2). Next, in operation 616, it is determined whether the displacement difference is as desired. If not, one or both of V.sub.BIAS and V.sub.OFFSET is adjusted in operation 618, and the process returns to operation 606 to set another state of displacement. If the displacement difference is as desired, calibration is complete.

[0047] Calibration can be performed for differences in displacement for different wavelengths, to compensate for temperature differences, as well as to maintain consistency over the life of the device.

[0048] FIGS. 5 and 6 each depict one possible order of operations to calibrate mirror(s). Not all operations need necessarily be performed in the order described. Some operations may be combined into a single operation. Additional operations may be performed as well.

[0049] FIG. 7 is a block diagram of an example of a device 700, embodying or including a PLM, that includes calibration circuit 300. For example, device 700 may include a light source assembly 702, which may include a lamp or laser. In some examples, light source assembly 702 may also include one or more lenses. The light generated by light source assembly 702 is directed toward a micromirror array and supporting structure 704, which may include an array of pixel structures 100 described above. Device 700 may also include a projection lens assembly 706 to which selected micromirrors of the micromirror array direct light. Other micromirrors may direct light to a light absorber 708 or light dump. At various times throughout the life of device 700, calibration circuit 300 may be used to calibrate the micromirrors of device 700 according to examples described herein.

[0050] PLM technology may be applied in various applications, some of which may be categorized based on wavelength. In the ultraviolet portion of the spectrum, applications in lithography and 3D printing can be realized. In the visible spectrum, a PLM device can be used for augmented reality or virtual reality (AR/VR), or automobile headlights. In the near-infrared (NIR) space, the device can be used for telecommunication or ranging applications.

[0051] Various examples of calibration circuits, devices, and methods of calibrating mirror displacement in a device with movable mirror structures, e.g., a digitally controlled MEMS PLM, are provided. All calculations, measurements, comparisons, adjustments, etc. may be done in situ, i.e., in and by the device, e.g., PLM, in which calibration circuit 300 resides. Calibrations may be performed from time-to-time to compensate for variations in manufacturing processes, to adjust for different wavelengths, and/or to produce predictable results over an extended period of time, e.g., the lifetime of the device.

[0052] Modifications of the described examples are possible, as are other examples, within the scope of the claims. Moreover, features described herein may be applied in other environments and applications consist with the teachings provided.