PIEZOELECTRIC-ON-INSULATOR (POI) SUBSTRATE AND METHOD FOR PRODUCING A PIEZOELECTRIC-ON-INSULATOR (POI) SUBSTRATE

Abstract

A piezoelectric-on-insulator substrate comprises a support substrate having a first acoustic impedance, a piezoelectric layer, especially a layer of lithium tantalate, lithium niobate, aluminum nitride, lead zirconate titanate, langasite or langatate, a dielectric layer having a second acoustic impedance and sandwiched between the piezoelectric layer and the support substrate, an intermediate layer positioned between the support substrate and the dielectric layer. The intermediate layer is a layer having a variable composition, in particular along its thickness, such that the acoustic impedance of the intermediate layer varies, in particular gradually, between the values of the first and the second acoustic impedances. The present disclosure also relates to a method for producing such a piezoelectric-on-insulator substrate and also to a surface acoustic wave device comprising such a piezoelectric-on-insulator substrate.

Claims

1. A piezoelectric-on-insulator (POI) substrate, comprising: a support substrate having a first acoustic impedance; a piezoelectriclayer; a dielectric layer having a second acoustic impedance positioned between the piezoelectric layer and the support substrate; and an intermediate layer positioned between the support substrate and the dielectric layer; wherein the intermediate layer is a layer having a variable composition along its thickness, such that the acoustic impedance of the intermediate layer varies between the values of the first acoustic impedance and the second acoustic impedance.

2. The piezoelectric-on-insulator substrate of claim 1, wherein the support substrate is a silicon-based substrate, the dielectric layer is a layer of silicon oxide and the intermediate layer is a layer of silicon oxynitride SiO.sub.xN.sub.y having a variable oxygen composition and/or a variable nitrogen composition.

3. The piezoelectric-on-insulator substrate of claim 1, wherein a variation in the composition of the intermediate layer is a gradual linear variation or a stepwise variation.

4. The piezoelectric-on-insulator substrate of claim 1, wherein the quantity qt of the variable composition of the silicon oxynitride SiO.sub.xN.sub.y layer is defined by qt=y/(y+x) and varies along a thickness of the silicon oxynitride SiO.sub.xN.sub.y layer.

5. The piezoelectric-on-insulator substrate of claim 4, wherein the quantity qt at the interface with the support substrate is equal to about 0.5 and the support substrate comprises a (100) Si support substrate.

6. The piezoelectric-on-insulator substrate of claim 4, wherein the quantity qt of the silicon oxynitride SiO.sub.xN.sub.y layer varies in an increasing manner between the interface with the dielectric layer of the piezoelectric layer and the interface with the support substrate.

7. The piezoelectric-on-insulator substrate of claim 1, further comprising a trapping layer on the support substrate.

8. A method of producing a piezoelectric-on-insulator substrate according to claim 1, the method comprising: providing a support substrate having a first acoustic impedance; providing a piezoelectric substrate; forming a dielectric layer having a second acoustic impedance on the piezoelectric substrate; forming an intermediate layer on a free surface of the support substrate, the intermediate layer having a variable composition along a thickness e of the intermediate layer, such that the acoustic impedance of the intermediate layer varies between the values of the first acoustic impedance and the second acoustic impedance; and joining the piezoelectric substrate with the dielectric layer with the support substrate with the intermediate layer.

9. The method of claim 8, wherein the joining of the piezoelectric substrate and the support substrate comprises bonding the intermediate layer directly to the dielectric layer.

10. The method of claim 8, further comprising forming a dielectric layer on the intermediate layer of the support substrate before the joining of the piezoelectric substrate with the support substrate, the joining comprising bonding the dielectric layer of the support substrate directly to the dielectric layer of the piezoelectric substrate.

11. The method of claim 8, wherein the forming of the intermediate layer on the free surface of the support substrate comprises forming a layer based on silicon oxynitride SiO.sub.xN.sub.y in which the amount of nitrogen in relation to the oxygen in the silicon oxynitride SiO.sub.xN.sub.y layer defined by qt.sub.1=y/(y+x) varies along its a thickness e.sub.1 of the intermediate layer.

12. The method of claim 8, wherein the forming of the intermediate layer on the free surface of the support substrate comprises forming a layer based on silicon oxynitride SiO.sub.xN.sub.y in which the quantity qt.sub.2 of the silicon oxynitride SiO.sub.xN.sub.y layer defined by qt.sub.2=y/(y+x) varies along a thickness e.sub.2 of the layer based on silicon oxynitride SiO.sub.xN.sub.y, and the method further comprises forming a SiO.sub.xN.sub.y layer on the dielectric layer of the piezoelectric substrate before the joining, the SiO.sub.xN.sub.y layer having a quantity qt.sub.3 for the SiO.sub.xN.sub.y layer defined by qt.sub.3=y/(y+x) that varies along a thickness e.sub.3 of the SiO.sub.xN.sub.y layer, the joining comprising bonding the SiO.sub.xN.sub.y layer of the support substrate and the SiO.sub.xN.sub.y layer of the piezoelectric substrate, where qt.sub.2 is equal to qt.sub.3 at an interface between the SiO.sub.xN.sub.y layer of the piezoelectric substrate and the SiO.sub.xN.sub.y layer of the support substrate.

13. The method of claim 8, further comprising forming a trapping layer on the support substrate.

14. The method of claim 8, wherein the forming of the intermediate layer comprises radiofrequency sputtering in a mixed oxygen and nitrogen atmosphere.

15. A surface acoustic wave device (SAW) comprising a piezoelectric-on-insulator substrate according to claim 1.

16. The piezoelectric-on-insulator substrate of claim 1, wherein the piezoelectric layer comprises a layer of lithium tantalate (LTO), lithium niobate (LNO), aluminium nitride (AlN), lead zirconate titanate (PZT), langasite or langatate.

17. The piezoelectric-on-insulator substrate of claim 1, wherein the acoustic impedance of the intermediate layer varies in a gradual manner between the values of the first acoustic impedance and the second acoustic impedance.

18. The piezoelectric-on-insulator substrate of claim 1, wherein qt is 0 at the interface with the dielectric layer and qt is at least 0.4 at the interface with the support substrate.

19. The piezoelectric-on-insulator substrate of claim 4, wherein the quantity qt at the interface with the support substrate is equal to about 0.68 and the support substrate comprises a (110) Si support substrate.

20. The piezoelectric-on-insulator substrate of claim 4, wherein the quantity qt at the interface with the support substrate is equal to about 0.7 and the support substrate comprises a (111) Si support substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present disclosure and its advantages will be explained in more detail below by way of preferred embodiments and supported, in particular, by the accompanying figures that follow, in which the reference numbers identify characteristics of the present disclosure.

[0024] FIG. 1 is a schematic representation of a piezoelectric-on-insulator (POI) substrate according to a first embodiment of the present disclosure.

[0025] FIG. 2 shows the variation in the velocity of sound in the intermediate layer as a function of the quantity qt of the composition of the intermediate layer for qt values corresponding to qt=0, qt=0.33, qt=0.50, qt=0.68 and qt=1, according to the first embodiment of the present disclosure.

[0026] FIG. 3 depicts the variation in acoustic impedance of the intermediate layer as a function of the quantity qt of the intermediate layer according to the first embodiment of the present disclosure.

[0027] FIG. 4 is a schematic representation of a piezoelectric-on-insulator (POI) substrate according to a first variant of the first embodiment of the present disclosure.

[0028] FIG. 5A is a schematic representation of a process for producing a piezoelectric-on-insulator (POI) substrate according to a second embodiment of the present disclosure.

[0029] FIG. 5B is a schematic representation of a process for producing a piezoelectric-on-insulator (POI) substrate according to a first variant of the second embodiment of the present disclosure.

[0030] FIG. 5C is a schematic representation of a process for producing a piezoelectric-on-insulator (POI) substrate according to a second variant of the second embodiment of the present disclosure.

DETAILED DESCRIPTION

[0031] The present disclosure will be described in more detail using advantageous embodiments in an exemplary manner and with reference to the drawings. The embodiments described are simply possible configurations and it should be kept in mind that the individual characteristics as described above can be provided independently of one another or can be omitted entirely in the implementation of the present disclosure.

[0032] FIG. 1 is a schematic representation of a piezoelectric-on-insulator (POI) substrate according to a first embodiment of the present disclosure.

[0033] The piezoelectric-on-insulator (POI) substrate 100 comprises a support substrate 102 joined to a piezoelectric layer 104 via an intermediate layer 106 positioned on the support substrate 102 that is in direct contact with the support substrate 102 at the interface 108 and with a dielectric layer 110 at the interface 112. The dielectric layer 110 is in direct contact with the piezoelectric layer 104 at the interface 114.

[0034] The support substrate 102 may be a silicon-based substrate, especially a silicon-based solid substrate. The support substrate 102 may be a crystalline or polycrystalline substrate. The support substrate 102 based on crystalline silicon may have an orientation (111), an orientation (100) or else an orientation (110). The silicon (100) has an acoustic impedance Z equal to 19.4*10.sup.6 P.Math.a s/m, the silicon (111) has an acoustic impedance of Z=21.6*10.sup.6 Pa.Math.s/m, the silicon (110) has an acoustic impedance of Z=21.1*10.sup.6 Pa.Math.s/m.

[0035] According to the present disclosure, the dielectric layer 110 is a silicon oxide-based layer having a thickness between 100 nm and 900 nm, more particularly between 200 nm and 700 nm. The dielectric layer 110 has a second acoustic impedance that is different from the first acoustic impedance of the support substrate 102, since the silicon oxide has an acoustic impedance of between 11.5*10.sup.6 Pa.Math.s/m and 14*10.sup.6 Pa.Math.s/m, more particularly about 13.7*10.sup.6 Pa.Math.s/m. In one variant, the dielectric layer 110 may also be a silicon nitride-based layer or a layer comprising a combination of silicon nitride and silicon oxide SiO.sub.xN.sub.y in which the amount of nitride in the layer is constant.

[0036] The piezoelectric layer 104 is a layer based on a piezoelectric material having a thickness of between 200 nm and 700 nm. The piezoelectric material may, for example, be lithium tantalate (LTO), lithium niobate (LNO), aluminum nitride (AlN), lead zirconate titanate (PZT), langasite or langatate.

[0037] The intermediate layer 106 is a layer having a variable composition, more particularly along its thickness e.sub.1. The variation in the composition of the intermediate layer 106 is such that the acoustic impedance of the intermediate layer 106 varies between the values of the first and the second acoustic impedance of the support substrate 102 and of the dielectric layer 110, respectively. The variable acoustic impedance of the intermediate layer 106 makes it possible to limit the influence of the difference in acoustic impedance between the dielectric layer 110 and the support substrate 102 of the POI substrate 100 when gradually passing from the first impedance value to the second impedance value.

[0038] According to one embodiment of the present disclosure, the intermediate layer 106 is a layer based on silicon oxynitride SiO.sub.xN.sub.y. The thickness e.sub.1 of the intermediate layer 106 is between 100 nm and 1000 nm, more particularly between 200 nm and 1000 nm.

[0039] The intermediate layer 106 of silicon oxynitride SiO.sub.xN.sub.y according to the present disclosure has a stoichiometry that varies as a function of its thickness e.sub.1 so as to adjust its acoustic impedance. This is because the acoustic impedance of the layer depends on the variation in the amount of oxygen and/or the variation in the amount of nitrogen in the layer.

[0040] The values for x and y are set such that a desired or predetermined variation in the acoustic impedance is observed. The amount of oxygen and nitrogen in the intermediate layer 106 depends on the production process used to deposit the layer of SiO.sub.xN.sub.y.

[0041] According to one embodiment, the intermediate layer is produced as described in Grahn et al.: Elastic properties of silicon oxynitride films determined by picosecond acoustics, Applied Physics Letters 53, 2281 (1988), so as to obtain a stoichiometry in the intermediate silicon oxynitride SiO.sub.xN.sub.y layer 106 that varies according to qt.sub.1(e.sub.1)=y/(y+x). The SiO.sub.xN.sub.y layer is produced by radiofrequency sputtering (RF sputtering) in a mixed oxygen and nitrogen atmosphere. The composition of the SiO.sub.xN.sub.y layer is thus controlled by varying the ratio y/(y+x), which corresponds to the amount of nitrogen and the amount of nitrogen and oxygen in the atmosphere during deposition.

[0042] The variation in the quantity qt of the silicon oxynitride SiO.sub.xN.sub.y layer 106 is a variation in the thickness e.sub.1 of the intermediate layer 106 between the two surfaces of the intermediate layer 106. In this first embodiment, the variation in the quantity qt.sub.1 of the silicon oxynitride SiO.sub.xN.sub.y layer 106 is an increasing variation between the interface 112 with the dielectric layer 110 and the interface 108 with the support substrate 102. The variation is, for example, a stepwise increase or is a linear increase.

[0043] FIG. 2 shows the variation in the velocity of the longitudinal acoustic wave V.sub.longi in the intermediate layer 106 as a function of the quantity qt of nitrogen (N) in the intermediate layer 106 for values for the quantity qt in the intermediate layer 106 of 0, 0.33, 0.50, 0.68 and 1. This figure has been published by Grahn et al. Elastic properties of silicon oxynitride films determined by picosecond acoustics, Applied Physics Letters 53,2281 (1988).

[0044] A linear increase in the velocity of the longitudinal acoustic wave as a function of an increase in the quantity qt of the intermediate layer 106 can also be seen. The line representing the linear variation is an adjustment by the least-squares method at the data points.

[0045] Starting from the data in FIG. 2, the acoustic impedance is obtained by calculating the acoustic impedance Z where Z=V.sub.longi*density, V.sub.longi being the velocity of the longitudinal acoustic wave, according to Grahn et al.: Elastic properties of silicon oxynitride films determined by picosecond acoustics, Applied Physics Letters 53, 2281 (1988).

[0046] The variation in the acoustic impedance of the SiO.sub.xN.sub.y layer as a function of the quantity qt is illustrated in FIG. 3. For a quantity qt equal to 0, the value for the acoustic impedance Z is equal to the value for the acoustic impedance Z of a layer of silicon oxide, this being on the order of 13.7*10.sup.6 Pa.Math.s/m. As the quantity qt increases, the acoustic impedance of the intermediate layer 106 increases continuously. For a value for quantity qt of between 0.5 and 0.7, the acoustic impedance Z becomes comparable to the acoustic impedance Z of silicon, which is between 19.4*10.sup.6 Pa.Math.s/m and 21.8*10.sup.6 Pa.Math.s/m, depending on the crystalline orientation of the silicon. For qt=1, the obtained acoustic impedance Z is that of Si.sub.3N.sub.4, which is on the order of 25.5*10.sup.6 Pa.Math.s/m. However, this value for the acoustic impedance Z depends on the deposition techniques employed.

[0047] Thus, by varying the quantity qt.sub.1 of the intermediate layer 106, a variation in the acoustic impedance value of the intermediate layer 106 can be obtained, a value that can vary between the acoustic impedance value of a layer of Si.sub.3N.sub.4 and that of a layer of silicon oxide. Starting from the values shown in FIG. 3, it is possible to set the value for the quantity qt as a function of the position in the thickness e.sub.1 of the SiO.sub.xN.sub.y layer.

[0048] On the basis of what is shown in FIG. 3, qt.sub.1(e.sub.1) is set at 0 in the intermediate layer 106 at the interface 112 with the dielectric layer 110. Thereafter, qt.sub.1 increases as a function of the thickness e.sub.1 until reaching a quantity qt.sub.1(e.sub.1=0)0.4, more particularly qt.sub.1(e.sub.1=0)=0.7 at the interface with the support substrate. The acoustic impedance of the intermediate layer 106 at the interface 108 with the support substrate 102 (e.sub.1=0) is thus on the order of the first acoustic impedance of the support substrate 102.

[0049] The intermediate layer 106 thus makes it possible to reduce the difference in acoustic impedance between the support substrate 102 and the dielectric layer 110 of silicon oxide by its acoustic impedance, which is between the impedance of the support substrate 102 and that of the dielectric layer 110.

[0050] In addition, the interface 112 between the dielectric layer 110 and the intermediate layer 106 is an interface that is free of nitrogen (N) and that comprises silicon oxide-silicon oxide bonds, which are known for being stable bonds that improve adhesion.

[0051] In addition, given that the intermediate layer 106 is a SiO.sub.xN.sub.y-based layer, the presence of nitrogen in the intermediate layer 106 makes it possible to reduce the diffusion of lithium or hydrogen into the support substrate 102.

[0052] The piezoelectric-on-insulator (POI) substrate 100 according to the present disclosure thus exhibits improved stability and also improved characteristics for the use thereof in surface acoustic wave devices (SAWs) such as sensors, filters or the like. Reducing the difference in acoustic impedance in the piezoelectric-on-insulator (POI) substrate 100 results in a reduction in undesirable modes in the desired frequency ranges for the operation of surface acoustic wave devices (SAWs).

[0053] FIG. 4 shows a variant of the first embodiment of the present disclosure. The sole difference between the POI substrate 100 and the POI substrate 200 of the variant is the presence of a trapping layer 116 between the support substrate 102 and the intermediate layer 106. All other characteristics of the POI substrate are the same as those described in FIG. 1. None of the characteristics common to the first embodiment employing the same reference number as above will be described again, but reference is made to their detailed description above.

[0054] The trapping layer 116 is in contact with the support substrate 102 at the interface 118 and is also in contact with the intermediate layer 106 at the interface 120. The trapping layer 116 is sandwiched between the support substrate 102 and the intermediate layer 106.

[0055] The trapping layer 116 is a layer based on polycrystalline or amorphous or porous silicon, having a thickness of between 200 nm and 5 m, more particularly between 500 nm and 2 m. The trapping layer 116 has a third acoustic impedance with a value of about 21*10.sup.6 Pa.Math.s/m, this value being close to the average acoustic impedance value for the three possible silicon orientations mentioned above.

[0056] In this variant, the value of the quantity qt.sub.1 of the variable composition of the silicon oxynitride SiO.sub.xN.sub.y layer 106 varies such that the acoustic impedance of the intermediate layer 106 at the interface 120 with the trapping layer 116 is on the order of the third acoustic impedance of the trapping layer 116.

[0057] The piezoelectric-on-insulator (POI) substrate 200 has the same advantages as the piezoelectric-on-insulator (POI) substrate 100 described in FIG. 1.

[0058] FIG. 5A is a schematic representation of a process for producing a piezoelectric-on-insulator (POI) substrate according to a second embodiment of the present disclosure to obtain a POI substrate as described above in FIGS. 1 and 4 according to the first embodiment of the present disclosure. Elements with the same reference numbers and the properties thereof will not be described again, but reference is made to their description above.

[0059] The process for producing a piezoelectric-on-insulator (POI) substrate 200 starts with step I) of providing a support substrate 102, in particular, a silicon-based substrate, more particularly a crystalline or polycrystalline silicon substrate.

[0060] According to the present disclosure, step II) involves the forming of the trapping layer 116 on the free surface 122 of the support substrate 102. The forming of the trapping layer 116 may be achieved by a thermal or plasma-assisted growth technique such as PECVD (plasma-enhanced chemical vapor deposition) or PVD (physical vapor deposition).

[0061] The trapping layer 116 formed on the support substrate 102 is a layer based on silicon, especially polycrystalline silicon. The thickness of the trapping layer 116 is between 200 nm and 5 m, more particularly between 500 nm and 2 m. The trapping layer 116 has a fourth acoustic impedance that may be the same as that of the support substrate 102 or it may be different.

[0062] In step III), the intermediate layer 106 is formed on the free surface 124 of the trapping layer 116.

[0063] The forming of the intermediate layer 106 may be achieved by a thermal or plasma-assisted growth technique such as LPCVD (low-pressure chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition).

[0064] The intermediate layer 106 is a layer based on silicon oxynitride SiO.sub.xN.sub.y. The thickness of the intermediate layer 106 is between 100 nm and 1000 nm, more particularly between 200 nm and 1000 nm.

[0065] To obtain the variable composition in the intermediate layer 106, the deposition parameters are varied during deposition so as to modify the amount of nitrogen and/or the amount of oxygen in the thickness of the deposited layer in a way that achieves the gradual variation in the composition of the deposited intermediate layer 106 necessary to obtain the desired acoustic impedance at the free upper surface 126 of the deposited intermediate layer 106, as explained above.

[0066] The variation in the composition of the deposited layer of silicon oxynitride SiO.sub.xN.sub.y is defined by qt=y/(y+x).

[0067] The variation in the quantity qti is a decreasing variation between the interface 108 with the support substrate 102 and the free upper surface 126 of the silicon oxynitride SiO.sub.xN.sub.y layer 106. The variation is a stepwise decrease or a linear decrease.

[0068] At the interface 118 with the support substrate 102, the quantity qt.sub.1 is at least equal to 0.4, more particularly the quantity qt.sub.1 is on the order of 0.7. The acoustic impedance of the intermediate layer 106 at the interface 118 with the support substrate 102 is thus on the order of the first acoustic impedance of the support substrate 102, more particularly it is the same.

[0069] At the free upper surface 126 of the intermediate layer 106, which is intended to contact another layer in a subsequent process step, the quantity qt.sub.1 is defined by the acoustic impedance value of the layer that is to be contacted with the free upper surface 126. [0070] In step IV), the piezoelectric substrate 128 is provided. [0071] In step V), the dielectric layer 110 is produced on the free surface 130 of the piezoelectric substrate 128. Before forming the dielectric layer 110, one or more steps of cleaning, brushing or polishing the free surface 130 of the piezoelectric substrate 128 can be carried out to eliminate the presence of particles and dust in order to thus obtain a cleaner free surface 130, which makes it possible to obtain a deposited dielectric layer 110 of better quality.

[0072] The forming of the dielectric layer 110 on the free surface 130 of the piezoelectric substrate 128 can be achieved by a thermal or plasma-assisted growth technique such as LPECVD at low pressure and/or low temperature. A thermal treatment may be carried out after deposition of the dielectric layer 110 in order to densify the dielectric layer 110.

[0073] According to one variant, surface-treatment steps on the free surface 130 of the piezoelectric substrate 128 may be carried out before the formation of the dielectric layer 110. Examples include a surface activation treatment such as a plasma treatment or an ozone-based treatment.

[0074] According to the present disclosure, the dielectric layer 110 is a layer of silicon oxide.

[0075] According to the present disclosure, the piezoelectric substrate 128 obtained after step V) is then joined to the support substrate 102 obtained in step III) during a step VI) of joining to form a support substrate-piezoelectric substrate assembly 132. The joining of the piezoelectric substrate 128 on the support substrate 102 is achieved by positioning the intermediate layer 106 in contact with the dielectric layer 110 of the piezoelectric substrate 128 such that the intermediate layer 106 is sandwiched between the dielectric layer 110 of the piezoelectric substrate 128 and the support substrate 102. The intermediate layer 106 is thus in direct contact with the dielectric layer 110 of the piezoelectric substrate 128 at the interface 112.

[0076] In this structure, the acoustic impedance of the intermediate layer 106 at the free upper surface 126 is on the order of the acoustic impedance of the dielectric layer 110 of silicon oxide. In addition, the bond between the substrates is created at an interface 112 that is essentially made of the same material on both sides of the interface 112.

[0077] Once the two substrates have been joined, a step (not illustrated) of thinning VII) of the piezoelectric substrate 128 may be carried out to obtain a thinner piezoelectric layer 104. For example, the thinning step may be carried out by grinding or by a step of forming a weakened zone in the piezoelectric substrate 128 in such a way as to delineate the piezoelectric layer 104 to be transferred onto the support substrate 102, and fracturing. This step of forming a weakened zone is carried out by implanting atomic or ionic species in the piezoelectric substrate 128. The atomic or ionic implantation may be carried out in such a way that the weakened zone is situated inside the piezoelectric substrate 128 and separates a piezoelectric layer 104 from the remainder of the piezoelectric substrate 128.

[0078] This is followed by the performance of a step of fracturing of the support substrate-piezoelectric substrate assembly 132 through an input of thermal and/or mechanical energy at the weakened zone of the piezoelectric substrate 128 so as to obtain a piezoelectric-on-insulator (POI) substrate 200 as illustrated in step VII) of FIG. 5A and in FIG. 4 that has a thinner piezoelectric layer 104 on a support substrate 102.

[0079] This method may also be applied to obtain the substrate of FIG. 1.

[0080] FIG. 5B is a schematic representation of a process for producing a piezoelectric-on-insulator (POI) substrate according to a first variant of the second embodiment of the present disclosure.

[0081] None of the characteristics common to the second embodiment employing the same reference number as above will be described again, but reference is made to their detailed description above.

[0082] The sole difference between this process and the one in FIG. 5A consists of the formation IIIc) of a dielectric layer 134 on the free surface of the intermediate layer 106 after step III) of FIG. 5A. The dielectric layer 134 is of the same material as the dielectric layer 110, i.e., silicon oxide. The dielectric layer 134 may be produced in the same way as the dielectric layer 110.

[0083] Thus, in the joining step VI), the dielectric layer 134 is contacted with the dielectric layer 110 of the piezoelectric substrate 128 at the interface 138. The assembly 140 is therefore created by molecular adhesion between the two dielectric layers 110 and 134, which are made of the same material, in this case silicon oxide. This achieves an improved bond between the substrates 102 and 128.

[0084] All other process steps in this variant are the same as the steps for the process according to the second embodiment described in FIG. 5A for obtaining the (POI) substrate 200.

[0085] FIG. 5C is a schematic representation of a process for producing a piezoelectric-on-insulator (POI) substrate according to a second variant of the second embodiment of the present disclosure.

[0086] None of the characteristics common to the second embodiment and variants thereof employing the same reference number as above will be described again, but reference is made to their detailed description above.

[0087] The sole difference between this process and the one in FIG. 5A consists of the separation of the intermediate layer 106 into two parts. Step III) of FIG. 5A is replaced by two steps, IIIa) and IIIb). A first intermediate layer 144 is formed on the trapping layer 116 in step IIIa). A second intermediate layer 150 is produced on the dielectric layer 110 in step IIIb).

[0088] For the first intermediate layer 144 formed on the support substrate 102 and therefore on the trapping layer 116, the first intermediate layer 144 is deposited in such a way in step IIIa) that the quantity qt.sub.2 of the variable composition of the first silicon oxynitride SiO.sub.xN.sub.y layer 144 varies along its thickness, where qt.sub.2(0) is at least 0.4 at the interface 146 with the trap-rich layer 116 of the support substrate 102.

[0089] The first intermediate layer 144 is deposited such that the quantity qt.sub.2 of the first silicon oxynitride SiO.sub.xN.sub.y layer 144 varies in a decreasing manner along the thickness of the first intermediate layer 144.

[0090] At the free surface 148 of the first intermediate layer 144, the quantity qt.sub.2 is set at the same value as that of the layer to be contacted in step VII). In this case, for example, qt.sub.2(e.sub.2)=0.2.

[0091] For the second intermediate layer 150 formed on the piezoelectric substrate 128, the second intermediate layer 150 is deposited in such a way in step IIIb) that the quantity qt.sub.3 of the variable composition of the second silicon oxynitride SiO.sub.xN.sub.y layer 150 varies along its thickness, where qt.sub.3 (e.sub.3=0) is 0 at its interface 152 with the dielectric layer 110.

[0092] The second intermediate layer 150 is deposited such that the quantity qt.sub.3 of the second silicon oxynitride SiO.sub.xN.sub.y layer 150 varies in an increasing manner along the thickness e.sub.3 of the intermediate layer 150.

[0093] At the free surface 154 of the second intermediate layer 150, the quantity qt.sub.3 is the same as the quantity qt.sub.2 at the free surface 148 of the first intermediate layer 144. In this case, therefore, qt.sub.3(e.sub.3)=0.2.

[0094] Thus, in the joining step VI), the first intermediate layer 144 of the support substrate 102 is contacted with the second intermediate layer 150 of the piezoelectric substrate 128.

[0095] As in the other processes described in relation to FIGS. 5A and 5B, the acoustic impedance varies across the first and second intermediate layers 144 and 150 between the value of the trapping layer 116 and the value of the dielectric layer 110.

[0096] The assembly 156 is created by molecular adhesion between the two substrates 102 and 128 at the interface 152 between the first intermediate layer 144 and the second intermediate layer 150. The assembly 156 is therefore created by molecular adhesion between the two intermediate layers 144 and 150, which have essentially the same material at the interface, in this case the silicon oxynitride SiO.sub.xN.sub.y layer where qt=0.2. This achieves an improved bond between the substrates 102 and 128.

[0097] All other process steps in this variant are the same as the steps for the process according to the second embodiment described in FIG. 5A for obtaining the (POI) substrate 200.

[0098] The process according to the second embodiment may also be used to produce the piezoelectric-on-insulator (POI) substrate 100 according to FIG. 1 without the presence of a trap-rich layer 116 on the support substrate 102.

[0099] The embodiments described are simply possible configurations and it should be kept in mind that the individual characteristics of the different embodiments can be combined with one another or provided independently of one another.