Reference voltage circuit and electronic apparatus with proportional and complementary voltage generation and temperature characteristic adjustment circuit

Abstract

A reference voltage circuit (1) includes a PTAT voltage generation circuit (20) that generates a voltage with a positive temperature coefficient, a CTAT voltage generation circuit (10) that generates a voltage with a negative temperature coefficient, and a temperature characteristic adjustment circuit (30) that generates a voltage for adjusting temperature characteristics. The reference voltage circuit outputs a reference voltage (VOUT) formed by calculation based on the output of the PTAT voltage generation circuit, output of the CTAT voltage generation circuit, and output of the temperature characteristic adjustment circuit.

Claims

1. A reference voltage circuit comprising: a Proportional To Absolute Temperature (PTAT) voltage generation circuit that generates a voltage with a positive temperature coefficient; a Complementary To Absolute Temperature (CTAT) voltage generation circuit that generates a voltage with a negative temperature coefficient; and a temperature characteristic adjustment circuit that generates a voltage to adjust a temperature characteristic, wherein the reference voltage circuit outputs a reference voltage formed by calculation from an output of the PTAT voltage generation circuit, an output of the CTAT voltage generation circuit, and an output of the temperature characteristic adjustment circuit.

2. The reference voltage circuit according to claim 1, wherein the temperature characteristic adjustment circuit is configured such that a voltage difference between an input side and an output side of the temperature characteristic adjustment circuit is a gate voltage difference between paired MOSFETs, and a current density ratio of drain currents in one MOSFET arranged on the input side and an other MOSFET arranged on the output side is adjustable.

3. The reference voltage circuit according to claim 2, wherein a plurality of MOSFETs selectable as the one MOSFET or a plurality of MOSFETs selectable as the other MOSFET, or a plurality of MOSFETs selectable as the one MOSFET and a plurality of MOSFETs selectable as the other MOSFET are arranged.

4. The reference voltage circuit according to claim 3, wherein the plurality of MOSFETs are arranged in parallel.

5. The reference voltage circuit according to claim 4, wherein the plurality of MOSFETs have a same W/L ratio.

6. The reference voltage circuit according to claim 4, wherein the plurality of MOSFETs have different W/L ratios.

7. The reference voltage circuit according to claim 3, wherein the plurality of MOSFETs are arranged in series.

8. The reference voltage circuit according to claim 7, wherein the plurality of MOSFETs have a same W/L ratio.

9. The reference voltage circuit according to claim 7, wherein the plurality of MOSFETs have different W/L ratios.

10. The reference voltage circuit according to claim 3, wherein the plurality of MOSFETs of the temperature characteristic adjustment circuit operates in a subthreshold region.

11. The reference voltage circuit according to claim 2, wherein the temperature characteristic adjustment circuit includes a current mirror circuit for passing a drain current through each of the paired MOSFETs, and the current mirror circuit is configured such that a mirror ratio adjustable.

12. The reference voltage circuit according to claim 11, wherein a plurality of MOSFETs capable of being selected as a MOSFET that passes a mirror current are arranged in the current mirror circuit.

13. The reference voltage circuit according to claim 1, wherein the PTAT voltage generation circuit is configured by connecting structures each for extracting a gate voltage difference between two paired MOSFETs in multiple stages.

14. The reference voltage circuit according to claim 13, wherein the two paired MOSFETs of the PTAT voltage generation circuit operate in a subthreshold region.

15. The reference voltage circuit according to claim 1, wherein the CTAT voltage generation circuit is configured to output a base-emitter voltage of a bipolar transistor.

16. An electronic apparatus comprising: a reference voltage circuit including a Proportional To Absolute Temperature (PTAT) voltage generation circuit that generates a voltage with a positive temperature coefficient, a Complementary To Absolute Temperature (CTAT) voltage generation circuit that generates a voltage with a negative temperature coefficient, and a temperature characteristic adjustment circuit that generates a voltage to adjust a temperature characteristic, wherein the reference voltage circuit outputs a reference voltage formed by calculation from an output of the PTAT voltage generation circuit, an output of the CTAT voltage generation circuit, and an output of the temperature characteristic adjustment circuit.

17. The electronic apparatus according to claim 16, wherein the temperature characteristic adjustment circuit is configured such that a voltage difference between an input side and an output side of the temperature characteristic adjustment circuit is a gate voltage difference between paired MOSFETs, and a current density ratio of drain currents in one MOSFET arranged on the input side and an other MOSFET arranged on the output side is adjustable.

18. The electronic apparatus according to claim 17, wherein a plurality of MOSFETs selectable as the one MOSFET or a plurality of MOSFETs selectable as the other MOSFET, or a plurality of MOSFETs selectable as the one MOSFET and a plurality of MOSFETs selectable as the other MOSFET are arranged.

19. The electronic apparatus according to claim 18, wherein the plurality of MOSFETs are arranged in parallel.

20. The electronic apparatus according to claim 19, wherein the plurality of MOSFETs have a same W/L ratio.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic principle diagram of a reference voltage circuit according to a first embodiment.

(2) FIG. 2 is a circuit diagram of the reference voltage circuit according to the first embodiment.

(3) FIG. 3 is a schematic principle diagram of a temperature characteristic adjustment circuit.

(4) FIG. 4 is a schematic principle diagram of a first example of the temperature characteristic adjustment circuit.

(5) FIG. 5 is a first configuration example of the first example of the temperature characteristic adjustment circuit.

(6) FIG. 6 is a second configuration example of the first example of the temperature characteristic adjustment circuit.

(7) FIG. 7 is a schematic principle diagram of a second example of the temperature characteristic adjustment circuit.

(8) FIG. 8 is a configuration example of the second example of the temperature characteristic adjustment circuit.

(9) FIG. 9 is a schematic principle diagram of the reference voltage circuit.

(10) FIG. 10 is a circuit diagram of the reference voltage circuit having a configuration causing MOSFETs to operate in a subthreshold region.

DESCRIPTION OF EMBODIMENTS

(11) The present disclosure will be described below on the basis of embodiments with reference to the drawings. The present disclosure is not limited to the embodiments, and various numerical values and materials in the embodiments are examples. In the following description, the same reference signs will be used for the same elements or elements having the same function, and duplicate description will be omitted. Incidentally, the description will be given in the following order.

(12) 1. Description of reference voltage circuit, and electronic apparatus, in general related to present disclosure

(13) 2. First Embodiment

(14) 3. Others

Description of Reference Voltage Circuit, and Electronic Apparatus, in General Related to Present Disclosure

(15) In the reference voltage circuit according to the present disclosure, or the reference voltage circuit used in the electronic apparatus according to the present disclosure (hereinafter, these may be simply referred to as “reference voltage circuit of the present disclosure”), the mode can be applied in which the temperature characteristic adjustment circuit is configured so that the voltage difference between the input side and the output side becomes the gate voltage difference of a pair of MOSFETs, and the current density ratio of the drain currents in one MOSFET arranged on the input side and the other MOSFET arranged on the output side is adjustable.

(16) In this case, a configuration can be applied in which a plurality of MOSFETs that can be selected as one MOSFET and/or a plurality of MOSFETs that can be selected as the other MOSFET are arranged. Note that, from the viewpoint of increasing the degree of freedom of adjustment, it is preferable for each of the one MOSFET and the other MOSFET to have a configuration in which a plurality of selectable MOSFETs is arranged.

(17) In this case, the plurality of MOSFETs can be arranged in parallel. Then, a plurality of MOSFETs having the same W/L ratio may also be arranged. In this case, for example, it is sufficient if the number of MOSFETs to be selected is adjusted. The MOSFETs can be selected, for example, by trimming a semiconductor element on which a reference voltage circuit is formed.

(18) Alternatively, a plurality of MOSFETs having different W/L ratios can also be arranged. In this case, it is sufficient if a MOSFET having a desired W/L ratio is selected alone, or a plurality of MOSFETs may be selected so that the W/L ratio of the MOSFET group becomes a desired value.

(19) Alternatively, a plurality of MOSFETs may also be arranged in series. Also in this case, a plurality of MOSFETs having the same W/L ratio may be arranged, or a plurality of MOSFETs having different W/L ratios may also be arranged.

(20) In the reference voltage circuit of the present disclosure including the various preferable configurations described above, the MOSFET of the temperature characteristic adjustment circuit can be configured to operate in the subthreshold region.

(21) The mode can be applied in which the reference voltage circuit of the present disclosure having the various preferable configurations described above includes a current mirror circuit for passing a drain current through each of the paired MOSFETs, and the current mirror circuit is configured so that the mirror ratio is adjustable. In this case, the current mirror circuit may be configured such that a plurality of MOSFETs that can be selected as MOSFETs that pass the mirror current is arranged.

(22) In the reference voltage circuit of the present disclosure including the various preferable configurations described above, the mode can be applied in which the PTAT voltage generation circuit is configured by connecting structures each for extracting the gate voltage difference between two paired MOSFETs in multiple stages. In this case, the MOSFETs of the PTAT voltage generation circuit can be configured to operate in the subthreshold region.

(23) In the reference voltage circuit of the present disclosure including the various preferred configurations described above, the mode can be applied in which the CTAT voltage generation circuit is configured to output the base-emitter voltage of a bipolar transistor.

(24) The reference voltage circuit of the present disclosure is suitable for use in portable electronic apparatuses and the like. As a suitable IC using the reference voltage circuit of the present disclosure, 1. reset IC, 2. power-saving real-time clock IC, and 3. power supply IC can be exemplified.

(25) The satisfaction of the various conditions illustrated in the present specification includes not only cases of being strictly satisfied but also cases of being substantially satisfied. The presence of various design or manufacturing variations is acceptable.

First Embodiment

(26) The first embodiment relates to a reference voltage circuit according to the present disclosure.

(27) FIG. 1 is a schematic principle diagram of the reference voltage circuit according to the first embodiment.

(28) The reference voltage circuit 1 according to the first embodiment includes

(29) a PTAT voltage generation circuit 20 that generates a voltage with a positive temperature coefficient,

(30) a CTAT voltage generation circuit 10 that generates a voltage with a negative temperature coefficient,

(31) a temperature characteristic adjustment circuit 30 that generates a voltage for adjusting a temperature characteristic.

(32) Then, the reference voltage formed by calculation from the output of the PTAT voltage generation circuit 20, the output of the CTAT voltage generation circuit 10, and the output of the temperature characteristic adjustment circuit 30 is output. To be more specific, a reference voltage obtained by adding the voltage generated by the PTAT voltage generation circuit 20, the voltage generated by the CTAT voltage generation circuit 10, and the voltage generated by the temperature characteristic adjustment circuit 30 is output. The reference voltage circuit 1 basically has a configuration in which a voltage generated for temperature characteristic adjustment is added to the output voltage of the reference voltage circuit 1 illustrated in FIG. 9. Note that the voltage generated by the PTAT voltage generation circuit 20 and the voltage generated by the CTAT voltage generation circuit 10 may be added after being multiplied by predetermined coefficients, if necessary.

(33) FIG. 2 is a circuit diagram of a reference voltage circuit according to the first embodiment.

(34) A specific configuration example of the reference voltage circuit 1 will be described. The CTAT voltage generation circuit 10 includes a circuit in which the base and the collector of the PNP transistor Q are grounded. The transistor Q is configured so that a mirror current flows from the transistor M.sub.P, and the base-emitter voltage V.sub.BE is a CTAT voltage (V.sub.CTAT) having a negative temperature coefficient.

(35) The PTAT voltage generation circuit 20 has a configuration similar to the PTAT voltage generation circuit 20 in the reference voltage circuit 9 illustrated in FIG. 10, and is configured by connecting structures each for extracting the gate voltage difference between two paired MOSFETs in multiple stages. The MOSFETs of the PTAT voltage generation circuit 20 operate in the subthreshold region. The PTAT voltage (V.sub.PTAT) generated by the PTAT voltage generation circuit 20 is represented by the second term of the above-mentioned equation (1).

(36) Subsequently, the temperature characteristic adjustment circuit 30 will be described.

(37) FIG. 3 is a schematic principle diagram of the temperature characteristic adjustment circuit.

(38) The temperature characteristic adjustment circuit 30 is configured such that the voltage difference between the input side and the output side becomes the gate voltage difference between a pair of MOSFETs. The MOSFET of the temperature characteristic adjustment circuit is configured to operate in the subthreshold region. Then, the current density ratio of the drain currents in one MOSFET arranged on the input side and the other MOSFET arranged on the output side is adjustable.

(39) The W/L ratio of the input side MOSFET (represented by the reference sign T.sub.1) of the two MOSFETs is represented by W.sub.1/L.sub.1, and the flowing drain current is represented by the reference sign I.sub.1. Further, the W/L ratio of the MOSFET on the output side (represented by the reference sign T.sub.2) is represented by W.sub.2/L.sub.2, and the flowing drain current is represented by the reference sign I.sub.2.

(40) The source sides of two MOSFETs (T.sub.1, T.sub.2) are connected to each other, and the sum of the source currents of the two MOSFETs (T.sub.1, T.sub.2) is I.sub.1+I.sub.2. At this time, the gate voltage difference ΔV.sub.GS between the two MOSFETs (T.sub.1, T.sub.2) is represented by the following equation (2).

(41) $\begin{matrix} Δ V_{GS} = η \frac{k_{B}}{q} T t n (\frac{I_{2}}{I_{1}} \frac{W_{1} / L_{1}}{W_{2} / L_{2}}) & (2) \end{matrix}$

(42) Here, in the case where the current densities of the two MOSFETs (T.sub.1, T.sub.2) are equal, in other words, in the case where the following equation (3) holds, the gate voltage difference ΔV.sub.GS is zero volt.

(43) $\begin{matrix} \frac{I_{1}}{W_{1} / L_{1}} = \frac{I_{2}}{W_{2} / L_{2}} & (3) \end{matrix}$

(44) Near the condition of the above-mentioned equation (3), the argument of the logarithmic function indicated in the above-mentioned equation (2) is approximately 1. Accordingly, the rate of change of the gate voltage difference with respect to the change of the current density ratio is expressed by the following equation (4).

(45) $\begin{matrix} {{\frac{d Δ V_{GS}}{d (\frac{I_{2} W_{1} / L_{1}}{I_{1} W_{2} / L_{2}})} .Math.}_{(\frac{I_{2} W_{1} / L_{1}}{I_{1} W_{2} / L_{2}}) = 1} = \frac{η \frac{k_{B}}{q} T}{(\frac{I_{2} W_{1} / L_{1}}{I_{1} W_{2} / L_{2}})} .Math.}_{(\frac{I_{2} W_{1} / L_{1})}{I_{1} W_{2} / L_{2}}) = 1} \approx η \frac{k_{B}}{q} T & (4) \end{matrix}$

(46) Here, for example, assuming that the slope factor η=1.5 and the temperature T=300 K, the right side of the equation (4) is expressed as the following equation (5).

(47) $\begin{matrix} η \frac{k_{B}}{q} T \approx 38 m V & (5) \end{matrix}$

(48) In this way, the temperature characteristic adjustment circuit 30 can generate a voltage (V.sub.COMP, illustrated in FIG. 1) that changes with sufficient sensitivity to temperature. Further, the degree can be adjusted by adjusting the W/L ratios of the two MOSFETs (T.sub.1, T.sub.2) and the ratio of the flowing drain currents.

(49) FIG. 4 is a schematic principle diagram of the first example of the temperature characteristic adjustment circuit.

(50) A temperature characteristic adjustment circuit 30A is configured to adjust the W/L ratios (M:N) of the MOSFETs (T.sub.1, T.sub.2) by using the drain currents of the two paired MOSFETs (T.sub.1, T.sub.2) as the same currents. The temperature characteristic adjustment circuit 30A includes a current mirror circuit for passing a drain current through each of the paired MOSFETs. A transistor T.sub.3 and a transistor T.sub.4 constituting the current mirror circuit have the same W/L ratio.

(51) Hereinafter, various configuration examples will be described in detail with reference to the drawings. FIG. 5 is a first configuration example of the first example of the temperature characteristic adjustment circuit.

(52) In a temperature characteristic adjustment circuit 30A.sub.1, a plurality of MOSFETs that can be selected as one MOSFET and a plurality of MOSFETs that can be selected as the other MOSFET are arranged. To be more specific, the plurality of MOSFETs is arranged in parallel. Transistors T.sub.1_1 to T.sub.1_J are provided to be selectable as one MOSFET on the input side. Further, transistors T.sub.2_1 to T.sub.2_K are provided to be selectable as the other MOSFET on the output side.

(53) In this configuration, MOSFETs having the same W/L ratio can be arranged as the transistors T.sub.1_1 to T.sub.1_J and the transistors T.sub.2_1 to T.sub.2_K. In this case, for example, it is sufficient if the number of MOSFETs to be selected is adjusted. The MOSFETs can be selected, for example, by trimming the semiconductor element on which the reference voltage circuit 1 is formed.

(54) Alternatively, in this configuration, MOSFETs having different W/L ratios may also be arranged as the transistors T.sub.1_1 to T.sub.1_J or the transistors T.sub.2_1 to T.sub.2_K. In this case, it is sufficient if a MOSFET having a desired W/L ratio is selected alone, or a plurality of MOSFETs is selected so that the W/L ratio as the MOSFET group becomes a desired value.

(55) It should be noted that in the temperature characteristic adjustment circuit 30A.sub.1, it has been assumed that a plurality of MOSFETs that can be selected as one MOSFET and a plurality of MOSFETs that can be selected as the other MOSFET are arranged, but a configuration in which a plurality of MOSFETs is arranged for only one of these can also be used. In this case, although the degree of freedom of adjustment is reduced, the number of elements can be reduced, so that the occupancy area of the circuit can be reduced.

(56) FIG. 6 is a second configuration example of the first example of the temperature characteristic adjustment circuit.

(57) Also in a temperature characteristic adjustment circuit 30A.sub.2, a plurality of MOSFETs that can be selected as one MOSFET and a plurality of MOSFETs that can be selected as the other MOSFET are arranged. Note that the plurality of MOSFETs is arranged in series. The transistors T.sub.1_1 to T.sub.1_J are provided to be selectable as one MOSFET on the input side. Further, the transistors T.sub.2_1 to T.sub.2_K are provided to be selectable as the other MOSFET on the output side.

(58) In this configuration, adjustment can be made depending on whether the source/drain regions of the transistors T.sub.1_2 to T.sub.1_J or the transistors T.sub.2_2 to T.sub.2_K are short-circuited. Also in this case, a plurality of MOSFETs having the same W/L ratio may be arranged, or a plurality of MOSFETs having different W/L ratios may be arranged.

(59) The first example of the temperature characteristic adjustment circuit has been described above. Subsequently, a second example of the temperature characteristic adjustment circuit will be described.

(60) FIG. 7 is a schematic principle diagram of a second example of the temperature characteristic adjustment circuit.

(61) A temperature characteristic adjustment circuit 30B of the second example is configured so that the W/L ratios of the two paired MOSFETs (T.sub.1, T.sub.2) are the same (1:1), and the ratio of the flowing drain current is adjusted. The drain current ratio is adjusted by changing the mirror ratio (M:N) of the current mirror circuit having the transistors T.sub.3 and T.sub.4.

(62) FIG. 8 is a configuration example of the second example of the temperature characteristic adjustment circuit.

(63) In a temperature characteristic adjustment circuit 30B.sub.1, a plurality of MOSFETs (reference signs T.sub.3_1 to T.sub.3_J and reference signs T.sub.4_1 to T.sub.4_K) that can be selected as MOSFETs that pass the mirror current are arranged in the current mirror circuit. The ratio of the drain currents flowing through the transistor T.sub.1 and the transistor T.sub.2 can be adjusted by appropriately selecting MOSFETs. Also in this case, a plurality of MOSFETs having the same W/L ratio may be arranged, or a plurality of MOSFETs having different W/L ratios may be arranged. The MOSFETs can be selected, for example, by trimming the semiconductor element on which the reference voltage circuit 1 is formed.

(64) Although the embodiments of the present disclosure have been specifically described above, the present invention is not limited to the above-described embodiments of the present disclosure, and various modifications based on the technical idea of the present invention can be applied.

(65) The reference voltage circuit of the present disclosure described above includes a PTAT voltage generation circuit that generates a voltage having a positive temperature coefficient, a CTAT voltage generation circuit that generates a voltage having a negative temperature coefficient, and a temperature characteristic adjustment circuit for generating a voltage for adjusting the temperature characteristics, and outputs a reference voltage formed by calculation from the output of the PTAT voltage generation circuit, the output of the CTAT voltage generation circuit, and the output of the temperature characteristic adjustment circuit. By using the temperature characteristic adjustment circuit, a wide adjustment range can be set, which can make fine adjustment.

(66) It should be noted that the technology of the present disclosure can also have the following configurations.

(67) [A1]

(68) A reference voltage circuit including:

(69) a PTAT voltage generation circuit that generates a voltage with a positive temperature coefficient;

(70) a CTAT voltage generation circuit that generates a voltage with a negative temperature coefficient; and

(71) a temperature characteristic adjustment circuit that generates a voltage to adjust a temperature characteristic, in which

(72) the reference voltage circuit outputs a reference voltage formed by calculation from the output of the PTAT voltage generation circuit, the output of the CTAT voltage generation circuit, and the output of the temperature characteristic adjustment circuit.

(73) [A2]

(74) The reference voltage circuit described in the above item [A1] in which

(75) the temperature characteristic adjustment circuit is configured such that a voltage difference between an input side and an output side of the temperature characteristic adjustment circuit is a gate voltage difference between paired MOSFETs, and

(76) a current density ratio of drain currents in one MOSFET arranged on the input side and the other MOSFET arranged on the output side is adjustable.

(77) [A3]

(78) The reference voltage circuit described in the above item [A2], in which

(79) a plurality of MOSFETs capable of being selected as the one MOSFET or a plurality of MOSFETs capable of being selected as the other MOSFET, or a plurality of MOSFETs capable of being selected as the one MOSFET and a plurality of MOSFETs capable of being selected as the other MOSFET are arranged.

(80) [A4]

(81) The reference voltage circuit described in the above item [A3], in which

(82) the plurality of MOSFETs is arranged in parallel.

(83) [A5]

(84) The reference voltage circuit described in the above item [A4], in which

(85) the plurality of MOSFETs with the same W/L ratio is arranged.

(86) [A6]

(87) The reference voltage circuit described in the above item [A5], in which

(88) the plurality of MOSFETs with different W/L ratios is arranged.

(89) [A7]

(90) The reference voltage circuit described in the above item [A4], in which

(91) the plurality of MOSFETs is arranged in series.

(92) [A8]

(93) The reference voltage circuit described in the above item [A7], in which

(94) the plurality of MOSFETs with the same W/L ratio is arranged.

(95) [A9]

(96) The reference voltage circuit described in the above item [A7], in which

(97) the plurality of MOSFETs with different W/L ratios is arranged.

(98) [A10]

(99) The reference voltage circuit described in the above items [A2] to [A9], in which

(100) the plurality of MOSFETs of the temperature characteristic adjustment circuit operates in a subthreshold region.

(101) [A11]

(102) The reference voltage circuit described in the above item [A2], in which

(103) the temperature characteristic adjustment circuit includes a current mirror circuit for passing a drain current through each of the paired MOSFETs, and

(104) the current mirror circuit is configured so that the mirror ratio capable of being adjusted.

(105) [A12]

(106) The reference voltage circuit described in the above item [A11], in which

(107) a plurality of MOSFETs capable of being selected as a MOSFET that passes a mirror current is arranged in the current mirror circuit.

(108) [A13]

(109) The reference voltage circuit described in any one of the above items [A1] to [A12], in which

(110) the PTAT voltage generation circuit is configured by connecting structures each for extracting the gate voltage difference between two paired MOSFETs in multiple stages.

(111) [A14]

(112) The reference voltage circuit described in the above item [A13], in which

(113) the two paired MOSFETs of the PTAT voltage generation circuit operate in a subthreshold region.

(114) [A15]

(115) The reference voltage circuit described in any one of the above items [A1] to [A14], in which

(116) the CTAT voltage generation circuit is configured to output a base-emitter voltage of a bipolar transistor.

(117) [B1]

(118) An electronic apparatus including:

(119) a reference voltage circuit including a PTAT voltage generation circuit that generates a voltage with a positive temperature coefficient, a CTAT voltage generation circuit that generates a voltage with a negative temperature coefficient, and a temperature characteristic adjustment circuit that generates a voltage to adjust a temperature characteristic, in which

(120) the reference voltage circuit outputs a reference voltage formed by calculation from an output of the PTAT voltage generation circuit, an output of the CTAT voltage generation circuit, and the output of an temperature characteristic adjustment circuit.

(121) [B2]

(122) The electronic apparatus described in the above item [B1], in which

(123) the temperature characteristic adjustment circuit is configured such that a voltage difference between an input side and an output side of the temperature characteristic adjustment circuit is a gate voltage difference between paired MOSFETs, and

(124) a current density ratio of drain currents in one MOSFET arranged on the input side and the other MOSFET arranged on the output side is adjustable.

(125) [B3]

(126) The electronic apparatus described in the above item [B2], in which

(127) a plurality of MOSFETs capable of being selected as the one MOSFET or a plurality of MOSFETs capable of being selected as the other MOSFET, or a plurality of MOSFETs capable of being selected as the one MOSFET and a plurality of MOSFETs capable of being selected as the other MOSFET are arranged.

(128) [B4]

(129) The electronic apparatus described in the above item [B3], in which

(130) the plurality of MOSFETs is arranged in parallel.

(131) [B5]

(132) The electronic apparatus described in the above item [B4], in which

(133) the plurality of MOSFETs with the same W/L ratio is arranged.

(134) [B6]

(135) The electronic apparatus described in the above item [B5], in which

(136) the plurality of MOSFETs with different W/L ratios is arranged.

(137) [B7]

(138) The electronic apparatus described in the above item [B4], in which

(139) the plurality of MOSFETs is arranged in series.

(140) [B8]

(141) The electronic apparatus described in the above item [B7], in which

(142) the plurality of MOSFETs with the same W/L ratio is arranged.

(143) [B9]

(144) The electronic apparatus described in the above item [B7], in which

(145) the plurality of MOSFETs with different W/L ratios is arranged.

(146) [B10]

(147) The electronic apparatus described in the above items [B2] to [B9], in which

(148) the plurality of MOSFETs of the temperature characteristic adjustment circuit operates in a subthreshold region.

(149) [B11]

(150) The electronic apparatus described in the above item [B2], in which

(151) the temperature characteristic adjustment circuit includes a current mirror circuit for passing a drain current through each of the paired MOSFETs, and

(152) the current mirror circuit is configured so that the mirror ratio capable of being adjusted.

(153) [B12]

(154) The electronic apparatus described in the above item [B11], in which

(155) a plurality of MOSFETs capable of being selected as a MOSFET that passes a mirror current is arranged in the current mirror circuit.

(156) [B13]

(157) The electronic apparatus described in any one of the above items [B1] to [B12], in which

(158) the PTAT voltage generation circuit is configured by connecting structures each for extracting the gate voltage difference between two paired MOSFETs in multiple stages.

(159) [B14]

(160) The electronic apparatus described in the above item [B13], in which

(161) the two paired MOSFETs of the PTAT voltage generation circuit operate in a subthreshold region.

(162) [B15]

(163) The electronic apparatus described in any one of the above items [B1] to [B14], in which

(164) the CTAT voltage generation circuit is configured to output a base-emitter voltage of a bipolar transistor.

REFERENCE SIGNS LIST

(165) 1, 1A, 9, 9A . . . Reference voltage circuit, 10 . . . CTAT voltage generation circuit, 20 . . . PTAT voltage generation circuit, 30, 30A, 30A.sub.1, 30A.sub.2, 30B, 30B.sub.1 . . . Temperature characteristic adjustment circuit, Q . . . PNP bipolar transistor, M.sub.1 to M.sub.10, M.sub.1 to M.sub.2J . . . MOSFET group constituting PTAT voltage generation circuit, M.sub.P . . . MOSFET that carries mirror current, M.sub.N . . . MOSFET that acts as load resistor, T.sub.1, T.sub.1_1 to T.sub.1_J . . . One MOSFET located on input side of temperature characteristic adjustment circuit, T.sub.2, T.sub.2_i to T.sub.2_K . . . Other MOSFET located on output side of temperature characteristic adjustment circuit, T.sub.3, T.sub.3_1 to T.sub.3_J, T.sub.4, T.sub.4_1 to T.sub.4_K . . . MOSFETs that constitute current mirror circuit of temperature characteristic adjustment circuit

Reference voltage circuit and electronic apparatus with proportional and complementary voltage generation and temperature characteristic adjustment circuit

Assignee

Inventors

Cpc classification

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G05F3/20

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G05F3/245

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G05F3/262

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G05F1/567

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G05F3/267

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G05F1/468

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International classification

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G05F1/46

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G05F1/567

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G05F3/24

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Abstract

Claims

Description