INVERTER AND BOOTSTRAP INVERTER HAVING IMPROVED OUTPUT CHARACTERISTICS

Abstract

The present invention relates to an inverter comprising: a first load transistor which has gate and drain electrodes connected to a power voltage (VDD) terminal; a second load transistor which has gate and drain electrodes connected to a source electrode of the first load transistor and has a source electrode connected to an output terminal; a driving transistor which has a drain electrode connected to the source electrode of the second load transistor to form the output terminal, has a gate electrode connected to an input (Vin) terminal, and has a source electrode connected to a ground (GND) terminal; and a control transistor which has a drain electrode connected to the source electrode of the first load transistor, has a gate electrode connected to the input (Vin) terminal, and has a source electrode connected to the ground (GND) terminal.

Claims

1. An inverter comprising: a first load transistor having a gate electrode and a drain electrode that are connected to a power voltage (VDD) terminal; a second load transistor having a gate electrode and a drain electrode that are connected to a source electrode of the first load transistor, the second load transistor having a source electrode connected to an output terminal; a driving transistor having a drain electrode connected to the source electrode of the second load transistor such that the output terminal is formed, the driving transistor having a gate electrode connected to an input (Vin) terminal and having a source electrode connected to a ground (GND) terminal; and a control transistor having a drain electrode connected to the source electrode of the first load transistor, having a gate electrode connected to the input (Vin) terminal, and having a source electrode connected to the ground (GND) terminal.

2. The inverter of claim 1, wherein, when the gate electrode of the control transistor is turned on, the source electrode of the first load transistor is connected to the ground (GND) terminal, so that a voltage of a node (P) to which the drain electrode of the second load transistor connected to the output terminal and the source electrode of the first load transistor are connected becomes 0V.

3. A bootstrap inverter comprising: a first load transistor having a drain electrode connected to a power voltage (VDD) terminal and having a gate electrode connected to a gate electrode of a second load transistor; the second load transistor having a drain electrode connected to a source electrode of the first load transistor and having a source electrode of the second load transistor connected to an output terminal; a bootstrap transistor having a gate electrode and a drain electrode connected to the power voltage (VDD) terminal and having a source electrode connected to the gate electrode of the second load transistor; a driving transistor having a drain electrode connected to the source electrode of the second load transistor such that the output terminal is formed, the driving transistor having a gate electrode connected to an input (Vin) terminal and having a source electrode connected to a ground (GND) terminal; and a control transistor having a drain electrode connected to the source electrode of the first load transistor, having a gate electrode connected to the input (Vin) terminal, and having a source electrode connected to the ground (GND) terminal.

4. The bootstrap inverter of claim 3, further comprising a capacitor having a first end connected to the source electrode of the bootstrap transistor and having a second end connected to the output terminal.

Description

DESCRIPTION OF DRAWINGS

[0017] FIG. 1 is a view illustrating a circuit diagram of a CMOS inverter.

[0018] FIG. 2 is a graph showing an input voltage and an output voltage when the input voltage of the inverter in FIG. 1 is increased from 0V to VDD that is a power voltage.

[0019] FIG. 3 is an example of an inverter formed of an N-channel Enhancement-type transistor.

[0020] FIG. 4 is a view illustrating a circuit diagram of a bootstrap inverter.

[0021] FIG. 5 is a view illustrating a circuit diagram of an inverter according to an embodiment of the present disclosure.

[0022] FIG. 6 is a view illustrating an operation of an input 0 and output 1 logic of the inverter in FIG. 5.

[0023] FIG. 7 is a view illustrating an operation of an input 1 and output 0 logic of the inverter in FIG. 5.

[0024] FIG. 8 is view illustrating a circuit diagram of a bootstrap inverter according to another embodiment of the present disclosure.

[0025] FIG. 9 is a view illustrating an operation of an input 0 and output 1 logic of the inverter in FIG. 8.

[0026] FIG. 10 is a view illustrating an operation of an input 1 and output 0 logic of the inverter in FIG. 8.

MODE FOR INVENTION

[0027] Hereinafter, the present disclosure will be described in detail with reference to the contents described in the accompanying drawings. However, the present disclosure is not limited or restricted by exemplary embodiments. Same reference numerals presented in each drawing represent members that perform substantially the same function.

[0028] Objectives and effects of the present disclosure may be naturally understood or more clearly understood according to the following description, and the objectives and the effects of the present disclosure are not limited to the following description. In addition, in describing the present disclosure, when it is determined that a detailed description of a known technology related to the present disclosure may unnecessarily obscure the subject matter of the present disclosure, the detailed description will be omitted.

[0029] FIG. 5 is a view illustrating a circuit diagram of an inverter 1 according to an embodiment of the present disclosure.

[0030] Referring to FIG. 5, the inverter 1 according to the present embodiment may include a first load transistor 11, a second load transistor 13, a driving transistor 15, and a control transistor 17.

[0031] A gate electrode and a drain electrode of the first load transistor 11 are connected to a power voltage (VDD) terminal. A gate electrode and a drain electrode of the second load transistor 13 are connected to a source electrode of the first load transistor 11, and a source electrode of the second load transistor 13 is connected to an output terminal.

[0032] A drain electrode of the driving transistor 15 is connected to the source electrode of the second load transistor 13 such that the output terminal is formed, a gate electrode of the driving transistor 15 is connected to an input (Vin) terminal, and a source electrode of the driving transistor 15 is connected to a ground (GND) terminal.

[0033] A drain electrode of the control transistor 17 is connected to the source electrode of the first load transistor 11, a gate electrode of the control transistor 17 is connected to the input (Vin) terminal, and a source electrode of the control transistor 17 is connected to the ground (GND) terminal.

[0034] The control transistor 17 is configured such that the source electrode of the first load transistor 11 is connected to the ground (GND) terminal when the gate electrode of the control transistor 17 is turned on, so that a voltage of a node (P) to which the drain electrode of the second load transistor 13 connected to the output terminal and the source electrode of the first load transistor 11 are connected becomes 0V.

[0035] FIG. 6 is a view illustrating an operation of an input 0 and output 1 logic of the inverter in FIG. 5.

[0036] Referring to FIG. 6, in a state in which the input is O, the driving transistor 15 and the control transistor 17 are turned off. The output voltage is connected to the VDD through the first load transistor 11 and the second load transistor 13 that are connected in series, so that the output voltage is increased by VDD-Vth. As the output voltage increases by VDD-Vth, a state in which the output is 1 is realized.

[0037] FIG. 7 is a view illustrating an operation of an input 1 and output 0 logic of the inverter in FIG. 5.

[0038] Referring to FIG. 7, in a state in which the input is 1, the driving transistor 15 and the control transistor 17 are turned on. It is preferable that a channel width of the control transistor 17 is set to be much larger than a channel width of each of the first and second load transistors 11 and 13. In the present embodiment, each resistance of the first and second load transistors 11 and 13 may be set to be much larger than a resistance of the control transistor 17. In this situation, the node (P) to which the first load transistor 11 and the second load transistor 13 are connected is connected to ground and becomes 0V. Eventually, since the drain electrode of the driving transistor 15 becomes 0V, the output voltage becomes a complete 0V.

[0039] FIG. 8 is view illustrating a circuit diagram of a bootstrap inverter 3 according to another embodiment of the present disclosure. Referring to FIG. 8, the bootstrap inverter 3 according to the present embodiment may include: a first load transistor 31 having a gate electrode and a drain electrode connected to a power voltage (VDD) terminal; a second load transistor 33 having a drain electrode connected to a source electrode of the first load transistor 31 and having a source electrode of the second load transistor 33 connected to an output terminal; a bootstrap transistor 30 having a gate electrode and a drain electrode connected to the power voltage (VDD) terminal and having a source electrode connected to a gate electrode of the second load transistor 33; a driving transistor 35 having a drain electrode connected to the source electrode of the second load transistor 33 such that the output terminal is formed, the driving transistor 35 having a gate electrode connected to an input (Vin) terminal and having a source electrode connected to a ground (GND) terminal; and a control transistor 37 having a drain electrode connected to the source electrode of the first load transistor 31, having a gate electrode connected to the input (Vin) terminal, and having a source electrode connected to the ground (GND) terminal. In addition, the bootstrap inverter 3 may further include a capacitor having a first end connected to the source electrode of the bootstrap transistor and having a second end connected to the output terminal.

[0040] FIG. 9 is a view illustrating an operation of an input 0 and output 1 logic of the bootstrap inverter 3. Referring to FIG. 9, in a state in which the input is 0, the driving transistor 35 and the control transistor 37 are turned off. The VDD voltage is connected to the output through the first load transistor 31 and the second load transistor 33, so that the output voltage is increased. At this time, as the output voltage is increased, each gate voltage of the first and second load transistors 31 and 33 is also increased due to the bootstrap transistor 30, and the output voltage is increased to the VDD, so that a state in which the output voltage is VDD that is l is realized.

[0041] FIG. 10 is a view illustrating an operation of an input 1 and output 0 logic of the bootstrap inverter 3. Referring to FIG. 10, in a state in which the input voltage is VDD that is 1, the driving transistor 35 and the control transistor 37 are turned on. Therefore, the voltage of the node P to which the first and second load transistors 31 and 33 are connected becomes 0V, and the output voltage becomes 0V. Therefore, in the state in which the input is 1, the output voltage is 0V, and an ideal 0 logic is capable of being realized.

[0042] Although the present disclosure has been described in detail through representative embodiments, those skilled in the art to which the present disclosure belongs will understand that various modifications of the described embodiments are possible within the spirit and scope of the present disclosure. Therefore, the spirit of the present disclosure should not be limited to the described embodiments, and all things equal or equivalent to the claims as well as the claims to be described later fall within the scope of the concept of the present disclosure.

DESCRIPTION OF REFERENCE NUMERALS

[0043] 1, 3: inverter [0044] 11, 31: first load transistor [0045] 13, 33: second load transistor [0046] 15, 35: driving transistor [0047] 17, 37: control transistor [0048] 30: bootstrap transistor

INDUSTRIAL APPLICABILITY

[0049] The present disclosure relates to an inverter and a bootstrap inverter, and the inverter and the bootstrap inverter having improved output characteristics may be provided by applying a circuit in which a predetermined transistor is added.