Semiconductor device

Abstract

A semiconductor device includes a substrate, a first transistor disposed on the substrate, a second transistor in proximity to the first transistor on the substrate, at least one interlayer dielectric layer covering the first transistor and the second transistor, a first stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the first transistor, and a second stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the second transistor.

Claims

1. A semiconductor device, comprising: a substrate; a first transistor disposed on the substrate; a second transistor disposed in proximity to the first transistor on the substrate; at least one interlayer dielectric layer covering the first transistor and the second transistor; a first stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the first transistor, wherein the first stress-inducing dummy metal pattern induces tensile stress to a channel of the first transistor; and a second stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the second transistor, wherein the second stress-inducing dummy metal pattern induces compressive stress to a channel of the second transistor, wherein the first stress-inducing dummy metal pattern and the second stress-inducing dummy metal pattern are disposed in a top metal layer or a pad layer disposed on an uppermost interlayer dielectric layer that is in direct contact with a passivation layer.

2. The semiconductor device according to claim 1, wherein the top metal layer is a copper damascene layer.

3. The semiconductor device according to claim 1, wherein the pad layer is an aluminum pad layer.

4. The semiconductor device according to claim 1, wherein the first stress-inducing dummy metal pattern is an annular metal ring pattern and the second stress-inducing dummy metal pattern is a monolithic pad pattern.

5. The semiconductor device according to claim 1, wherein the first stress-inducing dummy metal pattern and the second stress-inducing dummy metal pattern are monolithic pad patterns.

6. The semiconductor device according to claim 1, wherein the first stress-inducing dummy metal pattern and the second stress-inducing dummy metal pattern are annular metal ring patterns.

7. The semiconductor device according to claim 1, wherein the first stress-inducing dummy metal pattern and the second stress-inducing dummy metal pattern are covered with the passivation layer.

8. The semiconductor device according to claim 7, wherein the passivation layer comprises a silicon oxide layer and a stressed silicon nitride layer.

9. The semiconductor device according to claim 8, wherein the stressed silicon nitride layer is a compressive silicon nitride layer.

10. The semiconductor device according to claim 8, wherein the first transistor is an NMOS transistor and the stressed silicon nitride layer has tensile stress over the first transistor, and wherein the second transistor is a PMOS transistor and the stressed silicon nitride layer has compressive stress over the second transistor.

11. The semiconductor device according to claim 8, wherein the first transistor is an NMOS transistor and the stressed silicon nitride layer has compressive stress over the first transistor, and wherein the second transistor is a PMOS transistor and the stressed silicon nitride layer has tensile stress over the second transistor.

12. The semiconductor device according to claim 1, wherein the first stress-inducing dummy metal pattern and the second stress-inducing dummy metal pattern are electrically floating.

13. The semiconductor device according to claim 1, wherein the first stress-inducing dummy metal pattern and the second stress-inducing dummy metal pattern have a width greater than or equal to 2 micrometers along an extending direction of a gate underlying the first stress-inducing dummy metal pattern and the second stress-inducing dummy metal pattern.

14. The semiconductor device according to claim 1, wherein the first stress-inducing dummy metal pattern and the second stress-inducing dummy metal pattern have a thickness greater than 0.8 micrometers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

(2) FIG. 2 is a schematic cross-sectional view taken along line I-I in FIG. 1.

(3) FIG. 3 is a schematic cross-sectional view taken along the line II-II in FIG. 1.

(4) FIG. 4 is a schematic top view of a semiconductor device according to another embodiment of the present invention.

(5) FIG. 5 is a schematic cross-sectional view taken along line I-I in FIG. 4.

(6) FIG. 6 is a schematic cross-sectional view taken along line II-II in FIG. 4.

(7) FIG. 7 is a schematic top view of a semiconductor device according to still another embodiment of the present invention.

(8) FIG. 8 is a schematic cross-sectional view taken along line I-I in FIG. 7.

(9) FIG. 9 is a schematic cross-sectional view taken along line II-II in FIG. 7.

DETAILED DESCRIPTION

(10) In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

(11) Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

(12) The present invention discloses a semiconductor device comprising a field effect transistor (FET) device and a stress-inducing dummy metal pattern disposed directly above the FET device, which is suitable for applications in, for example, inverter circuits, radio frequency switches (RF switches) circuits, voltage regulator circuits, buck converter circuits, power amplifiers, RF LDMOS voltage controllers, single-pole double-throw RF switch for wireless communication systems, or switch mode power supply, etc.

(13) Please refer to FIG. 1 to FIG. 3. FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic cross-sectional view taken along line I-I in FIG. 1. FIG. 3 is a cross-sectional schematic view taken along line II-II in FIG. 1. As shown in FIG. 1 to FIG. 3, the semiconductor device 1 includes a substrate 100, such as a silicon substrate, but not limited thereto. On the substrate 100, a first transistor T1 is provided. For example, the first transistor T1 may be an NMOS transistor. A second transistor T2 is provided adjacent to the first transistor T1 on the substrate 100. For example, the second transistor T2 may be a PMOS transistor.

(14) According to an embodiment of the present invention, the first transistor T1 includes a gate G1 extending along the reference Y-axis direction, a source doped region S1, and a drain doped region D1. According to an embodiment of the present invention, the second transistor T2 includes a gate electrode G2 extending along the reference Y-axis direction, a source doped region S2, and a drain doped region D2. According to the embodiment of the present invention, the gate G1 and the gate G2 may be connected.

(15) According to an embodiment of the present invention, at least an interlayer dielectric layer is disposed on the substrate 100, for example, the interlayer dielectric layers IL1, IL2 and ILn in FIG. 2 and FIG. 3, which cover the first transistor T1 and the second transistor T2. According to an embodiment of the present invention, the interlayer dielectric layers IL1, IL2 and ILn may be low-k or ultra-low-k dielectric layers, and the interlayer dielectric layer ILn may be the uppermost interlayer dielectric layer.

(16) According to an embodiment of the present invention, the interlayer dielectric layers IL1, IL2 and ILn are provided with metal interconnect structures IS including, for example, the contact plugs CS1 and CD1 electrically connected to the source doped region S1 and the drain doped region D1 of the first transistor T1, respectively, and the contact plugs CS2 and CD2 electrically connected to of the source doped region S2 and the drain doped region D2 of the second transistor T2, respectively.

(17) According to an embodiment of the present invention, a first stress-inducing dummy metal pattern SID1 may be disposed on the interlayer dielectric layer ILn. According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 is located directly above the first transistor T1. According to an embodiment of the present invention, a second stress-inducing dummy metal pattern SID2 may be further disposed on the interlayer dielectric layer ILn. According to an embodiment of the present invention, the second stress-inducing dummy metal pattern SID2 is located directly above the second transistor T2.

(18) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 may be disposed in the top metal layer (or the topmost layer metal). According to an embodiment of the present invention, the top metal layer is a copper damascene layer.

(19) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 may be disposed in a pad layer.

(20) According to an embodiment of the present invention, the pad layer is an aluminum pad layer.

(21) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 is an annular metal ring pattern, and the second stress-inducing dummy metal pattern SID2 may be a monolithic pad pattern (without holes in the middle), for example, a square pad pattern. According to an embodiment of the present invention, the width W1 of the first stress-inducing dummy metal pattern SID1 in the reference Y-axis direction is greater than or equal to 2 m, for example, between 5-12 m, but not limited thereto. According to an embodiment of the present invention, the width W2 of the second stress-inducing dummy metal pattern SID2 in the reference Y-axis direction is greater than or equal to 2 m, for example, between 5-12 m, but not limited thereto.

(22) According to an embodiment of the present invention, for example, the size of the first stress-inducing dummy metal pattern SID1 is 9 m9 m, and the size of the central hole thereof is 7 m7 m. For example, the size of the second stress-inducing dummy metal pattern SID2 is 5 m5 m or 7 m7 m, but not limited thereto. According to an embodiment of the present invention, the thicknesses of the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are greater than 0.8 m, but not limited thereto.

(23) According to an embodiment of the present invention, as shown in FIG. 2 and FIG. 3, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are covered by the passivation layer 300. According to an embodiment of the present invention, the passivation layer 300 includes, for example, a silicon oxide layer 301 and a stressed silicon nitride layer 302. For example, the thickness of the silicon oxide layer 301 is about 4000 angstroms, and the thickness of the stressed silicon nitride layer 302 is about 5000 angstroms, but not limited thereto. According to an embodiment of the present invention, the stressed silicon nitride layer 302 is a compressive silicon nitride layer with compressive stress.

(24) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are electrically floating.

(25) One technical feature of the present invention is that the first stress-inducing dummy metal pattern SID1 can induce tensile stress in both the reference X-axis direction and the reference Y-axis direction to the channel of the first transistor T1 below, while the second stress-inducing dummy metal pattern SID2 can induce compressive stress in the reference X-axis direction to the channel of the second transistor T2 below, thereby enhancing operation performance of the second transistor T2.

(26) Please refer to FIG. 4 to FIG. 6. FIG. 4 is a schematic top view of a semiconductor device according to another embodiment of the present invention, FIG. 5 is a schematic cross-sectional view taken along line I-I in FIG. 4, and FIG. 6 is a schematic cross-sectional view taken along line II-II in FIG. 4, wherein like regions, layers or elements are designated by like numeral numbers or labels.

(27) As shown in FIG. 4 to FIG. 6, likewise, the semiconductor device 2 includes a substrate 100, such as a silicon substrate, but not limited thereto. On the substrate 100, a first transistor T1 is provided. For example, the first transistor T1 may be an NMOS transistor. A second transistor T2 is provided adjacent to the first transistor T1 on the substrate 100. For example, the second transistor T2 may be a PMOS transistor.

(28) According to an embodiment of the present invention, the first transistor T1 includes a gate G1 extending along the reference Y-axis direction, a source doped region S1, and a drain doped region D1. According to an embodiment of the present invention, the second transistor T2 includes a gate G2 extending along the reference Y-axis direction, a source doped region S2, and a drain doped region D2. According to an embodiment of the present invention, the gate G1 and the gate G2 may be connected.

(29) According to an embodiment of the present invention, at least one interlayer dielectric layer is disposed on the substrate 100, for example, the interlayer dielectric layers IL1, IL2 and ILn in FIG. 5 and FIG. 6, covering the first transistor T1 and the second transistor T2. According to an embodiment of the present invention, the interlayer dielectric layers IL1, IL2 and ILn may be low-k or ultra-low-k dielectric layers, and the interlayer dielectric layer ILn may be the uppermost interlayer dielectric layer.

(30) According to an embodiment of the present invention, the interlayer dielectric layers IL1, IL2 and ILn are provided with metal interconnect structures IS including, for example, the contact plugs CS1 and CD1 electrically connected to the source doped region S1 and the drain doped region D1 of the first transistor T1, respectively, and the contact plugs CS2 and CD2 electrically connected to of the source doped region S2 and the drain doped region D2 of the second transistor T2, respectively.

(31) According to an embodiment of the present invention, a first stress-inducing dummy metal pattern SID1 may be disposed on the interlayer dielectric layer ILn. According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 is located directly above the first transistor T1. According to an embodiment of the present invention, a second stress-inducing dummy metal pattern SID2 may be further disposed on the interlayer dielectric layer ILn. According to an embodiment of the present invention, the second stress-inducing dummy metal pattern SID2 is located directly above the second transistor T2.

(32) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 may be disposed in the top metal layer (or the topmost layer metal). According to an embodiment of the present invention, the top metal layer is a copper damascene layer.

(33) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 may be disposed in a pad layer.

(34) According to an embodiment of the present invention, the pad layer is an aluminum pad layer.

(35) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are monolithic pad patterns, for example, monolithic square patterns. According to an embodiment of the present invention, the width W1 of the first stress-inducing dummy metal pattern SID1 in the reference Y-axis direction is greater than or equal to 2 m, for example, between 5-12 m, but not limited thereto. According to an embodiment of the present invention, the width W2 of the second stress-inducing dummy metal pattern SID2 in the reference Y-axis direction is greater than or equal to 2 m, for example, between 5-12 m, but not limited thereto.

(36) According to an embodiment of the present invention, for example, the sizes of the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are both 5 m5 m or 7 m7 m, but not limited thereto. According to an embodiment of the present invention, the thicknesses of the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are greater than 0.8 m, but not limited thereto.

(37) According to an embodiment of the present invention, as shown in FIG. 5 and FIG. 6, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are covered by the passivation layer 300. According to an embodiment of the present invention, the passivation layer 300 includes, for example, a silicon oxide layer 301 and a stressed silicon nitride layer 302. For example, the thickness of the silicon oxide layer 301 is about 4000 angstroms, and the thickness of the stressed silicon nitride layer 302 is about 5000 angstroms, but not limited thereto. According to an embodiment of the present invention, the stressed silicon nitride layer 302 has tensile stress in the area A1 over the first transistor T1, and has compressive stress above the second transistor T2.

(38) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are electrically floating.

(39) Please refer to FIG. 7 to FIG. 9. FIG. 7 is a schematic top view of a semiconductor device according to still another embodiment of the present invention, FIG. 8 is a schematic cross-sectional view taken along line I-I in FIG. 7, and FIG. 9 is a schematic cross-sectional view taken along line II-II in FIG. 7, wherein like regions, layers or elements are designated by like numeral numbers or labels.

(40) As shown in FIG. 7 to FIG. 9, likewise, the semiconductor device 3 includes a substrate 100, such as a silicon substrate, but not limited thereto. On the substrate 100, a first transistor T1 is provided. For example, the first transistor T1 may be an NMOS transistor. A second transistor T2 is provided adjacent to the first transistor T1 on the substrate 100. For example, the second transistor T2 may be a PMOS transistor.

(41) According to an embodiment of the present invention, the first transistor T1 includes a gate G1 extending along the reference Y-axis direction, a source doped region S1, and a drain doped region D1. According to an embodiment of the present invention, the second transistor T2 includes a gate G2 extending along the reference Y-axis direction, a source doped region S2, and a drain doped region D2. According to the embodiment of the present invention, the gate G1 and the gate G2 may be connected.

(42) According to an embodiment of the present invention, at least an interlayer dielectric layer is disposed on the substrate 100, for example, the interlayer dielectric layers IL1, IL2 and ILn in FIG. 8 and FIG. 9, covering the first transistor T1 and the second transistor T2. According to an embodiment of the present invention, the interlayer dielectric layers IL1, IL2 and ILn may be low-k or ultra-low-k dielectric layers. The interlayer dielectric layer ILn may be the uppermost interlayer dielectric layer.

(43) According to an embodiment of the present invention, the interlayer dielectric layers IL1, IL2 and ILn are provided with metal interconnect structures IS including, for example, the contact plugs CS1 and CD1 electrically connected to the source doped region S1 and the drain doped region D1 of the first transistor T1, respectively, and the contact plugs CS2 and CD2 electrically connected to of the source doped region S2 and the drain doped region D2 of the second transistor T2, respectively.

(44) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 may be disposed on the interlayer dielectric layer ILn. According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 is located directly above the first transistor T1. According to an embodiment of the present invention, a second stress-inducing dummy metal pattern SID2 may be further disposed on the interlayer dielectric layer ILn. According to an embodiment of the present invention, the second stress-inducing dummy metal pattern SID2 is located directly above the second transistor T2.

(45) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 may be disposed in the top metal layer (or the topmost layer metal). According to an embodiment of the present invention, the top metal layer is a copper damascene layer.

(46) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 may be disposed in a pad layer.

(47) According to an embodiment of the present invention, the pad layer is an aluminum pad layer.

(48) According to an embodiment of the present invention, both the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are annular metal ring patterns. According to an embodiment of the present invention, the width W1 of the first stress-inducing dummy metal pattern SID1 in the reference Y-axis direction is greater than or equal to 2 m, for example, between 5-12 m, but not limited thereto. According to an embodiment of the present invention, the width W2 of the second stress-inducing dummy metal pattern SID2 in the reference Y-axis direction is greater than or equal to 2 m, for example, between 5-12 m, but not limited thereto.

(49) According to an embodiment of the present invention, for example, the sizes of the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are both 7 m7 m or 9 m9 m, but not limited thereto. According to an embodiment of the present invention, the thicknesses of the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are greater than 0.8 m, but not limited thereto.

(50) According to an embodiment of the present invention, as shown in FIG. 8 and FIG. 9, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are covered by the passivation layer 300. According to an embodiment of the present invention, the passivation layer 300 includes, for example, a silicon oxide layer 301 and a stressed silicon nitride layer 302. For example, the thickness of the silicon oxide layer 301 is about 4000 angstroms, and the thickness of the stressed silicon nitride layer 302 is about 5000 angstroms, but not limited thereto. According to an embodiment of the present invention, the stressed silicon nitride layer 302 has tensile stress in the area A2 over the second transistor T2, and has compressive stress above the first transistor T1.

(51) According to an embodiment of the present invention, the first stress-inducing dummy metal pattern SID1 and the second stress-inducing dummy metal pattern SID2 are electrically floating.

(52) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.