Memory device including double PN junctions and driving method thereof, and capacitor-less memory device including double PN junctions and control gates and operation method thereof

Abstract

A memory device includes at least one semiconductor layer having a double PN junction, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. In addition, a capacitor-less memory device includes at least one semiconductor layer including a double PN junction, a control gate which contacts the semiconductor layer, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. Methods of operating the memory device and the capacitor-less memory device are also disclosed.

Claims

1. A memory device including a double PN junction, comprising: at least one semiconductor layer having a double PN junction; and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction, and wherein the semiconductor layer is an NPN-type semiconductor layer, an N-type semiconductor layer of the NPN-type semiconductor layer is low concentration, and the other N-type semiconductor layer of the NPN-type semiconductor layer is high concentration.

2. The memory device including a double PN junction according to claim 1, wherein the NPN-type semiconductor layer comprises the N-type semiconductor layer, a P-type semiconductor layer, and the other N-type semiconductor layer.

3. The memory device including a double PN junction according claim 1, wherein the low concentration N-type semiconductor layer contacts the anode, and the high concentration N-type semiconductor layer contacts the cathode.

4. The memory device including a double PN junction according to claim 3, wherein a junction between the anode and the low concentration N-type semiconductor layer is the Schottky junction, and a junction between the high concentration N-type semiconductor layer and the cathode is the Ohmic junction.

5. A memory device array comprising the memory device according to claim 1 as a unit device.

6. An operation method of a memory device including a double PN junction, comprising: applying a program voltage to the memory device; lowering resistance of at least one semiconductor layer by lowering a potential barrier of the double PN junction by the program voltage to move carriers to the semiconductor layer; and reading the resistance of the semiconductor layer, wherein the memory device comprises: the semiconductor layer having the double PN junction; and an anode and a cathode which simultaneously contact the semiconductor layer, and wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction.

7. The operation method of a memory device according to claim 6, further comprising: after lowering the resistance of the semiconductor layer, increasing the resistance of the semiconductor layer by selectively applying an erase voltage to the memory device.

8. The operation method of a memory device according to claim 7, further comprising: after applying the program voltage, re-lowering the resistance of the semiconductor layer by selectively re-applying a refresh voltage to the memory device.

9. A capacitor-less memory device including a double PN junction and a control gate, comprising: at least one semiconductor layer having a double PN junction; a control gate which contacts the semiconductor layer; and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction, wherein the semiconductor layer is an NPN-type semiconductor layer, an N-type semiconductor layer of the NPN-type semiconductor layer is low concentration, and the other N-type semiconductor layer of the NPN-type semiconductor layer is high concentration, and wherein the low concentration N-type semiconductor layer contacts the anode, and the high concentration N-type semiconductor layer contacts the cathode.

10. A memory device array comprising the capacitor-less memory device according to claim 9 as a unit device.

11. An operation method of the capacitor-less memory device including a double PN junction and a control gate according to claim 9, the operation method comprising: applying a program voltage to the capacitor-less memory device; lowering resistance of the semiconductor layer by lowering a potential barrier of the double PN junction by the program voltage to move carriers to the semiconductor layer; and reading the resistance of the semiconductor layer.

12. The operation method of a capacitor-less memory device according to claim 11, further comprising: after lowering the resistance of the semiconductor layer, increasing the resistance of the semiconductor layer by selectively applying an erase voltage to the capacitor-less memory device.

13. The operation method of a capacitor-less memory device according to claim 11, further comprising: inhibiting, by the control gate, an operation error of an unselected cell in a memory cell array configuration formed using the capacitor-less memory device.

Description

DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a diagram of a memory device according to an embodiment of the present disclosure, and FIG. 2 is a diagram of a memory device having no N-type semiconductor layer between a P-type semiconductor layer and an anode as a comparative example.

(2) FIGS. 3 to 6 are energy diagrams illustrating an operating mechanism of a memory device (NPN+) according to an embodiment of the present disclosure.

(3) FIGS. 7 to 10 are energy diagrams illustrating an operating mechanism of a memory device having no N-type semiconductor layer between a P-type semiconductor layer and an anode.

(4) FIG. 11 shows the hole concentration in a P-type semiconductor layer of an embodiment and comparative examples over time after program.

(5) FIG. 12 is a diagram of a memory device array including the memory device of an embodiment as a unit device.

(6) FIG. 13 is a diagram of a memory device according to an embodiment of the present disclosure.

(7) FIGS. 14 to 16 are energy diagrams illustrating a program operation mechanism of a memory device according to an embodiment of the present disclosure.

(8) FIG. 17 is an energy band diagram of a memory device according to an embodiment before program (T.sub.ST, 0) and 10 sec after program (T.sub.ST, 1=10 s).

(9) FIGS. 18 to 19 are energy diagrams illustrating an erase operation mechanism of a memory device according to an embodiment of the present disclosure.

(10) FIG. 20 shows the operating voltage and the anode current of a memory device of an embodiment when a read operation is performed 10 sec after program (T.sub.ST, 1=10 s).

(11) FIG. 21 is a schematic diagram of a memory cell array configuration using a memory device according to an embodiment of the present disclosure.

(12) FIG. 22 is a table showing each operating voltage condition (anode, gate, cathode voltage) of a selected cell and an unselected cell according to each operation mode (standby, program, erase, read) of a device of an embodiment of the present disclosure.

(13) FIGS. 23 to 25 show memory characteristics by array disturbance pulses that may occur in each operation mode of a device of an embodiment of the present disclosure.

(14) FIG. 23 is an energy band diagram of a memory device of an embodiment by the application of program disturbance pulses to an unselected cell during the program operation of FIG. 22.

(15) FIG. 24 shows the stored hole concentration (N.sub.P) in a memory device of an embodiment by repetition of erase disturbance pulses applied to an unselected cell during the erase operation of FIG. 22.

(16) FIG. 25 shows the operating voltage and the anode current of a memory device of an embodiment by the repeated application of read pulses 10 times after the erase operation of FIG. 22.

(17) FIG. 26 is a diagram of a memory device array including the memory device of an embodiment as a unit device.

BEST MODE

(18) The present disclosure may be variously modified and have many different forms, and particular embodiments will be shown in the drawings and specifically described herein as below. However, it should be understood that this is not intended to limit the present disclosure to a particular disclosed embodiment and encompasses all modifications, equivalents or substitutes included in the spirit and scope of the present disclosure. In describing each drawing, like reference signs are used for like elements.

(19) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art document, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(20) Additionally, the terms anode, cathode, control gate, N-type region, P-type region, PN junction, Schottky junction and Ohmic junction as used herein are interpreted at the ordinary level, various changes may be made to the type, and such changes fall in the scope of the present disclosure. Additionally, the semiconductor layer is a device layer including a semiconductor material no matter whether it is horizontal or vertical, and encompasses any semiconductor structure including at least one NPN or PNP junction. Additionally, although the control gate is described as being disposed on the semiconductor layer, the structure is not limited to bottom or gate-all around, and encompasses any control gate structure that contacts the semiconductor layer. In the present disclosure, “capacitor-less” refers to no capacitor.

(21) To solve the above-described problem, the present disclosure combines the energy barrier at the Schottky junction with the energy barrier at the PN or NP junction, to increase the usage possibility of the memory device by avoiding the reliance on the metal work function as opposed to comparative example using the energy barrier at the Schottky junction alone. Accordingly, the semiconductor layer of the memory device according to an embodiment of the present disclosure includes a double PN junction such as NPN or PNP, and one of them forms a Schottky junction with the anode and the other forms an Ohmic junction.

(22) Additionally, to solve the above-described problem, the present disclosure includes an anode, a semiconductor layer including a double PN junction (an NPN junction and a PNP junction) and a cathode, the anode and the cathode in contact with the semiconductor layer form a Schottky junction and an Ohmic junction respectively, and a control gate is formed on the semiconductor layer. Accordingly, the simple device structure not requiring a capacitor may greatly improve the device integrity, and when a memory array is formed using the memory device, the disturbance problem between adjacent memory devices may be inhibited by the control gate, thereby achieving reliability of the memory array operation. Further, the present disclosure may protect data in adjacent memory devices by controlling carriers accumulated in the semiconductor layer through the control gate, thereby achieving reliability of the memory array operation.

(23) Hereinafter, the present disclosure will be described in more detail using a memory device according to an embodiment of the present disclosure using an NPN-type semiconductor layer.

(24) FIG. 1 is a diagram of a memory device according to an embodiment of the present disclosure, and FIG. 2 is a diagram of a memory device according to comparative example.

(25) Referring to FIGS. 1 and 2, the memory device according to an embodiment of the present disclosure uses an NPN semiconductor layer including an NP junction, in which an N-type semiconductor layer is sandwiched between an anode and a semiconductor layer including a PN junction, and the anode forms a Schottky junction with the NPN semiconductor layer and the cathode forms an Ohmic junction with the N-type semiconductor layer. The memory device of FIG. 2 of comparative example has a structure in which an anode and a P-type semiconductor layer form a Schottky junction, and an N-type semiconductor layer and a cathode form an Ohmic junction.

(26) The NPN-type memory device according to an embodiment of the present disclosure has a structure in which a high concentration N-type semiconductor layer contacts the cathode, and a low concentration N-type semiconductor contacts the anode.

(27) In case that the low concentration N-type semiconductor layer contacts the cathode, a Schottky junction rather than an Ohmic junction is formed, and in this case, sufficient electrons for impact ionization in the semiconductor layer may not be supplied from the cathode. Additionally, in case that the high concentration N-type semiconductor layer contacts the anode, the memory erase operation may fail. That is, in case that the high concentration N-type semiconductor layer contacts the anode, an Ohmic junction may be formed, and in this case, when a negative voltage is applied to the anode, electron transport and impact ionization occurs, leading to carrier accumulation.

(28) The gravest problem of comparative example shown in FIG. 2 is that the resistance state retention performance of the memory device may be greatly dependent on the height of Schottky barrier.

(29) A different in the retention time T.sub.ret as a function of Schottky barrier energy (Barrier Potential, φ.sub.Bp) in the memory device of the structure of FIG. 2 is as follows.
φ.sub.Bp=0.966 eV.fwdarw.T.sub.ret=300 ms, φ.sub.Bp=0.815 eV.fwdarw.T.sub.ret=3 ms

(30) Referring to the above result, it can be seen that the difference of 0.15 eV makes a difference to the retention time about 100 times. For the stable operation of the memory device, it is necessary to precisely control the energy barrier at the Schottky junction, and eventually, this limits the selection of anode materials. Additionally, even though there is a metal material having an optimal work function, the operation of the memory device may fail or the performance may greatly degrade due to defects formed at the interface of the anode metal electrode and the P-type semiconductor layer in the fabrication of the device.

(31) FIGS. 3 to 6 are energy band diagrams illustrating the operating mechanism of the memory device (NPN.sup.+) according to an embodiment of the present disclosure. Here, the Schottky barrier height is set to 0.815 eV.

(32) FIG. 3 is an energy band diagram when the anode voltage of 0 V (an equilibrium state) is applied. The energy barrier at the PN.sup.+ junction is high, leading to High Resistance State (HRS) representing low current. In comparative example, the energy barrier at the Schottky junction is determined by the work function of the anode, while the memory device including a double PN junction according to an embodiment of the present disclosure may adjust the energy barrier height at the NP junction by adjusting the doping concentration of the N-type semiconductor layer in contact with the anode. Additionally, since the NP junction has the lower defect concentration than the metal contact interface, it is easy to ensure the outstanding retention time performance of the fabricated memory device.

(33) FIG. 4 is an energy band diagram when the anode voltage of 2.4 V (a trigger voltage of program operation) is applied. By the application of the anode voltage, the energy barrier at the Schottky junction and the PN.sup.+ junction is lowered. Subsequently, electrons in the high concentration N-type semiconductor layer N.sup.+ are transported to the anode across the P-type semiconductor layer.

(34) FIG. 5 shows an energy band when the anode voltage is maintained at 2.4 V (a trigger voltage of program operation) for the pulse duration. Referring to FIG. 5, the impact ionization effect by the high electric field at the NP junction generates electrons and holes, and in this instance, the generated electrons accumulate in the N-type region and are maintained for a predetermined time, and the generated holes accumulate in the P-type region, which lowers the potential barrier. In this instance, the lowered potential barrier leads to Low Resistance State (LRS) in which electrons can easily move.

(35) FIG. 6 is an energy band diagram when the anode voltage reduces from 2.4 V (a trigger voltage of program operation) to 0 V. The anode voltage is lowered, but holes accumulate in the P-type semiconductor layer and the low energy barrier is maintained. In this instance, since the present disclosure has a structure in which the N-type semiconductor layer is sandwiched, more holes accumulate after program, leading to lower energy barrier for electrons, and the retention time is 600 ms. This structure exhibits the same Schottky barrier height (0.815 eV) as comparative example, but may improve the retention time of stored holes by the energy barrier at the NP junction.

(36) FIGS. 7 to 10 are energy diagrams illustrating an operating mechanism of the memory device having no N-type semiconductor layer between the P-type semiconductor layer and the anode according to comparative example. Here, the Schottky barrier height is set to 0.815 eV in the same way as an embodiment of the present disclosure.

(37) Referring to FIGS. 7 to 10, when voltage (1.8 V) is applied to the anode for the program operation, the energy barrier at PN.sup.+ is lowered, and electrons in the high concentration N-type semiconductor layer N.sup.+ are transported to the anode across the P-type semiconductor layer.

(38) FIG. 9 is an energy band diagram when the anode voltage is maintained at 1.8 V (a trigger voltage of program operation) for the pulse duration. By the application of the anode voltage, more electrons flow, and high electric field of the anode and the P-type semiconductor layer generates electrons and holes through impact ionization.

(39) FIG. 10 is an energy band diagram when the anode voltage reduces from 1.8 V (a trigger voltage of program operation) to 0 V. The anode voltage is lowered, but holes accumulate in the P-type semiconductor layer and low energy barrier is maintained. The memory device according to comparative example exhibits the retention time of about 3 ms.

(40) FIG. 11 shows the concentration of holes accumulated in the P-type semiconductor layer in an embodiment and comparative examples over time after the program operation.

(41) Referring to FIG. 11, as the energy barrier height φ.sub.Bp at the Schottky junction of comparative example reduces from 0.966 eV to 0.815 eV, holes accumulate at lower concentration after program, and the data retention time T.sub.ret reduces from 300 ms to 3 ms.

(42) However, in the case of an embodiment having the N-type semiconductor layer, it can be seen that despite the low Schottky barrier height of 0.815 eV, the retention time T.sub.ret is significantly improved up to the level of 600 ms by the accumulation of more holes than comparative example after the program operation.

(43) FIG. 12 is a diagram of a memory device array including the memory device of an embodiment as a unit device. Referring to FIG. 12, the memory device array including the memory device of an embodiment as a unit device is possible, and this is included in the scope of the present disclosure.

(44) Additionally, the present disclosure provides an operation method of a memory device including a double PN junction. The operation method includes selectively applying a program voltage to at least one memory device including a double PN junction; lowering the resistance of the semiconductor layer by lowering the potential barrier of the semiconductor layer by the program voltage to move carriers to the semiconductor layer; selectively applying an erase voltage to the memory device; returning the resistance of the semiconductor layer back to the initial level by erasing the carriers in the semiconductor layer by the erase voltage; and reading the resistance of the semiconductor layer.

(45) That is, the present disclosure may perform a data write operation by changing the resistance value of the semiconductor layer from high resistance to low resistance by the application of the program voltage to the memory device including the Schottky junction and changing the resistance value of the semiconductor layer from low resistance to high resistance by the application of the erase voltage. Additionally, the low resistance value of the semiconductor layer is maintained for a predetermined time after the program operation, and the resistance value of the semiconductor layer may be continuously maintained by selectively applying voltage (a refresh voltage) below the trigger voltage for the program operation within the retention time and the low resistance state of the semiconductor layer may be verified by applying the read voltage. That is, data in the memory device may be verified.

(46) The memory device operation method may effectively perform data write, erase, read and retention without using a separate complex structure such as a capacitor.

(47) Hereinafter, the present disclosure will be described in more detail using a memory device according to an embodiment of the present disclosure using an NPN-type semiconductor layer and a control gate.

(48) FIG. 13 is a diagram of a memory device according to an embodiment of the present disclosure.

(49) Referring to FIG. 13, the memory device according to an embodiment of the present disclosure includes an anode, an NPN semiconductor layer, a cathode and a control gate, the anode and the cathode in contact with the semiconductor layer form a Schottky junction and an Ohmic junction respectively, and the control gate is formed on the P-type semiconductor layer. Additionally, an insulating layer may be interposed between the P-type semiconductor layer and the control gate.

(50) The NPN-type memory device according to an embodiment of the present disclosure has a structure in which the high concentration N-type semiconductor layer contacts the cathode, and the low concentration N-type semiconductor contacts the anode.

(51) Since the high concentration N-type semiconductor layer forms an Ohmic junction with the cathode, sufficient electron sources are supplied through the cathode, and impact ionization may generate sufficient storage carriers for the memory operation.

(52) Since the low concentration N-type semiconductor layer forms a Schottky junction with the anode, the energy barrier height of storage holes stored in the P-type semiconductor layer and the memory operating current may be adjusted by adjusting the doping concentration, and further, the doping concentration and the substantial operating characteristics of the device may be effectively controlled through the control gate.

(53) FIGS. 14 to 16 are energy diagrams illustrating the program operation mechanism of the memory device according to an embodiment of the present disclosure.

(54) FIG. 14 is an energy band diagram before program when a standby state anode-cathode voltage V.sub.AC, ST (1.3 V) that is capable of maintaining Low Resistance State (LRS) after program is applied. Before program, the memory device has high energy barrier at the PN.sup.+ junction and is in a High Resistance State (HRS) representing low current.

(55) FIG. 15 is an energy band diagram when the cathode voltage of −1.0 V (a trigger cathode voltage of program operation) is applied. By the application of the cathode voltage of −1.0 V, anode-cathode voltage V.sub.AC, P of 2.3 V and gate-cathode voltage V.sub.GC, P of 1.0 V are applied to the memory device. When the negative cathode voltage is applied, the energy barrier at the Schottky junction and the PN.sup.+ junction is lowered. Subsequently, electrons in the high concentration N-type semiconductor layer N.sup.+ are transported to the anode across the P-type semiconductor layer. The impact ionization effect by the interaction between the transported electrons and the high electric field at the NP junction generates electrons and holes, and in this instance, the generated holes accumulate in the P-type region, which lowers the energy barrier at the PN.sup.+ junction. In this instance, the lowered potential barrier leads to Low Resistance State (LRS) in which electrons can easily move.

(56) FIG. 16 is an energy band diagram when the cathode voltage changes from −1.0 V (a trigger cathode voltage for program operation) back to the initial 0.0 V. The anode-cathode voltage V.sub.AC and the gate-cathode voltage V.sub.GC are reduced to 1.3 V and 0.0 V respectively, but the generated holes accumulate in the P-type semiconductor layer and the low PN.sup.+ energy barrier is maintained.

(57) FIG. 17 is an energy band diagram of the memory device according to an embodiment before program (T.sub.ST, 0) and 10 sec after program (T.sub.ST, 1=10 s). Since the standby state anode-cathode voltage V.sub.AC, ST (1.3 V) that is capable of maintaining Low Resistance State (LRS) is applied to the memory device, the programmed device may maintain the Low Resistance State (LRS) even after 10 seconds.

(58) FIGS. 18 to 19 are energy diagrams illustrating the erase operation mechanism of the memory device according to an embodiment of the present disclosure.

(59) FIG. 18 is an energy band diagram when 1.0 V (a gate voltage for erase operation) is applied to erase the holes stored in the P-type semiconductor layer of FIG. 16. By the application of the gate voltage of 1.0 V, gate-cathode voltage V.sub.GC, E of 1.0 V is applied to the memory device. In the memory device according to this embodiment, the stored holes in the P-type semiconductor layer are depleted by applying the positive gate voltage.

(60) FIG. 19 is an energy band diagram when the gate voltage of 1.0 V (a gate voltage for erase operation) returns back to the initial 0.0 V. The energy barrier at the PN.sup.+ junction is high due to the erased holes in the P-type semiconductor layer, and the memory state returns back to High Resistance State (HRS) before program.

(61) FIG. 20 shows the operating voltage and the anode current of the memory device of an embodiment when the read operation is performed 10 sec after program (T.sub.ST, 1=10 s). To accurately detect each memory state, the cathode voltage and the gate voltage are reduced to −1.0 V and −0.8 V respectively. Through this, the anode-cathode voltage V.sub.AC, R of 2.3 V and the gate-cathode voltage V.sub.GC, R of 0.2 V are applied to the memory device. The Low Resistance State (LRS) maintained after program may be detected at the high current level even after 10 seconds through the read voltage pulses.

(62) FIG. 21 is a schematic diagram of a memory cell array configuration using the memory device according to an embodiment of the present disclosure. When the gate-cathode voltage V.sub.GC is applied to an unselected device in the memory operation, it is possible to prevent unwanted operation errors. To effectively adjust the gate-cathode voltage V.sub.GC in the array configuration, the gate and the cathode are set by the word line WL and the bit line BL respectively, and for the standby state anode-cathode voltage V.sub.AC, ST that is capable of maintaining the Low Resistance State (LRS), the anode is fixed to 1.3 V.

(63) FIG. 22 is a table showing each operating voltage condition (anode, gate, cathode voltage) of a selected cell and an unselected cell according to each operation mode (standby, program, erase, read) of the device of an embodiment of the present disclosure. To maintain the stable resistance state in the standby state, the gate voltage V.sub.G and the cathode voltage V.sub.C in the standby state are all set to 0.0 V.

(64) FIGS. 23 to 25 show the memory characteristics by array disturbance pulses that may occur in each operation mode of the device of an embodiment of the present disclosure.

(65) FIG. 23 is an energy band diagram of the memory device of an embodiment by the application of the program disturbance pulses to the unselected cell during the program operation of FIG. 22. The program anode-cathode voltage V.sub.AC, P of 2.3 V and the gate-cathode voltage V.sub.GC of 0.0 V are applied to memory devices corresponding to a selected bit line BL and an unselected word line WL. When the gate-cathode voltage V.sub.GC of the unselected memory device is maintained below 0.0 V, there is no change in energy band before and after the program disturbance pulses, thereby preventing program disturbance-induced errors.

(66) FIG. 24 shows the stored hole concentration NP in the memory device of an embodiment by repetition of erase disturbance pulses applied to the unselected cell during the erase operation of FIG. 22. The anode-cathode voltage VAC of 0.3 V and the gate-cathode voltage V.sub.GC of 0.0 V are applied to the selected word line WL and the unselected bit line BL. Since the gate-cathode voltage V.sub.GC is maintained below 0.0 V, the stored hole concentration in the programmed cell does not change in spite of the repeated erase disturbance pulses, thereby preventing erase disturbance-induced errors.

(67) FIG. 25 shows the operating voltage and the anode current of the memory device of an embodiment by the repeated application of read pulses 10 times after the erase operation of FIG. 22. The read pulses of the anode-cathode voltage V.sub.AC, R of 2.3 V and the gate-cathode voltage V.sub.GC, R of 0.2 V are repeatedly applied to the erased memory device, but there is no change in the read current level, so High Resistance State (HRS) of the erased memory is stably maintained, thereby preventing read operation-induced program errors.

(68) FIG. 26 is a diagram of a memory device array including the memory device of an embodiment as a unit device. Referring to FIG. 26, the memory device array including the memory device of an embodiment as a unit device is possible, and this is included in the scope of the present disclosure.

(69) Additionally, the present disclosure provides an operation method of a memory device including a double PN junction and a control gate. The operation method includes selectively applying a program voltage to at least one memory device including a double PN junction; lowering the resistance of the semiconductor layer by lowering the potential barrier of the semiconductor layer by the program voltage to move carriers to the semiconductor layer; selectively applying an erase voltage to the memory device; returning the resistance of the semiconductor layer back to the initial level by erasing the carriers in the semiconductor layer by the erase voltage; and reading the resistance of the semiconductor layer.

(70) That is, the present disclosure performs a data write operation by changing the resistance value of the semiconductor layer from high resistance to low resistance by the application of the program voltage to the memory device including the double PN junction and the control gate and changing the resistance value of the semiconductor layer from low resistance to high resistance by the application of the erase voltage. Additionally, the low resistance value of the semiconductor layer after the program operation may be stably maintained by applying the standby state anode-cathode voltage V.sub.AC, ST (1.3 V) that is capable of maintaining Low Resistance State (LRS) after program, and the low resistance state of the semiconductor layer may be verified by applying the read voltage. That is, data in the memory device may be verified.

(71) The memory device operation method may effectively perform data write, erase, read and retention without using a separate complex structure such as a capacitor.