Circuit for controlling a resistive circuit

Abstract

In accordance with an embodiment, a circuit is configured to vary an intensity of a drive current of a resistive heater element based on the digital control signal. The circuit includes and output circuit configured to control a respective slew rate and an electric energy dissipated in the resistive heater element independently of a resistance value of the resistive heater element.

Claims

1. A circuit, comprising: a heater drive node configured to be coupled to a resistive heater element to provide a drive current thereto, wherein power dissipated in the resistive heater element varies over time as a function of an intensity of the drive current provided to the resistive heater element; control circuitry configured to vary the intensity of the drive current of the resistive heater element, wherein the control circuitry comprises: driver circuitry configured to produce an analog target voltage based on an analog drive current intensity signal; and an output circuit coupled to the driver circuitry to receive therefrom the analog target voltage, the output circuit configured to produce the drive current provided to the resistive heater element based on the analog target voltage, wherein the output circuit is configured to control the power dissipated in the resistive heater element independently of a resistance value of the resistive heater element, and the output circuit comprises an amplifier and a feedback capacitor coupled between an output of the amplifier and the heater drive node.

2. The circuit of claim 1, wherein: the driver circuitry is configured to provide the drive current based on the analog target voltage with a respective slew rate, and the output circuit is configured to control the respective slew rate of the drive current provided to the resistive heater element independently of the resistance value of the resistive heater element.

3. The circuit of claim 1, wherein the output circuit is configured to produce: the drive current based on the analog target voltage from the driver circuitry; and a feedback current signal indicative of the intensity of the drive current produced by the output circuit.

4. The circuit of claim 3, wherein the feedback current signal is a down-scaled replica of the drive current flowing in the resistive heater element.

5. The circuit of claim 1, further comprising: a bias current generator coupled to the amplifier and configured to provide a bias current thereto, wherein the amplifier comprises a first input configured to receive the analog target voltage; and a resistive voltage divider coupled to a second input of the amplifier and to the heater drive node.

6. The circuit of claim 5, wherein the bias current generator is a programmable current generator.

7. The circuit of claim 5, wherein the resistive voltage divider has an equivalent series resistance greater than the resistance value of the resistive heater element.

8. The circuit of claim 5, wherein: the driver circuitry is configured to provide the drive current based on the analog target voltage with a respective slew rate; the output circuit is configured to control the respective slew rate of the drive current provided to the resistive heater element independently of the resistance value of the resistive heater element; and the output circuit is configured to control the respective slew rate of a voltage of the heater drive node based on a ratio of the bias current and a capacitance of the feedback capacitor.

9. The circuit of claim 1, wherein: the driver circuitry comprises a trans-linear circuit configured to receive the analog drive current intensity signal and to apply a current based on the analog drive current intensity signal to a reference resistor, and the analog target voltage is equal to a voltage drop across the reference resistor.

10. The circuit of claim 1, wherein: the resistive heater element is configured to be thermally coupled to a tip of a read/write head in a memory storage device; the read/write head is configured to have a spacing between the tip and a storage medium surface in the memory storage device; the spacing varies as a function of the power dissipated in the resistive heater element; and the power dissipated varies as a function of the intensity of the drive current provided to the resistive heater element.

11. The circuit of claim 1, wherein a slew rate of a voltage of the heater drive node is based on a capacitance of the feedback capacitor.

12. A memory storage device, comprising: a read/write head configured to have a spacing between a tip of the read/write head and a storage medium surface in the memory storage device, and the circuit according to claim 1 coupled to the read/write head, the circuit configured to control power dissipated in the resistive heater element, wherein the spacing varies as a function of the intensity of the drive current provided to the resistive heater element.

13. The memory storage device of claim 12, wherein the memory storage device comprises a hard-disk drive, HDD.

14. A circuit, comprising: an output transistor having an output node configured to be coupled to a heater resistor; an amplifier having an output coupled to a control node of the output transistor; a passive circuit element coupled between the output node of the output transistor and a first input of the amplifier; and a feedback capacitor coupled between the output of the amplifier and the output node of the output transistor.

15. The circuit of claim 14, wherein a slew rate of a voltage at the output node of the output transistor is based on a bias current of the amplifier and a capacitance of the feedback capacitor.

16. The circuit of claim 14, further comprising the heater resistor.

17. The circuit of claim 14, further comprising a translinear divider circuit coupled between a current input node and a second input of the amplifier, the translinear divider circuit configured to provide an output current proportional to a current provided at the current input node divided by a current flowing through the heater resistor.

18. The circuit of claim 17, further comprising a current digital-to-analog converter (DAC) coupled to the current input node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) One or more embodiments will now be described, by way of non-limiting example only, with reference to the annexed Figures, wherein:

(2) FIG. 1 shows a perspective view of an exemplary data storage device;

(3) FIG. 2 is a diagram exemplary of control circuitry operating the data storage device exemplified in FIG. 1;

(4) FIG. 3 is a diagram exemplary of principles underlying one or more embodiments;

(5) FIG. 4 is a block diagram exemplary of a fly-height control system as per the present disclosure;

(6) FIG. 5 is a circuit diagram exemplary of fly-height control circuitry as per the present disclosure;

(7) FIG. 6 is a block diagram exemplary of an alternative embodiment of a fly-height control system;

(8) FIG. 7 is a circuit diagram exemplary of an alternative embodiment of fly-height control circuitry as per the present disclosure; and

(9) FIGS. 8A and 8B are a time diagrams exemplary of evolution over time of signals in one or more embodiments.

(10) Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

(11) The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(12) In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

(13) Reference to an embodiment or one embodiment in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as in an embodiment or in one embodiment that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.

(14) Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(15) The drawings are in simplified form and are not to precise scale.

(16) Throughout the figures annexed herein, like parts or elements are indicated with like references/numerals unless the context indicates otherwise, and for brevity a corresponding description will not be repeated for each and every figure.

(17) The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

(18) For the sake of simplicity, in the following detailed description a same reference symbol may be used to designate both a node/line in a circuit and a signal that may occur at that node or line.

(19) In various embodiments, energy dissipated over time in resistive elements is controlled, for instance for/in data storage devices. One or more embodiments may be applied to control a read/write head of a data storage device, e.g., heating the head to maintain a fly-height or distance from a surface of the memory storage device. One or more embodiments may be applied to an amplifier stage of a hard-disk drive (HDD), for instance.

(20) As exemplified in FIG. 1, a data storage device 10 such as a hard disk drive, for instance, includes: at least one data storage disk 12 having a storage surface capable of storing data in a manner known per se, a spindle 14 comprising a respective spindle motor, the spindle 14 coupled to the storage disk 12 and configured to perform high-speed spinning thereof in response of actuation by the motor (not visible in FIG. 1); a read/write head 20 mounted on a positioning arm 22 and configured to read data from/write data to the storage disk 12; and an actuator 24 coupled to one end 26 of the positioning arm 22 opposite the read/write head 20, the actuator 24 configured to controllably swing the read/write head 20 into a desired position across the surface of the storage disk 12 as this is spinning driven via the motor of the spindle 14.

(21) As exemplified in FIG. 2, the storage device 10 comprises one or more storage disks attached to the same spindle 14 such that each storage disk 12 rotates at the same speed, as well as one or more read/write heads 20 and associated positioning arms 22 coupled to one or more actuators 24.

(22) As exemplified in FIG. 2, the storage device 10 further comprises control circuitry 100 (e.g., mounted on a housing of the HDD 10) configured to process data received from and supplied to the R/W head 20 and to control positioning of the read/write head 20 relative to the storage disk 12.

(23) For instance, the control circuitry 100 comprises electronic components mounted on a printed-circuit board (PCB), such as: a memory buffer 102, e.g., SDRAM, configured to temporarily host data to be read from/written to the disk, a system-on-chip (SoC) 110 comprising a hard-disk controller (HDC) 112 configured to produce (e.g., voice coil motor and spindle) control signals VCM, SC for actuating the positioning arm 26 and the motor of the spindle 14, respectively; the SoC 110 further comprises at least one R/W channel 114 configured to transfer data to/from each R/W head 20 of each disk 12 of the HDD 10, a motor controller 118 coupled to the HDC 112 and configured to receive the control signals VCM, SC therefrom, the motor controller 118 further configured to provide the control signals VCM, SC to the positioning arm 26 and the motor of the spindle 14, respectively, driving their actuation, and pre-amplifier circuitry 120 (e.g., mounted on flexible printed-circuit board inside the HDD 10) providing an interface between the SOC 110 and the R/W heads 20 to process the data for reading from/writing to the disks 12.

(24) For instance, the pre-amplifier 120 is configured to receive a digital control signal PHT (provided by the SoC 110, for instance) indicative of a desired value of energy dissipated over time (e.g., electrical power) in the resistive element RHT, e.g., onboard the R/W head(s) 20, as discussed in the following.

(25) It is noted that the particular arrangement of elements shown in FIGS. 1 and 2 is presented by way of illustrative example only. Those skilled in the art will recognize that a wide variety of other storage device configurations may be used in implementing embodiments of the invention.

(26) As exemplified herein, a memory storage device 10 (such as a hard-disk drive, HDD, for instance) includes: a read/write head 20 configured to have a spacing d between the tip 200 and a storage medium surface 12 in the memory storage device 10; and a circuit as exemplified herein coupled to the read/write head 20, the circuit configured to control electrical energy VHT (e.g., power or voltage) dissipated in the resistive heater element RHT over time, wherein the spacing d varies as a function of intensity of the drive current IHT provided to the resistive heater element RHT (e.g., the heater element RHT having a resistance ranging from tens to hundreds of Ohms and beyond).

(27) As exemplified in FIG. 3, the R/W head 20 comprises various components (known per se) such as a write element and/or a read element and a heater circuit RHT. For instance, the heater circuit comprises a resistive element RHT (e.g., referred to ground GND) placed near the R/W head 20 to dissipate a controlled energy over time in proximity thereof.

(28) As exemplified in FIG. 3, the surface of the storage disk 12 comprises a plurality of tracks for storing blocks of data in a magnetic layer below the surface of the disk 12. As exemplified in FIG. 3, such a surface may be non-planar, that is presenting peaks and valleys. For instance, the R/W head 20 comprises a tip 200 to read/write data blocks (in a manner per se known) that is driven to hover at a certain fly-height FH in order to counter the risk of collisions with track peaks and to facilitate reading magnetic tracks, e.g., by reducing magnetic spacing MS.

(29) In order to vary the fly-height FH, the pre-amplifier circuitry 120 comprises fly-height control circuitry 40 configured to vary a voltage VHT (and/or current I.sub.HT) signal provided to the resistive element RHT of the heater circuit.

(30) As exemplified in FIG. 3, (e.g., increased) heat produced due to (e.g., increased) energy/power dissipation in the resistive element RHT of the heater causes thermal expansion of the tip 200 of the R/W head 20, e.g., so that the head 20 protrudes by an amount d towards the disk 12. For instance, controlled actuation of the head 20 leads to setting a desirable fly-height FH in the range of few nanometers (1 nanometer=10.sup.9 m), e.g., in order to improve signal-to-noise ratio (SNR).

(31) As exemplified herein, the resistive heater element RHT is configured to be thermally coupled to a tip 200 of a read/write head 20 in a memory storage device 10, the read/write head 20 configured to have a spacing d between the tip 200 and a storage medium surface 12 in the memory storage device. For instance, the spacing d varies as a function of the (electrical) energy dissipated in the resistive heater element RHT, wherein the energy dissipated varies as a function of intensity of the drive current IHT provided to the resistive heater element RHT.

(32) FIG. 4 is a block diagram of a fly-height control system 40 according to the present disclosure.

(33) For instance, the fly height control system 40 controls a level of electric energy applied over time to the resistive heater element RHT (e.g., via controlling applied levels of electric voltage/current) based on the control signal PHT received at an input node and produces an output current flow IHT to provide to the resistive heater element RHT referred to ground GND via an output node VHT coupled thereto.

(34) As exemplified in FIG. 4, the fly-height control system 40 adjusts the output current IHT to control the energy/power applied to the resistive heater element RHT, thereby controllably adjusting the spacing between the read/write head 20 and a surface of the storage disk 12, as discussed above with reference to FIG. 3.

(35) As exemplified in FIG. 4, the fly-height control circuitry 40 includes: a digital-to-analog converter (DAC) 41 configured to (e.g., finely) convert a digital control signal PHT (provided by the SoC 110, for instance) to an analog current having a target current intensity value I_DAC, the digital control signal PHT being indicative of a setpoint value of electrical power/energy dissipated across the resistive element RHT of the R/W head 20; a divider circuit block 42, such as a divider, for instance, the divider circuit 42 having an input node coupled to the DAC 41 to receive therefrom the analog current I_DAC; optionally, the divider 42 has a further input node coupled to a slew rate (SR) control stage 46 to receive therefrom a feedback (current) signal I.sub.HT/N; as discussed in the following, the divider 42 is configured to provide as an output a target current (intensity) value I.sub.T based on the (intensity of the) target analog current I_DAC (preferably, based on a ratio of the analog current intensity I_DAC and the feedback current intensity I.sub.HT/N); a current-to-voltage converter 44 coupled to the divider 42 to receive the target current value I.sub.T therefrom, the current-to-voltage converter 44 configured to apply current-to-voltage conversion to the target current value I.sub.T, producing a target voltage (drop) value V.sub.T as a result; and a SR circuit block 46 having an input node coupled to the current-to-voltage converter 44 and an output node coupled to the heater resistive element RHT, the SR circuit block 46 configured to produce a (energy) voltage drop VHT across the resistive element RHT as a function of the target voltage value V.sub.T.

(36) As exemplified herein, the SR circuit block 46 is further configured to limit slew-rate of output voltage drop VHT, e.g., in order to limit interference between the heater circuit output and adjacent circuit blocks.

(37) As known to those of skill in the art, the term slew rate refers to a rate of variation of voltage or current (or any other electrical quantity) per unit of time.

(38) In one or more embodiments, the target voltage value V.sub.T provided to the SR stage 46 can have any slope (that is, any rate of variation in time) thanks to the slew-rate control being embedded in the same circuit block 46 that generates the voltage level VHT based on the target voltage value V.sub.T.

(39) As exemplified herein, a circuit includes: a resistive heater element RHT configured to produce heat based on an electric energy dissipated therein; a heater drive node VHT coupled to the resistive heater element to provide a drive current I.sub.HT thereto, wherein the energy dissipated in the resistive heater element RHT varies over time as a function of the intensity of the drive current provided to the resistive heater element; an input node configured to receive a digital control signal indicative of a target intensity of the drive current; and control circuitry 40 coupled to the input node and to the heater drive node, the control circuitry configured to vary the intensity of the drive current of the resistive heater element based on the digital control signal.

(40) As exemplified herein, the control circuitry includes: a digital-to-analog converter, DAC, 41 coupled to the input node to receive the digital control signal therefrom, the DAC configured to produce, based on the digital control signal, an analog current I_DAC having an analog target intensity value of the drive current; driver circuitry 42, 44 coupled to the DAC to receive therefrom the analog target intensity of the drive current, the driver circuitry configured to produce an analog target voltage V.sub.T; and an output circuit 46 coupled to the driver circuitry to receive therefrom the analog target voltage, the output circuit configured to produce the drive current provided to the resistive heater element based on the analog target voltage, wherein the driver circuitry is configured to produce the analog target voltage based on the analog target intensity from the DAC, and wherein the output circuit controls the energy dissipated in the resistive heater element independently of a resistance value of the resistive heater element.

(41) For instance, the driver circuitry is configured to provide the drive current based on the analog target voltage V.sub.T with a respective slew rate dVHT/dt, wherein the output circuit controls the respective slew rate of the drive current independently of a resistance value of the resistive heater element.

(42) As exemplified herein, the output circuit 46 is configured to produce: the drive current I.sub.HT based on the (variation of) analog target voltage V.sub.T from the driver circuitry 44; and a feedback current signal I.sub.HT/N indicative of the (intensity of the) drive current I.sub.HT produced by the output circuit.

(43) As exemplified in FIGS. 4 and 5, the DAC circuit block 41 comprises a current generator 41 configured to produce a (e.g., finely tuned) target analog current I_DAC that has a current intensity value proportional (e.g., by a gain constant Ko) to the input digital signal I_AN, e.g., to a decimal value of the digital code I_AN input to the DAC circuit 41.

(44) As exemplified in FIG. 5, the driver circuitry comprises a trans-linear circuit M1, M2, M11, M22 configured to receive the analog target current value I_DAC from the DAC 41 and to apply a current I.sub.T having an intensity based on the analog target current intensity I_DAC to a reference resistor R.sub.IV. For instance, the target analog voltage is equal to a voltage drop across the reference resistor R.sub.IV.

(45) As exemplified in FIG. 5, the divider circuit block 42 comprises (e.g., bi-polar or MOSFETs) transistors M1, M2, M11, M22 arranged (in a manner known per se) as a translinear cell, a first transistor M1 configured to receive the DAC current I_DAC, a second transistor M11 configured to receive the feedback current I.sub.HT/N, a third transistor M22 configured to receive a compensation current I_FIX and a fourth transistor M2 configured to provide a current I.sub.HT1 proportional (via a mirror factor, e.g., unitary in case transistors M23 and M33 have a same size) to the target current value I.sub.T.

(46) In an exemplary scenario, the target current intensity I.sub.T is obtained as a function of a ratio of the analog current intensity value I_DAC provided by the DAC 41 and the feedback current intensity value I.sub.HT/N provided by the SR circuit 46. For instance, the target current value I.sub.T is proportional to ratio of the analog current value I_DAC from the DAC 41 and the feedback current value I.sub.HT/N from the SR circuit 46, e.g., with a proportionality factor equal to the compensation current I_FIX, and it can be expressed as:
I.sub.T=I_DAC.Math.I_FIX.Math.N/I.sub.HT,
where N is any integer indicative of which fraction 1/N of the current I.sub.HT flowing in the resistive element RHT is used as feedback signal I.sub.HT/N.

(47) As exemplified herein, SR circuit 46 is configured to produce the feedback signal I.sub.HT/N, where integer N selectable to balance frequency domain behavior, precision and consumption of the circuit 46. For instance, increasing values of integer N (e.g., varying the area footprint of transistor M41, as discussed in the following), facilitates reducing consumption and area.

(48) As exemplified herein, the (intensity of the) feedback current I.sub.HT/N is a fraction or down-scaled replica of the (intensity of the) current flowing in the resistive heater element RHT, preferably down-scaled by an integer scale factor N.

(49) As exemplified in FIG. 5, the current-to-voltage converter 44 comprises a current mirror arrangement of a first transistor M23 and a second transistor M33 having respective (e.g., source) first transistor nodes coupled to a common supply voltage level VPLUS and respective (e.g., gate) control nodes coupled therebetween. For instance, the first transistor M23 in the converter 44 has a third (e.g., drain) transistor node coupled to the fourth transistor M2 in the trans-linear cell of the divider 42 to receive the target current I.sub.T while the second transistor M33 in the converter 44 has its respective third node coupled to a reference resistor R.sub.IV.

(50) As exemplified in FIG. 5, the target voltage value V.sub.T is equal to the voltage drop across the reference resistor R.sub.IV when target current I.sub.T flows therein via the mirror arrangement M23, M33.

(51) It is noted that in one or more embodiments the target current I.sub.T flowing in the reference resistance R.sub.IV can have any slope value, in contrast with existing solutions that use current generators with programmable (slope) profile in order to generate current variations within a limited (slope) range.

(52) As exemplified in FIG. 5, the output stage 46 comprises an operational amplifier circuit, op-amp, 460 coupled to a bias current generator I.sub.TAIL to receive a bias current therefrom, wherein the op-amp 460 includes: a first op-amp input node V.sub.T coupled to the driver circuitry 42, 44 to receive the target voltage (variation) V.sub.T therefrom; a second op-amp input node coupled to the output node VHT via a resistive voltage divider R1, R2, and an op-amp output node HT_CAP coupled to a control node of a transistor M44 configured to provide the drive current at the heater drive node VHT of the circuit 40; and a feedback capacitor CSR having a first capacitor end coupled to the op-amp output node HT_CAP and a second capacitor end coupled to the heater drive node VHT of the circuit 40 and to the second op-amp input node via the resistive voltage divider R1, R2.

(53) As exemplified in FIG. 5, the SR circuit block 46 includes: a first gain stage 460, e.g., an operational amplifier 460 operating with a (e.g., programmable) bias current I.sub.TAIL, the operational amplifier 460 having a first, e.g., inverting input node V.sub.T coupled to the current-to-voltage converter 44 to receive the target voltage level V.sub.T therefrom, the op-amp 460 having a second, e.g., non-inverting input node coupled to the heater resistance RHT to sense the output voltage VHT applied thereto, e.g., via a resistive voltage divider R.sub.1, R.sub.2, the op-amp 460 further having the output node HT_CAP coupled to the second input node and to the output node VHT of the fly-height control circuit 40 via a capacitor C.sub.SR; and a second gain stage M44, e.g., a pMOS or a pnp transistor known per se, coupled to an output node HT_CAP of the first amplifier stage 460 and in series with the heater resistive element RHT to provide an output current IHT thereto. In some embodiments, operational amplifier 460 may be implemented using amplifier circuits known in the art, such as an operational transconductance amplifier circuit.

(54) As exemplified in FIG. 5, resistive values of resistors in the feedback resistive voltage divider R.sub.1, R.sub.2 are selected to fix a ratio between the target voltage VT and the output voltage VHT, e.g., V.sub.T=VHT*R.sub.2/(R.sub.1+R.sub.2).

(55) As exemplified in FIG. 5, the second gain stage M44 is coupled to the divider 42 via a further transistor M41 to provide thereto (e.g., via current mirroring) a N-th fraction of the output current I.sub.HT as the feedback (current) signal I.sub.HT/N. For instance, the integer N may be selected by varying (e.g., increasing or reducing) a ratio between area footprint of the transistor M41 with respect to the other transistor M44 forming the current mirror arrangement.

(56) As exemplified in FIG. 5, the capacitor C.sub.SR forms a so-called Miller configuration with the output node HT_CAP of the op-amp 460 and the output node VHT of the fly-height control circuit 40. In this way, for instance, the capacitor C.sub.SR exploits the (per se known) Miller effect of the first gain stage 460, that is an increase in equivalent input capacitance of the op-amp 460 due to amplification of the effect of capacitance C.sub.SR having a first capacitor end coupled to the output node HT_CAP of the op-amp 460 and a second capacitor end coupled to the output node VHT of the fly-height control circuit 40.

(57) As exemplified in FIG. 5, the maximum current flow to charge/discharge the Miller capacitance C.sub.SR is equal to the tail current value I.sub.TAIL. As a result, for instance, the slew rate of the output signal I.sub.HT is controlled via the tail current I.sub.TAIL. Such a current, for instance, provides a bias of the input differential pair of the op-amp 460 (as illustrated in FIG. 5).

(58) In one or more embodiments, a selected (intensity) value of the programmable tail current I.sub.TAIL (e.g., selected based on the desired slope of the target current I.sub.T) determines a max intensity of a current flow through the output node of the op-amp to charge the Miller capacitance C.sub.SR (as illustrated in FIG. 5 by the solid arrow line near the VCC node) and discharge the Miller capacitance C.sub.SR (as illustrated in FIG. 5 by the dashed arrow line adjacent the capacitance C.sub.SR).

(59) As exemplified herein, the resistive voltage divider R.sub.1, R.sub.2 comprises resistive elements with an equivalent series resistance substantially greater than the resistance RHT (e.g., the latter could be within a range from tens up to hundreds of Ohms, or even more) of the resistive element RHT of the heater, e.g., (R.sub.1+R.sub.2)>>RHT. As a result, for instance, the bias current I.sub.TAIL flows directly in the resistance RHT of the heater when target energy (e.g., electric power or voltage) changes significantly.

(60) For instance, the resistive voltage divider R1, R2 has an equivalent series resistance greater than the resistance of the resistive heater element RHT.

(61) As exemplified herein, in response to an appreciable variation (e.g., increase or decrease) of the target voltage V.sub.T (and corresponding target energy/power PHT), the current I.sub.TAIL flows (directly) to (or from) the resistance RHT discharging (or charging) Miller capacitor C.sub.SR; this yields a slew rate SR equal to a ratio between tail current I.sub.TAIL and Miller capacitance C.sub.SR, e.g., SR=I.sub.TAIL/C.sub.SR. For instance, the output circuit is configured to control the respective slew rate of the output voltage based on a ratio of the bias current and a capacitance of the feedback capacitor.

(62) As exemplified in FIG. 5, for instance: output voltage VHT across the load resistance RHT has a value independent from the value of the load resistance RHT and can be expressed as VHT=V.sub.T*(1+R.sub.1/R.sub.2); output current I.sub.HT flowing in the load resistance RHT can be expressed as I.sub.HT=I_DAC*I_FIX*N/I.sub.T; reference resistance R.sub.IV can be expressed as R.sub.IV=V.sub.T/I.sub.T, so that an output energy over time (that is, power) P.sub.HT dissipated into the resistive load RHT has a value independent from the value of the load resistance RHT and can be expressed as:

(63) $P_{\mathrm{HT}}=I_{\mathrm{HT}}.Math.V\mathrm{HT}=I_{\mathrm{DAC}}.Math.\underset{}{I_{\mathrm{FIX}}.Math.N.Math.R_{\mathrm{iv}}.Math.\left(1+\frac{R_1}{R_2}\right).}$

(64) In one or more embodiments, as a result, a (e.g., variating) profile of the output current I.sub.HT (or voltage VHT) provided by the fly-height circuitry 40 can be controlled by programming the slew-rate of the first gain stage 460 in the SR circuit block 46.

(65) As exemplified in FIG. 5, the operational amplifier 460 preferably comprises an adjustable value of bias (or tail) current I.sub.TAIL, e.g., programmable using few selections (plus additional selections for fine-tuning or trimming, to facilitate reaching the target intensity value, for instance).

(66) For instance, the bias current generator I.sub.TAIL of the op-amp 460 is a programmable current generator.

(67) One or more embodiments, optionally, facilitate fine-tuning of bias current I.sub.TAIL of the operational amplifier 460 in the first gain stage of the SR circuit block 46, e.g., to compensate process variations towards fast or slow process corners, keeping the values of slew rate within a certain design range.

(68) As exemplified in FIG. 6, in an alternative scenario (such as a testing application, for instance) the circuitry 40 may be used without relying on the feedback current signal I.sub.HT/N, in a so-called voltage mode configured to control the voltage VHT applied to the resistive load RHT.

(69) For instance, the target current (intensity) I.sub.T is equal to (the intensity of) the analog current I_DAC provided by the DAC 41.

(70) As appreciable by visual comparison of the diagram exemplified in FIG. 6 with that of FIG. 4, operating the circuitry 40 in voltage mode comprises de-activating the current feedback loop from the SR circuit block 46 to the divider 42.

(71) As exemplified in FIG. 6, when operated in voltage mode, the DAC current intensity value I_DAC 41 is provided (directly) to the current-to-voltage converter 44, e.g., bypassing the divider 42. As a result, the target current IT has an intensity equal to the analog current intensity value I_DAC provided by the DAC circuit block 41, e.g., due to the compensation current I_FIX being turned off.

(72) FIG. 7 is a circuit diagram exemplary of an implementation of the alternative embodiment exemplified in FIG. 6, where like references indicate like elements to those discussed in the foregoing so that a corresponding description is not repeated for the sake of brevity.

(73) While not explicitly visible in FIG. 7, the tail current generator ITAIL can be present also in the SR circuit block 46 exemplified in FIG. 7, according to the same underlying principles discussed in the foregoing with reference to FIG. 5.

(74) As exemplified in FIGS. 8A and 8B, performing fly-height control of the head 20 of the HDD 10 using a control circuit 40 as exemplified in FIGS. 4 to 7 facilitates obtaining a flat time derivative dVHT/dt signal of the output voltage VHT across the load resistance RHT for any load resistance value. For instance, each line plotted in FIGS. 8A and 8B represents the behavior of the system for a selected one of the programmable tail current values I.sub.TAIL, corresponding to various slew-rate values.

(75) It will be otherwise understood that the various individual implementing options exemplified throughout the figures accompanying this description are not necessarily intended to be adopted in the same combinations exemplified in the figures. One or more embodiments may thus adopt these (otherwise non-mandatory) options individually and/or in different combinations with respect to the combination exemplified in the accompanying figures.

(76) Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection. The extent of protection is defined by the annexed claims.