In-memory arithmetic processors

Abstract

In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.

Claims

1. An in-memory arithmetic processor for receiving a first n-bit operand and a second n-bit operand of an arithmetic operation and generating a m-bit output number, the processor comprising: a memory array comprising memory cells arranged in p rows and q columns, pre-storing m-bit cell values of an arithmetic table used to define the arithmetic operation and generating a number q of m-bit cell values in response to an activated row driving signal associated with the second n-bit operand; and a column selector to select one from the number q of m-bit cell values in response to an activated column driving signal associated with the first n-bit operand to output the m-bit output number; wherein a number of the memory cells is associated with a number of the m-bit cell values; wherein each memory cell comprises a number m of unit cells in a row, wherein each unit cell comprises: a vertical first metal line connected to a digital voltage; a vertical second metal line connected to a ground node; a vertical metal bit line; and a first NMOS device, a source electrode of which is connected to the vertical metal bit line and a drain electrode of which is connected to one of the vertical first metal line and the vertical second metal line according to its corresponding bit value; wherein gate electrodes of the first NMOS devices in a row are connected together to form one of p wordlines in the memory array and receive its corresponding row driving signal.

2. The processor according to claim 1, further comprising: a first input circuitry to activate one of q column driving signals according to the first n-bit operand to respectively apply the activated column driving signal and (q-1) deactivated column driving signals to the column selector; and a second input circuitry to activate one of p row driving signals according to the second n-bit operand to respectively apply the activated row driving signal and (p-1) deactivated row driving signals to p wordlines of the memory array.

3. The processor according to claim 2, wherein the first input circuitry comprises: a first input register for storing the first n-bit operand; a first decoder connected to the first input register and having 2.sup.n first output nodes, wherein the first decoder activates one of the 2.sup.n first output nodes according to the first n-bit operand; and a column driver connected to the first decoder and supplying the activated column driving signal and the (q-1) deactivated column driving signals to the column selector according to the activated first output node.

4. The processor according to claim 2, wherein the second input circuitry comprises: a second input register for storing the second n-bit operand; a second decoder connected to the second input register and having 2.sup.n second output nodes, wherein the second decoder activates one of the 2.sup.n second output nodes according to the second n-bit operand; and a wordline driver connected to the second decoder and supplying the activated row driving signal and the (p-1) deactivated row driving signals to the p wordlines of the memory array according to the activated second output node.

5. The processor according to claim 1, wherein the column selector comprises q switches, and each switch comprises a number m of second NMOS devices in a row, and wherein gate electrodes of the second NMOS devices in a row are connected together to receive its corresponding column driving signal.

6. The processor according to claim 1, further comprising: an output register for storing the m-bit output number.

7. The processor according to claim 1, wherein the memory array is selected from the group comprising a SRAM array, a DRAM array, a ROM array and an non-volatile RAM array.

8. An in-memory arithmetic processor for receiving a first n-bit operand and a second n-bit operand of an arithmetic operation and generating a m-bit output number, the processor comprising: a memory array comprising memory cells arranged in p rows and q columns, pre-storing m-bit cell values of an arithmetic table used to define the arithmetic operation and generating a number q of m-bit cell values in response to an activated row driving signal associated with the second n-bit operand; and a column selector to select one from the number q of m-bit cell values in response to an activated column driving signal associated with the first n-bit operand to output the m-bit output number; wherein a number of the memory cells is associated with a number of the m-bit cell values; wherein each memory cell pre-stores a corresponding m-bit cell value in the arithmetic table with a size of 2.sup.n*2.sup.n, wherein if the arithmetic operation is a multiplication operation, the arithmetic table is a multiplication table and m=2*n, wherein if the arithmetic operation is an addition operation, the arithmetic table is an addition table and m=n+1, and wherein if the arithmetic operation is a subtraction operation, the arithmetic table is a subtraction table and m=n+1.

9. The processor according to claim 8, further comprising: a first input circuitry to activate one of q column driving signals according to the first n-bit operand to respectively apply the activated column driving signal and (q-1) deactivated column driving signals to the column selector; and a second input circuitry to activate one of p row driving signals according to the second n-bit operand to respectively apply the activated row driving signal and (p-1) deactivated row driving signals to p wordlines of the memory array.

10. The processor according to claim 9, wherein the first input circuitry comprises: a first input register for storing the first n-bit operand; a first decoder connected to the first input register and having 2.sup.n first output nodes, wherein the first decoder activates one of the 2.sup.n first output nodes according to the first n-bit operand; and a column driver connected to the first decoder and supplying the activated column driving signal and the (q-1) deactivated column driving signals to the column selector according to the activated first output node.

11. The processor according to claim 9, wherein the second input circuitry comprises: a second input register for storing the second n-bit operand; a second decoder connected to the second input register and having 2.sup.n second output nodes, wherein the second decoder activates one of the 2.sup.n second output nodes according to the second n-bit operand; and a wordline driver connected to the second decoder and supplying the activated row driving signal and the (p-1) deactivated row driving signals to the p wordlines of the memory array according to the activated second output node.

12. The processor according to claim 8, wherein the column selector comprises q switches, and each switch comprises a number m of second NMOS devices in a row, and wherein gate electrodes of the second NMOS devices in a row are connected together to receive its corresponding column driving signal.

13. The processor according to claim 8, further comprising: an output register for storing the m-bit output number.

14. The processor according to claim 8, wherein the memory array is selected from the group comprising a SRAM array, a DRAM array, a ROM array and an non-volatile RAM array.

15. An in-memory arithmetic processing method for receiving a first n-bit operand and a second n-bit operand of an arithmetic operation and generating a m-bit output number, the method comprising: pre-storing m-bit cell values of an arithmetic table used to define the arithmetic operation by a memory array comprising memory cells arranged in p rows and q columns; generating a number q of m-bit cell values by the memory array in response to an activated row driving signal associated with the second n-bit operand; and selecting one from the number q of m-bit cell values by a column selector comprising q switches in response to an activated column driving signal associated with the first n-bit operand to output the m-bit output number; wherein a number of the memory cells is associated with a number of the m-bit cell values; wherein each memory cell pre-stores a corresponding m-bit cell value in the arithmetic table with a size of 2.sup.n*2.sup.n, wherein if the arithmetic operation is a multiplication operation, the arithmetic table is a multiplication table and m=2*n, wherein if the arithmetic operation is an addition operation, the arithmetic table is an addition table and m=n+1, and wherein if the arithmetic operation is a subtraction operation, the arithmetic table is a subtraction table and m=n+1.

16. The method according to claim 15, further comprising: prior to the step of selecting and after the step of pre-storing, activating one of q column driving signals according to the first n-bit operand to respectively apply the activated column driving signal and (q-1) deactivated column driving signals to the q switches of the column selector.

17. The method according to claim 15, further comprising: prior to the step of generating and after the step of pre-storing, activating one of p row driving signals according to the second n-bit operand to respectively apply the activated row driving signal and (p-1) deactivated row driving signals to p wordlines of the memory array.

18. The method according to claim 15, wherein the memory array is selected from the group comprising a SRAM array, a DRAM array, a ROM array and an non-volatile RAM array.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made to the following drawings, which show the preferred embodiment of the present invention, in which:

(2) FIG. 1 shows the conventional Von-Neumann computing architecture for a typical Central Processing Unit (CPU).

(3) FIG. 2 shows the decimal multiplication table.

(4) FIG. 3 shows the decimal addition table.

(5) FIG. 4 shows the decimal subtraction table.

(6) FIG. 5 shows the n-bit by n-bit multiplication table according to this invention.

(7) FIG. 6 shows the n-bit by n-bit addition table according to this invention.

(8) FIG. 7 shows the n-bit by n-bit subtraction table according to this invention.

(9) FIG. 8 shows the schematics of an in-memory arithmetic processor including a 2.sup.n*2.sup.n memory array with two “n-bit” registers, two “n-bit” decoders and two drivers for implementing the n-bit by n-bit arithmetic tables according to this invention.

(10) FIG. 9 shows the schematic of “m-bit” ROM cells for storing a resultant binary code according to an arithmetic table cell selected from the memory array 850 according to an embodiment of the invention.

(11) FIG. 10 shows the schematic of 2.sup.n sets of Y-Switch for connecting a set of m-bit output bitlines to one of 2.sup.n sets of m-bit input bitlines according to an embodiment of the invention.

(12) FIG. 11 shows the 4-bit by 4-bit Multiplication Table according to an embodiment of the invention.

(13) FIG. 12 shows the 4-bit by 4-bit Addition Table according to another embodiment of the invention.

(14) FIG. 13 shows the 4-bit by 4-bit Subtraction Table according to another embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

(15) The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and element changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. Those of ordinary skill in the art will immediately realize that the embodiments of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure.

(16) To illustrate the main idea of the in-memory arithmetic processors 800, we apply a Read Only Memory (ROM) array for implementing the arithmetic tables in IC chips. Although the embodiment of the memory array 850 is described in terms of a ROM array, it should be understood that embodiments of the memory array 850 are not so limited, but are applicable to other types of memory arrays such as SRAM arrays, DRAM arrays, and Non-volatile RAM arrays.

(17) In the embodiment, the schematic of the ROM array 850 including the cells 900 of the arithmetic table is shown in FIG. 9. The ROM array 850 includes 2.sup.n-column by 2.sup.n-row arithmetic table cells 900. Each arithmetic table cell 900 is represented by a row of “m” ROM cells 910 for storing the “m-bit” of resultant codes. Each ROM cell 910 comprises an N-type Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) device 915, and two vertical metal lines 920 and 930 for applying digital voltages V.sub.SS and V.sub.DD, and one vertical output metal bitline 940. The source electrodes 903 of “m” NMOSFET devices 915 in the row are connected to their vertical bitlines 940, respectively. The gates 901 of the row of the NMOSFET devices 915 are connected to form a horizontal wordline W.sub.j 950. The drain electrode 902 of NMOSFET device 915 is connected to either cell's V.sub.SS line 920 for “0” or Cell's V.sub.DD line 930 for “1” in each ROM cell 910 by a metal contact 911. For example, the row of the “m-bit” ROM cells 910 represents the binary code of (01 . . . 00 . . . 11 b) as illustrated in FIG. 9. When a wordline W.sub.j 950 of the ROM cells 910 is activated “high”, the voltage signals of the entire row j of binary codes for 2.sup.n sets of m-bit codes pass to the 2.sup.n sets of “m” bitlines in the memory cell 850.

(18) Meanwhile the Y-Switch 830 comprises “2.sup.n” sets of switches 110 as shown in FIG. 10. In FIG. 10, each set of switches 110 comprises “m” NMOSFET devices. The gates of the “m” NMOSFET devices of each switch set 110 are connected to form a bitline switch BS.sub.i, which is connected to the Y-Switch Driver 822 for i=0, 1, . . . , (2.sup.n−1) as shown in FIG. 8. When one of the bitline switches BS.sub.i is activated, a corresponding set of the “m” NMOSFET devices is turned on to connect a corresponding set of bitlines 85BL to the output bitlines 83BL to pass the resultant “m-bit” code C.sub.ij stored in the (i+1).sup.th column and (j+1).sup.th row cell of the memory array 850 for i, j=0, 1, 2, . . . , (2.sup.n−1). Since the schematics and the operations of the registers 810/820 for bit-storage, the bit decoders 811/821, the wordline driver 812 and the Y-switch driver 822 are well known to the people skilled in the art, we will not address in many details.

(19) For the illustration purpose of using the conventional hexadecimal format, we will apply the 4-bit by 4-bit arithmetic operations for the embodiments (n=4). However, the numbers of bits for the arithmetic operation can be any integer number greater than 1. For the 4-bit by 4-bit multiplication, the resultant integer in the decimal format (upper) and its 8-bit representation in the hexadecimal format (lower) in each arithmetic table cell are shown in FIG. 11. According to the schematic in FIG. 8, we have the 4-bit decoder 821 decoding the 4-bit code A for the bitline switches of sixteen columns in the Y-switch 830 and the 4-bit decoder 811 decoding 4-bit code B for switching the wordlines of sixteen rows in the ROM array 850, and 16*16*8 ROM cells 910 of the ROM array 850. Every eight ROM cells 910 (m=8) in a row as illustrated in FIG. 9 stores the resultant 8-bit code C for the correspondent table cell of the 4-bit by 4-bit multiplication table in FIG. 11. Note the 8-bit code C represented in the hexadecimal format in the memory cell 85ij is implemented by connecting one of V.sub.DD for “1 s” and V.sub.SS for “0s” to the drain electrode 902 of NMOSFET device 915 by a metal contact 911 in each individual ROM cell 910 shown in FIG. 9. For example, 2*3=6=(06h)=(0000 0110b) connects the voltage biases (V.sub.SSV.sub.SSV.sub.SSV.sub.SSV.sub.SSV.sub.DDV.sub.DDV.sub.SS) to the drain electrodes 902 of each NMOSFET devices 915 by metal contacts 911 in the eight ROM cells 910 from the left to right for the correspondent memory cell 85ij for i, j=2, 3 (according to the binary code of the correspondent 4.sup.th-column and 5.sup.th-row cell in the 4-bit by 4-bit multiplication table in FIG. 11); 7*15=105=(69h)=(0110 1001 b) connects the voltage biases (V.sub.SSV.sub.DDV.sub.DDV.sub.SSV.sub.DDV.sub.SSV.sub.SSV.sub.DD) to the drain electrodes 902 of each NMOSFET devices 915 by metal contacts 911 in the 8 ROM cells 910 from the left to right for the correspondent memory cell 85ij for i, j=7, 15 (according to the binary code of the correspondent 9.sup.th-column and 17.sup.th-row cell in the 4-bit by 4-bit multiplication table in FIG. 11); 15*15=225=(e1h)=(1110 0001b) connects the voltage biases (V.sub.DDV.sub.DDV.sub.DDV.sub.SSV.sub.SSV.sub.SSV.sub.SSV.sub.DD) to the drain electrodes 902 of NMOSFET devices 915 by metal contacts 911 in the eight ROM cells 910 from the left to right for the correspondent memory cell 85ij for i, j=15, 15 (according to the binary code of the correspondent 17.sup.th-column and 17.sup.th-row cell in the 4-bit by 4-bit multiplication table in FIG. 11), and so forth for the rest of ROM cells 910.

(20) For the 4-bit by 4-bit addition, the resultant integer in the decimal format (upper) and its 5-bit representation (m=5) in the binary format (lower) in each table cell are shown in FIG. 12. According to the schematic in FIG. 8, we have the 4-bit decoder 821 decoding the 4-bit code A for the bitline switches of sixteen columns in the Y-switch 830 and the 4-bit decoder 811 decoding the 4-bit code B for switching the wordlines of sixteen rows in the ROM array 850 and 16*16*5 ROM cells 910 of the ROM array 850. Every five ROM cells 910 in a row as illustrated in FIG. 9 stores the resultant 5-bit code C including a “carry-over bit” for the correspondent table cell of the 4-bit by 4-bit addition table in FIG. 12. Note the 5-bit code C represented in the binary format in the memory cell 85ij is implemented by connecting either V.sub.DD for “1 s” or V.sub.SS for “0s” to the drain electrodes 902 of NMOSFET devices 915 by metal contacts 911 in the ROM cells 910 shown in FIG. 9. For example, 2+3=5=(0 0101b) connects the voltage biases (V.sub.SSV.sub.SSV.sub.DDV.sub.SSV.sub.DD) to the electrodes 902 of NMOSFET devices 915 by metal contacts 911 in the five ROM cells from the left to right for the correspondent memory cell 85ij for i, j=2, 3 (according to the binary code of the correspondent 4.sup.th-column and 5.sup.th-row cell in the 4-bit by 4-bit addition table in FIG. 12); 7+15=12=(0 1100b) connects the voltage biases (V.sub.SSV.sub.DDV.sub.DDV.sub.SSV.sub.SS) to the drain electrodes 902 of NMOSFET devices 915 in the five ROM cells from the left to right for the correspondent memory cell 85ij for i, j=7, 15 (according to the binary code of the correspondent 9.sup.th-column and 17.sup.th-row cell in the 4-bit by 4-bit addition table in FIG. 12); 15+15=30=(1 1110b) connects the voltage biases (V.sub.SSV.sub.DDV.sub.DDV.sub.SSV.sub.SS) to the drain electrodes 902 of NMOSFET devices 915 by metal contacts 911 in the five ROM cells 910 from the left to right for the correspondent memory cell 85ij for i, j=15, 15 (according to the binary code of the correspondent 17.sup.th-column and 17.sup.th-row cell in the 4-bit by 4-bit addition table in FIG. 12), and so forth for the rest of ROM cells 910.

(21) For the 4-bit by 4-bit subtraction, the resultant integer in the decimal format (upper) and its 5-bit representation (m=5) in the binary format in each table cell are shown in FIG. 13. According to the schematic in FIG. 8, we have the 4-bit decoder 821 decoding the 4-bit code A for the bitline switches of sixteen columns in the Y-switch 830 and the 4-bit decoder 811 decoding 4-bit code B for switching the wordlines of sixteen rows in the ROM array 850, and 16*16*5 ROM cells 910 of the ROM array 850. Every five ROM cells 910 in a row as illustrated in FIG. 9 stores the resultant 5-bit code C including a “sign” bit for the correspondent table cell of the 4-bit by 4-bit addition table in FIG. 13. Note the 5-bit code C represented in the binary format in the memory cell 85ij is implemented by connecting either V.sub.DD for “1 s” or V.sub.SS for “0s” to the drain electrodes 902 of NMOSFET devices 915 by metal contacts 911 in the ROM cells 910 shown in FIG. 9. For example, 2−3=−1=(1 0001b) connects the voltage biases (V.sub.DDV.sub.SSV.sub.SSV.sub.SSV.sub.DD) to the electrodes 902 of NMOSFET devices 915 by metal contacts 911 in the five ROM cells from the left to right for the correspondent memory cell 85ij for i, j=2, 3 (according to the binary code of the correspondent 4.sup.th-column and 5.sup.th-row cell in the 4-bit by 4-bit subtraction table in FIG. 13); 15-7=8=(0 1000b) connects the voltage biases (V.sub.SSV.sub.DDV.sub.SSV.sub.SSV.sub.SS) to the electrodes 902 of NMOSFET devices 915 by metal contacts 911 in the five ROM memory cells from the left to right for the correspondent memory cell 85ij for i, j=15, 7 (according to the binary code of the correspondent 17.sup.th-column and 9.sup.th-row cell in the 4-bit by 4-bit subtraction table in FIG. 13); 15-15=30=(0 0000b) connects the voltage biases (V.sub.SSV.sub.SSV.sub.SSV.sub.SSV.sub.SS) to the electrodes 902 of NMOSFET devices 915 by metal contacts 911 in the five ROM memory cells from the left to right for the correspondent memory cell 85ij for i, j=15, 15 (according to the binary code of the correspondent 17.sup.th-column and 17.sup.th-row cell in the 4-bit by 4-bit subtraction table in FIG. 13).

(22) The aforementioned description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiment disclosed. Accordingly, the description should be regarded as illustrative rather than restrictive. The embodiment is chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.