RADIO FREQUENCY DIGITAL-TO-ANALOG CONVERTER

Abstract

A radio frequency digital-to-analog converter comprising: a first stage converter, driven by a clock signal having a frequency F.sub.BB, configured to receive a digital baseband signal and to generate a number N parallel data streams, each having a first resolution; a serializer, driven by a clock signal having a frequency F.sub.s, configured to convert the number N parallel data streams into a serial data stream; and a second stage converter, configured to generate an analog up-converted RF signal based on the serial data stream, wherein the analog up-converted RF signal has a second resolution. The second stage converter comprises a number K slices in parallel, configured to each generate a respective portion of the analog up-converted RF signal, such that the second resolution matches the first resolution. Each slice of the number K slices comprises at least one analog delay element. F.sub.BB=F.sub.s/N; N is an integer, N>=1; K is an integer, K>=2.

Claims

1. A radio frequency digital-to-analog converter, RFDAC, comprising: a first stage converter, configured to receive a digital baseband signal and to generate a number N parallel data streams, each having a first resolution; a serializer, configured to convert the number N parallel data streams into a serial data stream; and a second stage converter, configured to receive the serial data stream, and to generate an analog up-converted radio frequency, RF, signal based on the serial data stream, wherein the analog up-converted RF signal has a second resolution; wherein the first stage converter is a digital Finite Impulse Response, FIR, filter; wherein the first stage converter is configured to be driven by a first clock signal having a first frequency F.sub.BB; wherein the serializer is configured to be driven by a second clock signal having a second frequency F.sub.s; wherein the second stage converter comprises a number K slices in parallel, at least some of the number K slices are configured to each generate a respective portion of the analog up-converted RF signal based on a unique part of the serial data stream, such that the second resolution matches the first resolution; wherein each slice of the number K slices comprises at least one analog delay element for shaping the respective portion of the analog up-converted RF signal; wherein F.sub.BB=F.sub.s/N; wherein N is an integer, and N>=1; and wherein K is an integer, and K>=2, preferably K>=4.

2. The RFDAC according to claim 1, wherein N>=2.

3. The RFDAC according to claim 1, wherein the first stage converter comprises a number N modules in parallel, each configured to generate a respective one of the number N parallel data streams.

4. The RFDAC according to claim 1, wherein the number N parallel data streams comprise data encoded by binary or thermometric coding.

5. The RFDAC according to claim 1, wherein the second resolution is equal to or different from the first resolution.

6. The RFDAC according to claim 1, wherein each slice of the number K slices has a respective weighting value for scaling a respective amplitude step of the respective portion of the analog up-converted RF signal.

7. The RFDAC according to claim 1, wherein each slice of the at least some of the number K slices is configured to generate the respective portion of the analog up-converted RF signal having a respective amplitude step; and wherein the analog up-converted RF signal is formed by combining the outputs of the at least some of the number K slices.

8. The RFDAC according to claim 1, wherein the at least one analog delay element is tunable or programmable.

9. The RFDAC according to claim 1, wherein any two slices of the number K slices have a same number or different numbers of analog delay elements and wherein any two analog delay elements of each slice are same or different.

10. The RFDAC according to 9, wherein any of the K slices that have a different number of analog delay cells and/or any of the K slices that have different analog delay elements are randomly selected during operation.

11. The RFDAC according to claim 1, wherein each analog delay element of the number K slices has a respective weighting value for an amplitude scaling.

12. The RFDAC according to claim 1, wherein each slice of the number K slices comprises a delay locked loop comprising the at least one analog delay element; and wherein the delay locked loop is configured to synchronize said slice to the second clock signal.

13. The RFDAC according to claim 1, wherein each slice comprises any of: a switched-capacitor digital-to-analog converter, sc-DAC, a switched-capacitor amplifier, and a Zero Order Hold, ZOH, analog FIR filter.

14. A radio frequency transmitter, comprising an RFDAC according to claim 1, configured to receive the digital baseband signal and to generate the analog up-converted RF signal for transmitting.

15. A digital-to-analog converting method, comprising: receiving a digital baseband signal and generating a number N parallel data streams each having a first resolution, by a first stage converter; converting the number N parallel data streams into a serial data stream, by a serializer; and receiving the serial data stream, and generating an analog up-converted RF signal based on the serial data stream, by a second stage converter, wherein the analog up-converted RF signal has a second resolution; wherein the first stage converter is a digital Finite Impulse Response, FIR, filter; wherein the first stage converter is configured to be driven by a first clock signal having a first frequency F.sub.BB; wherein the serializer is configured to be driven by a second clock signal having a second frequency F.sub.s; wherein the second stage converter comprises a number K slices in parallel, the method comprising: at least some of the number K slices each generating a respective portion of the analog up-converted RF signal based on a unique part of the serial data stream, such that the second resolution matches the first resolution; wherein each slice of the number K slices comprises at least one analog delay element, the method comprising: the at least one analog delay element shaping the respective portion of the analog up-converted RF signal; wherein F.sub.BB=F.sub.s/N; wherein N is an integer, and N>=1; and wherein K is an integer, and K>=2, preferably K>=4.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0084] The above, as well as additional objects, features, and advantages of the present description, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

[0085] FIG. 1 is a schematical view of an example RFDAC.

[0086] FIGS. 2A-2B are two examples of a first stage converter.

[0087] FIGS. 3A-3B are two examples of a serializer.

[0088] FIG. 4 illustrates operation principles of a serializer.

[0089] FIG. 5 is a schematical view of an example second stage converter.

[0090] FIGS. 6A-6B illustrate different weighting schemes for slices of a second stage converter.

DETAILED DESCRIPTION

[0091] In connection with FIG. 1, an example RFDAC will be discussed in detail.

[0092] The RFDAC comprises a first stage converter 1, a second stage converter 2, and a serializer 3 connecting to the first and second stage converter 1, 2.

[0093] An RF transmitter or transceiver may comprise the RFDAC for receiving a digital baseband signal and to generate an analog up-converted RF signal for transmitting by an antenna.

[0094] The first stage converter 1 is a digital Finite Impulse Response, FIR, filter. The first stage converter 1 is configured to receive a digital baseband signal as an input signal, and to generate a number N parallel data streams, each having a first resolution. N is an integer, and N>=1.

[0095] The first stage converter 1 is configured to be driven by a first clock signal having a first frequency F.sub.BB.

[0096] The first stage converter 1 is a digital Finite Impulse Response, FIR, filter.

[0097] Since the conversion performed by the first stage converter 1 is digital, which is fully configurable, the spectral performance of the RFDAC can be improved, and the inter-symbol interference (ISI) can be suppressed.

[0098] The serializer 3 is configured to receive and convert the number N parallel data streams into a serial data stream.

[0099] As shown in FIG. 1, the serializer 3 may be configured to convert the number N parallel streams of data into one serial data stream.

[0100] The serializer 3 may comprise a multiplexer or a switch.

[0101] The serializer 3 is configured to be driven by a second clock signal having a second frequency F.sub.s, wherein F.sub.BB=F.sub.s/N.

[0102] By using the serializer 3, multiple parallel slow sample rate data streams can be combined into one or more high speed data streams.

[0103] The first stage converter 1 and the serializer 3 may be implemented as a single module, driven by the first clock signal.

[0104] When N=1, since there is a single data stream feed into the serializer 3, the output and input of the serializer 3 may be the same.

[0105] The number N parallel data streams may comprise data encoded by binary or thermometric coding.

[0106] The second stage converter 2 is configured to receive the serial data stream, and to generate an analog up-converted radio frequency, RF, signal based on the serial data stream. The analog up-converted RF signal has a second resolution.

[0107] The second stage converter 2 comprises a number K slices in parallel, at least some of the number K slices are configured to each generate a respective portion of the analog up-converted RF signal based on a unique part of the serial data stream, such that the second resolution matches the first resolution.

[0108] Each slice of the number K slices comprises at least one analog delay element for shaping the respective portion of the analog up-converted RF signal. K is an integer, and K>=2, preferably K>=4.

[0109] A slice of a converter may refer to a portion or subsection of the converter, which may perform a part of the overall functionality of the converter, and collectively contribute to the conversion process.

[0110] Each slice may convert a part of the serial data stream into a part of the analog up-converted RF. The outputs of the number K slices may be summed or combined to form the analog up-converted RF signal.

[0111] Thus, the slices may be considered to contribute to the resolution of the analog up-converted RF signal. The higher the number of the slices for forming the analog up-converted RF signal, the higher the resolution of the analog up-converted RF signal.

[0112] Each slice may comprise multiple different components, such as one or more analog delay elements, amplifiers, mixers, etc. These components work together to convert a digital input into an analog up-converted RF output.

[0113] Having multiple slices may also allow for parallel conversion, which can increase the overall conversion speed and performance. The number K slices can be connected or configured in various ways depending on the specific design and requirements of the RFDAC.

[0114] The second stage converter 2 may be configured to be driven by the second clock signal having the second frequency F.sub.s, or a different clock signal having the second frequency F.sub.s.

[0115] The second stage converter may be configured to generate the analog up-converted RF signal by mixing with an RF carrier. The analog up-converted RF signal may be up-converted by a mixer (not shown) mixing with an RF carrier. Thus, the output signal of the second stage converter 2 is not an I/Q signal for transmitting by a I/Q transmitter.

[0116] As shown in FIG. 1, the second stage converter 2 may receive a RF clock signal having a frequency F.sub.RF.

[0117] The at least one analog delay element may be tunable or programmable.

[0118] A tunable analog delay element may be an analog device or circuit that introduces a controllable delay to an input signal by utilizing analog components. Since it allows an adjustable delay time, it is widely used in radar systems, telecommunication systems, and various electronic applications where precise control over signal delays is essential.

[0119] A programmable analog delay element may be a more advanced version of the tunable delay element. It can offer additional features and capabilities by allowing a user to program the delay time, e.g., remotely or through a control interface. The programmable analog delay element typically comprises a microcontroller to enable a precise and convenient control over the delay settings.

[0120] This is advantageous as an accurate, dynamic, and flexible control over the delay parameters can be achieved.

[0121] The second resolution may be equal to or different from the first resolution.

[0122] The term resolution is used to define the level of detail, e.g., of an image or of a signal. The higher the resolution, the more details are present, resulting in more detailed images or signals. In the present application, the term resolution is used to define the level of detail of a signal.

[0123] The first resolution may be characterized by the number of bits of data of the number N parallel data streams. For example, when the data is 5-bits, the first resolution of the parallel data stream may be 32 (2.sup.5). The resolution of the serial data stream may be different from the first resolution of the parallel data stream, as the serializer may skip one or more bits of the data of the parallel data streams.

[0124] The second resolution may be characterized by the number K, i.e. the number of slices, i.e. the number of portions for forming the analog up-converted RF signal.

[0125] For example, when K is selected to be 32 and all 32 slices respectively generate 32 portions for forming the analog up-converted RF signal, the analog up-converted RF signal has 32 amplitude steps (both amplitude increasing steps and decreasing steps). Thus, it is considered that the second resolution (the 32 portions) of the analog up-converted RF signal matches the first resolution (5-bits).

[0126] However, the first and second resolution do not need to be equal. For example, when the serializer 3 skips one bit of the parallel data streams (e.g., 5-bits), the serial data stream input to the second stage converter 2 is of e.g., 4-bits (51). Even if K is 32 and only 16 of the 32 slices are used to respectively generate 16 portions for forming the analog up-converted RF signa, it is still considered that the second resolution (the 16 amplitude steps) matches the first resolution (5-bits).

[0127] In other words, the number K is selected such that the resolution of the output analog up-converted RF signal matches the resolution of the input parallel data streams in a way that no information or very little amount of information is lost during the digital-to-analog conversion.

[0128] In FIG. 1, one example slice comprises a number L analog delay elements. L is an integer, and L>=1.

[0129] The pulse shape of the analog up-converted RF signal to be transmitted is important for its spectral performance. As any discontinuity of the pulse shape of a signal in the time domain would introduce unwanted noises in the frequency domain.

[0130] The analog delay elements of the slices may refine the pulse shape of the analog up-converted RF signal for improving spectral performance.

[0131] The analog delay elements may refine the pulse shape of the analog up-converted RF signal by interpolation. Interpolation may refer to a method of creating new data points based on a set of known data points to refine or smoothen a curve based on the set of known data points. One goal of interpolation is to create intermediate values between provided values. Examples of interpolation may include linear interpolation, polynomial interpolation, etc.

[0132] The present description also includes a digital-to-analog converting method. The digital-to-analog converting method can be implemented by the RFDAC of the present description.

[0133] The digital-to-analog converting method comprises: [0134] receiving a digital baseband signal and generating a number N parallel data streams each having a first resolution, by a first stage converter 1; [0135] converting the number N parallel data streams into a serial data stream, by a serializer 3; and [0136] receiving the serial data stream, and generating an analog up-converted RF signal based on the serial data stream, by a second stage converter 2, wherein the analog up-converted RF signal has a second resolution; [0137] wherein the first stage converter 1 is a digital Finite Impulse Response, FIR, filter; [0138] wherein the first stage converter 1 is configured to be driven by a first clock signal having a first frequency F.sub.BB; [0139] wherein the serializer 3 is configured to be driven by a second clock signal having a second frequency F.sub.s; [0140] wherein the second stage converter 2 comprises a number K slices in parallel, the method comprising: [0141] at least some of the number K slices each generating a respective portion of the analog up-converted RF signal based on a unique part of the serial data stream, such that the second resolution matches the first resolution; [0142] wherein each slice of the number K slices comprises at least one analog delay element, the method comprising: [0143] the at least one analog delay element shaping the respective portion of the analog up-converted RF signal; [0144] wherein F.sub.BB=F.sub.s/N; N is an integer, and N>=1; and K is an integer, and K>=2, preferably K>=4.

[0145] In connection with FIGS. 2A-2B, the first stage converter will be discussed in detail.

[0146] FIG. 2A illustrates an example first stage converter 1a when N=1.

[0147] The first stage converter 1a is a digital Finite Impulse Response, FIR, filter, configured to receive a digital baseband signal as input and to generate one data stream having a first resolution as output.

[0148] A digital FIR filter is a type of digital filter used to process digital signals. It is called Finite Impulse Response because the filter's response to an impulse input is finite in duration. An FIR filter operates by convolving the input signal with a finite and usually symmetric sequence of filter coefficients, often called the impulse response. These coefficients determine the overall frequency response of the FIR filter.

[0149] Using a digital FIR filter is advantageous as it can be easily designed to provide a clean output signal without introducing any distortion in the time domain, and to offer a better control over the frequency response characteristics.

[0150] In typical implementation, N>=2. FIG. 2B illustrates an example first stage converter 1b when N>=2.

[0151] As shown in FIG. 2B, the first stage converter 1b may comprise a number N modules in parallel, each configured to receive the same digital baseband signal, and to generate a respective one of the number N parallel data streams.

[0152] The serializer 3 in FIG. 2B is illustrated as a switch.

[0153] The switch may be configured to operatively connect to one of the number N parallel data streams at a time, from a first until a last data stream of the number N parallel data streams, to sequentially receive data from the number N parallel data streams. After connected to the last data stream, the switch may loop back to connect to the first data stream, and operatively connect from the first until the last data stream again, to sequentially receive data from the number N parallel data streams. Thus, the switch may perform the parallel to serial conversion by repeatedly sweeping over the number N parallel data streams.

[0154] In FIG. 2B, the number k refers to a depth of the digital FIR filter, which is different the number K representing the number of slices of the second stage converter 2.

[0155] FIGS. 2A-2B are only two examples of the first stage converter 1. The first stage converter 1 may be implemented differently.

[0156] In connection with FIGS. 3A-3B, the serializer 3 will be discussed in detail.

[0157] FIG. 3A is a schematical view of a basic 2:1 serializer for serializing two parallel data inputs into one serial data output.

[0158] In FIG. 3A, one latch is provided for the data input D.sub.0, and two latches are provided for the data input D.sub.1. A multiplexer is provided for selecting from the latched data of D.sub.0 and D.sub.1. The three latches and the multiplexer are controlled by a same clock signal clk.

[0159] Thus, by using latches and a multiplexer, the two parallel data inputs D.sub.0 and D.sub.1 can be serialized into one serial data output.

[0160] The 2:1 serializer of FIG. 3A can be used as a basic unit for building a serializer for serializing more than two parallel data inputs.

[0161] FIG. 3B is a schematical view of an 8:1 serializer for serializing eight parallel data inputs into one serial data output by using seven 2:1 serializers of FIG. 3A.

[0162] In a first level, four serializers are provided in parallel for respectively serializing two of the eight parallel data inputs D.sub.0 to D.sub.7. The first clock signal for driving these four serializers has a frequency CK2 (e.g., 0.5 GHz).

[0163] In a second level, two serializers are provided in parallel for respectively serializing four parallel data inputs (i.e. the outputs of the four serializers of the first level). The second clock signal for driving these two serializers has a frequency CK1 (e.g., 1 GHz), CK1=CK22.

[0164] In a third level, one serializer is provided for serializing two parallel data inputs (i.e. the outputs of the two serializers of the second level). The third clock signal for driving these two serializers has a frequency CK0 (e.g., 2 GHz), CK0=CK12.

[0165] The final output serial data stream has a frequency of CK, CK=CK02.

[0166] As shown in FIG. 3B, by cascading the 2:1 serializer of FIG. 3A, the 8:1 serializer of a higher serialization ratio can be achieved.

[0167] Further, the frequency of the final output serialized data steam of FIG. 3B (e.g., 4 GHz) is eight times of the frequency of the input parallel data D.sub.0-D.sub.7 (e.g., 0.5 GHz).

[0168] In connection with FIG. 4, operation principles of the serializer 3 will be discussed in detail.

[0169] FIG. 4 illustrates the number N parallel data streams D.sub.0, D.sub.1, D.sub.N-1, D.sub.N, which are input to the 4:1 serializer (not shown). In this example, N=4.

[0170] The serializer 3 using a speed higher than the data speed of the number N parallel data streams D.sub.0, D.sub.1, D.sub.N-1, D.sub.N, to fetch data from each of the number N parallel data streams D.sub.0, D.sub.1, D.sub.N-1, D.sub.N, and combine the fetched into a serial data stream in a sequential order. Thus, by increasing the data speed (frequency), the number N parallel data streams D.sub.0, D.sub.1, D.sub.N-1, D.sub.N can be combined into a serial data stream without losing any information.

[0171] In connection with FIG. 5, the second stage converter 2 will be discussed in detail.

[0172] Each slice of the at least some of the number K slices may be configured to generate the respective portion of the analog up-converted RF signal having a respective amplitude step.

[0173] The analog up-converted RF signal may be formed by combining the outputs of the at least some of the number K slices.

[0174] The analog up-converted RF signal may be formed by combining the outputs of the number K slices.

[0175] The amplitude step of the respective portion of the analog up-converted RF signal may be a maximum amplitude difference of said portion of the analog up-converted RF signal.

[0176] The amplitude step may be one least significant bit, LSB, step of the up-converted RF analog signal.

[0177] One slice of the second stage converter 2 of FIG. 5 comprises multiple analog delay elements connected in series. Thus, each of the analog delay elements may individually delay the input signal entering said analog delay element for a delay time. Further, each analog delay element is provided with an amplifier for increasing the amplitude of the input signal of said amplifier. All the delayed signals of a single slice may be summed together to form a portion of the analog up-converted RF signal. In other words, the analog delay elements and the amplifiers will work together to define the pulse shape (delay time and amplitude) of the portion of the analog up-converted RF signal for transmitting.

[0178] As shown in FIG. 5, the amplitude step of this slice may be refined into multiple tiny steps each having a duration of the delay time of the analog delay elements (assuming that the delay time is the same for each analog delay element).

[0179] Thus, the at least one analog delay element of the slice may provide an interpolation within the amplitude range of the amplitude step of said slice. In other words, instead of having number K of amplitude steps, the analog delay elements further refine the shape of the up-converted RF analog signal by interpolation.

[0180] Any two analog delay elements of each slice may be same or different.

[0181] Two same analog delay elements may have the same delay parameters such that they will cause the same delay time. In contrast, two different analog delay elements may have different delay parameters such that they will cause different delays in time.

[0182] Using different analog delay elements within one slice and/or between different slices may also improve spectral performance. Randomly changing a selected slice from slices with a different set of analog delay parameters for the analog delay elements may further improve the spectral performance and improve the performance in view of process, voltage and temperature variations.

[0183] Each analog delay element of the number K slices may have a respective weighting value for an amplitude scaling.

[0184] The weighting values for the analog delay elements of one slice may be e.g., 1, 2, 4, 8, 16 . . . . By providing a weighting value for each analog delay element, the RFDAC can be more flexible. This is also advantageous for shaping the analog signal.

[0185] The weighting value can be realized by the amplifier. The amplifier may comprise an inverter connected with a capacitor in series, as shown in FIG. 5.

[0186] The weighting values for any two analog delay elements of each slice may be the same or different.

[0187] Each slice of the number K slices may comprise a delay locked loop comprising the at least one analog delay element. The delay locked loop may be configured to synchronize said slice to a signal, e.g., the second clock signal.

[0188] The slice may be calibrated to synchronize with both the rising edge and the falling edge of said signal.

[0189] Any two slices of the number K slices may have a same number or different numbers of analog delay elements. For example, the number K slices may each comprise a same number L of analog delay element. For example, the number K slices may comprise different numbers of analog delay element each.

[0190] For example, any of the K slices that have a different number of analog delay cells and/or any of the K slices that have different analog delay elements are randomly selected during operation. Randomly changing a selected slice from slices with a different number of analog delay elements may further improve the spectral performance and improve the performance in view of process, voltage and temperature variations.

[0191] Each slice of the number K slices may comprise a delay locked loop comprising the at least one analog delay element. The delay locked loop may be configured to synchronize said slice to the second clock signal.

[0192] Each slice may be calibrated to synchronize with any of the rising edge and the falling edge of the second clock signal.

[0193] The slice may be implemented by a combination of a digital-to-analog converter (DAC) and a power amplifier (PA).

[0194] Each slice may comprise any of: [0195] a switched-capacitor digital-to-analog converter, sc-DAC, [0196] a switched-capacitor amplifier, and [0197] a Zero Order Hold, ZOH, analog FIR filter.

[0198] In connection with FIGS. 6A-6B, different weighting schemes for the number K slices will be discussed in detail.

[0199] Each slice of the number K slices may have a respective weighting value for scaling a respective amplitude step of the respective portion of the analog up-converted RF signal.

[0200] In FIG. 6A, three different weighting schemes are provided as examples. For example, the N parallel data streams each comprises data of 3-bit, and K=7.

[0201] A first example is the LSB thermos weighted, e.g., 1, 1, 1, 1, 1, 1, 1.

[0202] A second example is the binary weighted, e.g., 1, 2, 4.

[0203] A third example is the LSB+MSB weighted (row-column), e.g., 1, 2, 2, 2.

[0204] From FIG. 6B, the second resolution remains unchanged no matter which weighting scheme is used.

[0205] By using the RFDAC for converting the digital baseband signal to the analog up-converted RF signal, the noises can be suppressed over the spectrum. Further, by using the number K slices comprising at least one analog delay element for shaping the respective portion of the analog up-converted RF signal, the spectral performance can be further improved. Moreover, the RFDAC can be easily calibrated and manufactured.

[0206] In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.