METHOD FOR FABRICATING SILICON CHIP CARRIERS USING WET BULK MICROMACHINING FOR IR DETECTOR APPLICATIONS

Abstract

The invented method is to realize a silicon chip carrier using wet bulk micromachining of silicon. In the silicon chip carrier, three (or more) supports are realized solely based on the wet etching of the silicon. The fabricated supports are triangular in shape and provide a minimum contact area between the sensing element and carrier. The invention provides a simple, cost-effective fabrication technology, which uses anisotropic wet etchant for silicon bulk-micromachining. A fabricated silicon wafer can be diced as per the requirement of single/multiple channel IR detectors. These chip carriers will cut down the IR detector cost with attractive lower thermal conductance in the field of gas sensors, spectrometry, thermal imaging, and fire detection.

Claims

1-3. (canceled)

4. A method for fabricating a silicon chip carrier, the method comprising: generating a pre-etched pattern to precisely identify a first direction and a second direction to fabricate three triangular-shaped supports or more supports, wherein: the first direction is identified by a set of V-grooves in a particular angular direction; notches of the set of V-grooves are aligned in one straight line; and notches of all other V-grooves at angular directions other than the particular angular direction are misaligned; aligning precisely, with the pre-etched pattern and with a first desired mask layout on a first side of a silicon wafer and a second desired mask layout on an opposite side of the silicon wafer; and etching silicon from the first side and the second side of the silicon wafer by a wet bulk micromachining until silicon is completely etched in a center of the silicon wafer to realize the silicon chip carrier.

5. The method according to claim 4, wherein the three triangular-shaped supports minimize a contact area between the silicon chip carrier and detector elements to reduce a thermal conductance.

6. The method according to claim 4, wherein the three triangular-shaped supports are fabricated with tapered walls, the tapered walls at 54.7 and 45 on a top side of the silicon chip carrier and a bottom side of the silicon chip carrier and being configured for perfect step coverage during metal deposition by sputtering, e-beam evaporation, or thermal evaporation to form an electrical connection between metallic layers deposited on the top and the bottom sides of the chip carrier.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0009] The present invention is illustrated in FIG. 1 to 8 of the drawings accompanying this specification. In the drawings, reference numbers/letters indicate corresponding parts in the various figures.

[0010] FIG. 1 represents a flow chart for a fabrication method of a silicon chip carrier.

[0011] FIG. 2 represents circular patterns placed diagonally at 45 (w.r.t. direction [110]) at opposite ends of a silicon wafer side A (shown in a cross-section of a silicon wafer).

[0012] FIG. 3 shows pre-etched patterns generated from an array of circles after anisotropic etching.

[0013] FIG. 4 depicts a direction [100] in the fabricated pre-etched pattern.

[0014] FIG. 5 and FIG. 6 represent an image of mask layouts, designed to perform wet bulk micromachining from sides A and B of the silicon wafer respectively.

[0015] FIG. 7 and FIG. 8 shows scanning electron microscopy (SEM) images of the fabricated silicon chip carrier from side A and side B.

DETAILED DESCRIPTION

[0016] FIG. 1 represents a flow chart 1 in which a process begins with a double side polished silicon wafer 2 (as shown in FIG. 2), which is of orientation {100}. The thickness of the silicon wafer 2 is chosen according to a thickness of a pyroelectric element, which is to be accommodated on a chip carrier for IR detector fabrication. A layer of silicon dioxide (SiO.sub.2) or any other suitable masking material for wet bulk micromachining is grown/deposited on both sides of the silicon wafer 2. Photolithography is carried out to pattern a series of circles 2a and 2b diagonally over the silicon wafer 2 on side A. Anisotropic etching is performed using wet etchant (tetramethylammonium hydroxide: TMAH/potassium hydroxide: KOH/ethylene diamine pycocatechol: EDP) to generate pre-etched pattern 2a using which direction [100] is precisely identified as reported by Singh and Pal (Precise identification of the direction [100] on the silicon wafer 2 using a novel self-aligning pre-etched technique, J. Micromech. Microeng. 26 025012 (5 pp.) 2016). A suitable surfactant (like Triton-100/isopropanol: IPA) can be used to minimize the undercutting. With the help of selected pre-etched patterns (alignment marks), the patterning in a masking layer is carried out on the side A of the silicon wafer 2 using a mask layout 5 (as shown in FIG. 5) followed by patterning on side B of the silicon wafer 2 using a mask layout 6 (as shown in FIG. 6). Subsequently, silicon bulk micromachining is performed simultaneously (on both sides of the silicon wafer 2), till the time the silicon from both sides is completely etched in a center 5c of a carrier. Finally, the masking layer is etched/removed to achieve a silicon chip carrier 7. This silicon wafer 2 can be diced into single and multiple channels as per the requirement of the intended application.

[0017] Referring now to FIG. 2, for the identification of direction [100] and direction [110], the pre-etched technique proposed by Singh et al. 2016 is used. Usually, the primary cut along the direction [110] in the silicon wafer 2 is not accurate and typically has a 1-5 error. Therefore, for precise etching, it is necessary to identify the direction [100] and direction [110]. A set of four circles of 100 m diameter are designed at 45 in the mask. Their centers are in a straight line, passing through the center of the silicon wafer 2 on the side A. These circles are separated at a distance of 45.5 m, 44.5 m, and 43.5 m from each other in the radial direction. Furthermore, these circle patterns are repeated 24 times around the periphery on each side of the reference line at an angular interval of 0.16. A similar set of circles are also patterned on the diagonally opposite side of the silicon wafer 2. The required number of circles, their diameters, and their distances can vary depending on the accuracy of wafer flats in the silicon wafer 2.

[0018] Referring now to FIG. 3, after the anisotropic etching for a sufficient time, the circles 2a assume the shape of inverted pyramids 2a (or square V-Grooves), i.e, the pre-etched pattern. The direction [100] is identified by a set of V-grooves (in a particular angular direction) with their notches aligned in one straight line 2d. Whereas, in all other V-grooves at other angular directions, the notches are misaligned.

[0019] Referring now to FIG. 4, an optical snapshot of the generated pre-etched pattern shows the alignment of all notches generated from a particular set of four circles in a straight line 2d, which is the direction [100].

[0020] Referring now to FIG. 5, an edge 5a of the mask layout 5 is precisely aligned with pre-patterned alignment marks the straight line 2d, which is in the direction [100] and an edge 5b is automatically aligned in the direction [110]. Simultaneously, with the help of this alignment, the alignment marks on the side A are generated, which is to be used for patterning on a side B using a mask layout 6. The anisotropic etching using this mask layout 5 is performed to etch half the thickness of the silicon wafer 2 from the side A.

[0021] Similarly referring to FIG. 6, using the earlier generated alignment marks on side A, edges 6a and 6b are aligned with the direction [100] and the direction [110] respectively using the backside alignment (BSA) technique. The anisotropic etching using the mask layout 6 is performed to etch half the thickness of the silicon wafer 2 from the side B. After equal etching from both sides of the silicon wafer 2, the silicon is completely etched in center 5c. The silicon wafer 2 is diced (across dotted lines) as per the required number of channels. To realize a four-channel carrier, lines 6c, 6e, 6f, and 6h are used for dicing. Similarly, a two-channel carrier can be realized, either using a set of 6c, 6d, 6e, 6f, and 6h or a set of 6d, 6f, 6g, and 6h dicing lines. In the case of a single channel, dicing is carried out across all dicing lines namely 6c, 6d, 6e, 6f, 6g, and 6h.

[0022] After performing etching from both sides of the silicon wafer 2 using the mask layouts 5 and 6, FIG. 7 represents an SEM image of single-channel silicon chip carrier 7 with three triangular supports 7a, 7b, and 7c, fabricated using wet bulk micromachining. The corner near 7b indicates a {110} plane 7d at 45 and {111} plane 7e at 54.7. Similarly, at another corner, the {111} plane 7g is at 54.7 and {110} plane 7f is at 45. The planes 7h and 7i are fast etching planes generated due to undercutting at a convex corner, while etching.

[0023] FIG. 8 shows an SEM image of the side B of the fabricated silicon chip carrier. The {110} plane 8a is at 45 and {111} planes 8b and 8c are at 54.7. The planes 8d and 8e are fast etching planes generated after anisotropic etching from side B.

SUMMARY

[0024] The invention relates to the manufacturing of the silicon chip carrier 7 using micromechanical means, which is used as a support for pyroelectric elements in IR detector technology. Usually, these chip carriers are fabricated in the silicon wafer 2 through wet anisotropic etching using TMAH/KOH/EDP from one side and deep reactive ion etching (DRIE) from the other side of the silicon wafer to realize three or more supports for holding the pyroelectric detector element. The objective of this invention is to provide a simple, fast, cost-effective fabrication technology, which is solely based on wet etchants for silicon bulk-micromachining to realize the silicon chip carrier 7. The basic process of the carrier fabrication is to remove silicon from both sides of the silicon wafer 2 with controlled anisotropic etching to realize the three support points in silicon. These triangular-shaped support 7a, 7b, and 7c with minimum contact area (with pyroelectric sensing elements) are made through precise identification of direction [100] (at 45 angle w.r.t. direction [110]) in silicon wafer 2. The triangular-shaped supports 7a, 7b, and 7c minimize the contact area between the silicon chip carrier 7 and detector elements to reduce thermal conductance. Usually, the primary/secondary flats of supplied silicon wafers have an inaccuracy of 1-5 and therefore cannot be relied upon for precise identification of the direction [100]. Therefore, pre-etched patterns are created in the silicon wafer 2. After pre-etching, amongst the generated patterns a set self-aligns across direction [100] while other sets are misaligned. The plane shown in the 7d, 7f, and 8a is oriented at an angle of 45 to the wafer surface and appears along the direction [100]. The generated pre-etched patterns are used as alignment marks and help to perform etching at the plane at 45, which leads to the fabrication of triangular-shaped supports with tapered walls for a mounting pyroelectric chip. These tapered walls at 45 and 54.7 on a top and bottom sides in the silicon chip carrier 7 help in perfect step coverage during metal deposition using sputtering, e-beam evaporation, and thermal evaporation to form an electrical connection between the metallic layers deposited on the top and the bottom sides of the silicon chip carrier 7. The identified [100] directed pre-etched patterns are used for photolithography on both sides of the silicon wafer 2 followed by wet silicon bulk micromachining to realize the silicon chip carriers 7. The silicon wafer 2 can be diced as per the requirement to obtain single/multiple channel IR detectors. These chip carriers help in cutting down the cost of the miniaturized single/multi-channel pyroelectric IR detectors and offer attractive lower thermal conductance.

[0025] Thus, summarizing the present invention, the present invention provides a method for the fabrication of the silicon chip carrier 7. The method comprises generating the pre-etched pattern 2a to precisely identify the direction [100] and the direction [110] to fabricate three triangular supports 7a, 7b, and 7c, or more supports. Further, aligning precisely with the pre-etched pattern 2a, and with the mask layouts 5 and 6 on sides A and B of a silicon wafer 2, silicon wet bulk micromachining is carried out from the side A and side B of the silicon wafer 2 to realize the silicon chip carrier 7.

[0026] Further, some examples have been provided below to provide more clarification on the present invention:

Example 1

[0027] A method for silicon chip carrier 7 based solely on silicon wet bulk micromachining has been developed for IR detector applications. Silicon wafer-3 of 3-inch diameter, 340 m thickness, 1-20 ohm-cm resistivity and orientation {100}0.50 has been used for the process. After generating the pre-etched pattern on side A of the silicon wafer 2, out of the 49 sets of V-grooves, the notches of the pattern at the 28.sup.th position (clockwise from primary flat) are found aligned in the 2d i.e. direction [100]. The patterning using mask layouts 5 and 6 was carried out on side A and side B respectively for realizing the 2.95 mm2.95 mm single chip carriers to accommodate the 2 mm2 mm pyroelectric detector element. Silicon etching in TMAH (25% wt) along with surfactant Triton X-100 (0.1%) is carried out at 90 for 285 minutes simultaneously from both sides of the wafer. The SEM image of fabricated silicon chip carrier 7 has been captured from side A and side B.

Example 2

[0028] A method for fabricating silicon chip carrier 7 based solely on silicon wet bulk micromachining has been developed for IR detector applications. Another silicon wafer-5 of 3-inch diameter, 337 m thickness, 1-20 ohm-cm resistivity and orientation {100}0.50 has been used for the process. In generated pre-etched pattern on side A, the notches of the pattern at the 21.sup.st position (clockwise from primary flat) out of the 49 sets of V-grooves are in a straight line 2d in direction [100]. After patterning using layouts 5 and 6 on side A and side B respectively, silicon etching in TMAH (25% wt) along with surfactant Triton X-100 (0.1%) is carried out at 90 for 283 minutes on both sides of wafer to fabricate the 2.95 mm2.95 mm single chip carriers to hold 2 mm2 mm pyroelectric detector element. The SEM image of fabricated silicon chip carrier 7 confirms that the silicon chip carrier is of the same dimensions as obtained in Example 1.