MESSAGE-BASED PROCESSOR WITH TRANSMISSION DISABLING MODE

Abstract

A message-based processor has at least one processor cluster. The processor cluster includes a plurality of processor cluster elements. Each processor cluster element has an operational mode indicator that indicates an operational mode of the processor cluster element, such as a transmission disabling operational mode and a transmission enabling operational mode. In some examples, the message-based processor sets a particular processor cluster element of the plurality of processor cluster elements to the transmission disabling operational mode and transmits, with a delay, a re-enable control message to the particular processor cluster element to reassume the transmission enabling operational mode.

Claims

1. A message-based processor comprising at least one processor cluster, the at least one processor cluster comprising a plurality of processor cluster elements, each processor cluster element of the plurality of processor cluster elements having an operational mode indicator that indicates an operational mode of the processor cluster element, the operational mode being one of a plurality of operational modes comprising a transmission disabling operational mode and a transmission enabling operational mode, the message-based processor storing instructions that, when executed, cause the message-based processor to perform operations comprising: setting a particular processor cluster element of the plurality of processor cluster elements to the transmission disabling operational mode; and transmitting, with a delay, a re-enable control message to the particular processor cluster element to reassume the transmission enabling operational mode.

2. The message-based processor of claim 1, wherein each processor cluster element of the plurality of processor cluster elements further has a state value that indicates a state of the processor cluster element.

3. The message-based processor of claim 2, the operations further comprising: receiving an input message that identifies the particular processor cluster element; and updating the state value of the particular processor cluster element.

4. The message-based processor of claim 3, the operations further comprising, before setting the particular processor cluster element to the transmission disabling operational mode: determining that the particular processor cluster element is in the transmission enabling operational mode; and based on determining that the particular processor cluster element is in the transmission enabling operational mode, causing transmission of one or more output messages from the particular processor cluster element to one or more other processor cluster elements of the plurality of processor cluster elements.

5. The message-based processor of claim 2, the operations further comprising: while the particular processor cluster element is in the transmission disabling operational mode, continuing to update the state value of the particular processor cluster element in response to one or more input messages.

6. The message-based processor of claim 1, the operations further comprising: disabling transmission of an output message targeting the particular processor cluster element at least until the particular processor cluster element receives the re-enable control message.

7. The message-based processor of claim 1, wherein the re-enable control message comprises a state value of the particular processor cluster element at a time of transmission.

8. The message-based processor of claim 7, the operations further comprising: determining that the state value has transgressed a predetermined change threshold; and in response to determining that the state value has transgressed the predetermined change threshold, initiating generation of one or more output messages.

9. The message-based processor of claim 8, wherein determining that the state value has transgressed the predetermined change threshold is based on a binary value of a state value change indicator for the particular processor cluster element.

10. The message-based processor of claim 1, the operations further comprising: comparing a current time with a timestamp of an oldest message in a FIFO message buffer for re-enable control messages; determining that at least one of a plurality of conditions is met, the plurality of conditions comprising that a predetermined period of time has elapsed between the oldest message and the current time, and that the FIFO message buffer is full; and in response to determining that at least one of the plurality of conditions is met, delivering the oldest message.

11. The message-based processor of claim 1, the operations further comprising: dynamically controlling a duration of the delay associated with the re-enable control message.

12. The message-based processor of claim 2, wherein the at least one processor cluster represents a neural network with neural elements, and wherein the state value represents an action potential.

13. The message-based processor of claim 12, wherein the particular processor cluster element executes a particular neural element of the neural elements, the operations further comprising: selectively transmitting an output message based on the action potential of the particular neural element having transgressed a predetermined change threshold.

14. The message-based processor of claim 1, comprising a plurality of the processor clusters.

15. A method performed by a message-based processor comprising at least one processor cluster, the at least one processor cluster comprising a plurality of processor cluster elements, each processor cluster element of the plurality of processor cluster elements having an operational mode indicator that indicates an operational mode of the processor cluster element, the operational mode being one of a plurality of operational modes comprising a transmission disabling operational mode and a transmission enabling operational mode, the method comprising: setting a particular processor cluster element of the plurality of processor cluster elements to the transmission disabling operational mode; and transmitting, with a delay, a re-enable control message to the particular processor cluster element to reassume the transmission enabling operational mode.

16. The method of claim 15, wherein each processor cluster element of the plurality of processor cluster elements further has a state value that indicates a state of the processor cluster element.

17. The method of claim 16, the operations further comprising: receiving an input message that identifies the particular processor cluster element; and updating the state value of the particular processor cluster element.

18. The method of claim 17, the operations further comprising, before setting the particular processor cluster element to the transmission disabling operational mode: determining that the particular processor cluster element is in the transmission enabling operational mode; and based on determining that the particular processor cluster element is in the transmission enabling operational mode, causing transmission of one or more output messages from the particular processor cluster element to one or more other processor cluster elements of the plurality of processor cluster elements.

19. One or more non-transitory computer-readable media storing computer-executable instructions that, when executed by a message-based processor, cause the message-based processor to perform operations, the message-based processor comprising at least one processor cluster, the at least one processor cluster comprising a plurality of processor cluster elements, each processor cluster element of the plurality of processor cluster elements having an operational mode indicator that indicates an operational mode of the processor cluster element, the operational mode being one of a plurality of operational modes comprising a transmission disabling operational mode and a transmission enabling operational mode, the operations comprising: setting a particular processor cluster element of the plurality of processor cluster elements to the transmission disabling operational mode; and transmitting, with a delay, a re-enable control message to the particular processor cluster element to reassume the transmission enabling operational mode.

20. The one or more non-transitory computer-readable media of claim 19, wherein each processor cluster element of the plurality of processor cluster elements further has a state value that indicates a state of the processor cluster element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] These and other aspects are described in more detail with reference to the drawings. Therein:

[0012] FIG. 1 schematically shows a message-based processor that comprises at least one processor cluster;

[0013] FIGS. 2 and 3 shows an exemplary processor clusters in more detail;

[0014] FIG. 3 shows an exemplary processor cluster in more detail;

[0015] FIG. 4A, 4B shows examples of message handling utilities involved in conveying transmission re-enable messages;

[0016] FIG. 5 shows a first example of a method disclosed herein;

[0017] FIG. 6 shows a second example of a method disclosed herein;

[0018] FIG. 7 shows a more detailed example of a portion of an embodiment of a processor clusters;

[0019] FIG. 8 shows aspects of other embodiments of the method.

DETAILED DESCRIPTION OF EMBODIMENTS

[0020] Terminology used for describing particular embodiments is not intended to be limiting of the invention. As used herein, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term and/or includes any and all combinations of one or more of the associated listed items. It will be understood that the terms comprises and/or comprising specify the presence of stated features but do not preclude the presence or addition of one or more other features. It will be further understood that when a particular step of a method is referred to as subsequent to another step, it can directly follow said other step or one or more intermediate steps may be carried out before carrying out the particular step, unless specified otherwise. Likewise it will be understood that when a connection between structures or components is described, this connection may be established directly or through intermediate structures or components unless specified otherwise.

[0021] The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. In the drawings, the absolute and relative sizes of systems, components, layers, and regions may be exaggerated for clarity. Embodiments may be described with reference to schematic and/or cross-section illustrations of possibly idealized embodiments and intermediate structures of the invention. In the description and drawings, like numbers refer to like elements throughout. Relative terms as well as derivatives thereof should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the system be constructed or operated in a particular orientation unless stated otherwise.

[0022] FIG. 1 schematically shows a message-based processor 1 that comprises at least one processor cluster 10, here also processor clusters 10a, . . . , 10h. Each of the processor clusters has a plurality of processor cluster elements a, . . . , j, . . . , n.

[0023] By way of example a processor cluster 10 is shown in more detail in FIG. 2. As shown therein, processor cluster elements a, . . . , j, . . . , n, have a respective addressable storage space 110a, . . . , 110j, . . . , 110n to store a state value Xj indicative for their state. Furthermore, common control utilities, computation utilities 140 and message handling utilities 20, 25, 120, 130, are provided in the processor cluster 10. In this embodiment the common control utilities and the common computation utilities are provided by a general purpose processor 140. Alternatively, separate means may be present, such as a sequencer to function as a common control utility and a signal processor to function as the common computation utility. Such a signal processor may for example be a general purpose processor, but may alternatively be a processor dedicated to perform specific signal computations, for example implemented in dedicated hardware.

[0024] The common computation utilities 140 are configured, for example upon receipt of a message Mj addressing a processor cluster element j, to retrieve a previous state X.sub.n,j of a processor cluster element j stored in its addressable storage space 110j, and to replace this with the updated state X.sub.n+1,j. The common computation utilities 140 are also configured to instruct the message output unit 130 with a signal Fj to send one or more output messages Mout.

[0025] The message handling utilities comprise a network interface 25 which is connected by a link 20 to a network used by the processor clusters 10, 10a, . . . , 10h to communicate with each other. The message handling utilities further include a message input unit 120 to receive input messages Min and a message output unit 130 to transmit output messages Mout. In addition the message handling utilities comprise a respective dedicated message transfer line 27, 27a, . . . , 27h for each processor cluster 10, 10a, . . . , 10h. If the message-based processor 1 only comprises one processor cluster 10, or if message exchange only needs to take place within one processor cluster 10, the network may be absent, and messages can be passed directly from the message output unit 130 to the message input unit 120.

[0026] The message input unit 120 is configured to receive input messages Min that designate specific ones of the plurality of processor cluster elements and the computation utilities 140 are configured to update a state value stored in the respective storage element of the designated processor cluster element.

[0027] The addressable storage space of each processor cluster element e.g. storage space 110j for a processor cluster element j further stores an operational mode indicator OMj that is indicative for a currently prevailing operational mode of that processor cluster element j. The operational mode OMj is selected from at least one of a first operational mode OME, wherein transmission is enabled and a second operational mode OMD, wherein transmission is disabled. The message output unit 130 is configured to selectively transmit output messages for a processor cluster element to one or more processor cluster elements (e.g. to itself and/or to an processor cluster element in the same processor cluster, or another processor cluster) dependent on its operational mode.

[0028] The transmission disabling mode OMD is a temporary operational mode, in that the common control utilities upon setting a processor cluster element to the transmission disabling mode also transmit with delay a re-enable control message to that processor cluster element. Upon receipt of the re-enable control message the processor cluster element reassumes the transmission enable mode OME.

[0029] In the embodiment of FIG. 2, the message handling utilities 120, 130, 20, 25 both serve to handle update messages to update a state of a processor cluster element designated therein and re-enable control messages. FIG. 3 shows an alternative embodiment wherein a separate message buffer unit 27 is provided to deliver re-enable control messages. In operation the message buffer unit 27 receives through the message output unit 130 a re-enable control message from a processor cluster element, e.g. j, that designates itself and delivers it to the message input unit 120 with a predetermined delay. It is noted that computation and control utilities 140 may control the duration T of the delay with a control signal Ct for example based on input data indicative for a network load and a required precision indicator.

[0030] FIG. 4A shows a first example of a message buffer unit 27. The message buffer unit 27 comprises a FIFO-buffer 270, a FIFO-buffer controller 271 and a time stamp section 272. In the example shown, the FIFO-buffer 270 contains buffered re-enable control messages, of which message M2.sub.k having a time stamp T2.sub.k is the oldest. Once a time T, indicated by a clock, here included in the time stamp section 272 is equal to the value of the time stamp T2.sub.k of the oldest message, the FIFO-buffer controller 271 issues an output enable control signal O.sub.en that causes the FIFO-buffer 270 to deliver the buffered re-enable message M2.sub.k to the message input unit 120. In the embodiment shown, the time stamp section 272 assigns the time-stamp to the received messages. For example the message M2.sub.k+m received from the message output unit 130 is provided with a time stamp T2.sub.k+m, which contains a time value equal to the current time of the day augmented with the predetermined delay time. In other embodiments a time-stamp unit may be included in the message output unit 130 instead.

[0031] In practice the buffer space available in FIFO-buffer 270 can be designed to be sufficient to hold the re-enable messages for the predetermined delay time. Nevertheless an alternative embodiment is provided in FIG. 4B that provides a fallback operation for the exceptional case that the FIFO-buffer 270 is fully occupied. In this alternative embodiment, the FIFO-buffer controller 271 issues the output enable signal O.sub.en if either the time stamp of the oldest message has a value equal to the current time, or if the FIFO-buffer indicates that it is full with the signal F.sub.full. In the examples of FIG. 4A, 4B, the control signal Ct can be used for used for example to control the delay in that the assigned timestamp has the value T (current time)+T as a function of the control signal Ct. Therewith the point in time that a re-enable message is released from the FIFO can be shifted to a controllable extent into the future.

[0032] FIG. 5 schematically shows an embodiment of a method for operating a message-based processor comprising at least one processor cluster with a plurality of processor cluster elements and common control utilities computation utilities and message handling utilities for the processor cluster elements. The message-based processor operated with the method is for example one of the embodiments of the message-based processor as describe above.

[0033] As shown therein, the method comprises a step S1A, or S1B of receiving an input message, e.g. with message input unit 120, that designates a specific one of the plurality of processor cluster elements. In step S1A the received message is an update message M1. An update message M1 may include further data in addition to the designation of the processor cluster element, such as an indication of an operation to be applied and an indication of one or more operand values. This is however not mandatory. Alternatively, in a step S1B, a re-enable message M2 may be received. As will be described in more detail below, the receipt of the message has the effect that the common computation utilities update the state value X stored of the designated processor cluster element. As set out above, the processor cluster 10 has a plurality of processor cluster elements a, . . . , j, . . . n. Accordingly for each of these processor cluster elements a respective state value is stored. For simplicity the state value Xj of the processor cluster element j that is designated by the message M1 or M2 is indicated as X. Upon receipt of a message M1 in step S1A, the common computation utilities 140 first compute a preliminary updated state value X, which is stored in a shared register. The computation may be controlled by control data, e.g. an opcode and one or more operands in the message M1, but that is not necessary. An embodiment may be contemplated wherein the update message M1 merely contains the designation of the processor cluster element and always has the same effect, e.g. adding a predetermined value to the state value.

[0034] Upon receipt of a re-enable message M2, the state value X of the designated processor cluster element is stored as the preliminary updated state value X, and subsequently the state value X is assigned the value (M2.StatVal) which is conveyed by the message M2.

[0035] In subsequent steps S3-S5 a quantized state change value O is computed as follows. In step S3 a quantized state value Xq is computed from the value X stored as the current state value of the designated processor cluster element. In this example this is achieved by a shift right operation with THR bits and returning the integer value of the result. The same operation is performed in step S4 for preliminary updated state value X, to obtain the quantized preliminary updated state value Xq. In step S5, the quantized state change value O is computed as the difference between the activation function value AF(Xq) for the quantized preliminary updated state value Xq and the activation function value AF(Xq) for the quantized state value Xq.

[0036] In step S6 it is determined whether or not the quantized state change value O differs from 0. If the quantized state change value O is equal to 0, the operational state OM of the designated processor cluster element is subsequently checked in step S7. Each processor cluster element has a proper storage space for its operational state. The required storage space is a single bit, unless the operational mode of a processor cluster element needs to be selected from more than two potential operational modes. The storage space for storing the operational mode indicator OM may for example be part of the storage space reserved for the state value X, e.g. an addressable memory entry 110j for processor cluster element j. Upon determining that the operational mode OM is the enabled operational mode OME, the method continues with step S10, wherein the preliminary updated state value X is stored as the state value X for the designated processor element. In case that the operational mode OM is the disabled operational mode OMD and confirming in step S8 that the received message is not a re-enable message, the method also continues with step S10. If in the disabled operational mode it is determined in step S8 that the received message is a re-enable message then the operational mode of the designated processor element is set as enabled operational mode in step S9, and procedure continues with step S10.

[0037] If it is determined in step S6 that the quantized state change value O differs from 0, the operational mode OM of the designated processor cluster element is subsequently checked in step S11. If the operational mode is the disabled operational mode OMD, and it is determined in step S12 that the received message is not a re-enable message, the method continues with step S10. If the operational mode is the enabled operational mode OME, or if it is determined in step S12 that the received message is a re-enable message and re-enabling in step S13, the method continues with step S14, wherein an update message MIO, indicative of the quantized state change value O is transmitted by the designated processor element to one or more destination processor cluster elements, which may include itself, one or more other processor cluster elements in the same cluster or in another cluster. The message may be transmitted for example by message output unit 130. Subsequent said transmission, in step S15 the common control utilities 140 reset the operational state of the designated processor cluster element to disabled OMD. Also, in step S16, a re-enable control message M2 is transmitted to the designated processor cluster element with a delay AT, as schematically indicated by the dashed arrow in FIG. 5, and the method continues with step S10. As described above, receipt of the message M2 by the designated processor element enables it to reassume the transmission enable mode OME, e.g. in step S9, or in step S13.

[0038] FIG. 6 shows an alternative embodiment of the method. Steps therein corresponding to those in FIG. 5 have the same reference number. As becomes apparent from FIG. 6, the procedure followed in this alternative embodiment corresponds to the one until step S17. In step S17, it is checked whether or not the following combination of conditions is complied with: [0039] O0 (the quantized state change value O differs from 0) [0040] OM=OME (Transmission enabled mode)
If these both conditions are complied with, the transmission enable mode OM is set disabled (OMD) in step S15, and the transmission re-enable message M2O(X) carrying the current state value X is transmitted in step S16.

[0041] Subsequent to step S16, or subsequent to step S17 if it is determined therein that the combination of conditions is not complied with, it is verified in step S12 whether or not a transmission re-enable message M2 was received. If this is not the case the method continues with step S10. If indeed a transmission re-enable message M2 was received, the operational mode OM is switched to OME in step S13. Therewith the processor element is enabled to transmit an update message M1O in step S14, provided that it is determined in step S6 that the quantized state change value O differs from 0.

[0042] FIG. 7 schematically illustrates a possible implementation of a common utilities that may perform the method of FIG. 6. By way of example, the common update and control utilities are currently active for a processor cluster element j having its state indicator X and its operational mode indicator OM stored in an addressable entry 110j of a memory 110 (indicated as a double walled box). In the example shown, the common message handling utilities comprise message receiving utilities 120, with a first control module 120M1 and a second control module 120M2. Upon receipt of an input message M1 by the message receiving utilities the first control module 120M1 activates an update module 1402 with control signal L1 to compute an updated state value X from the value indicated by the state indicator X in entry 110j and a value indicated by the message. E.g. the update module 1402 may compute:

X=X+W*V, wherein

W is a weight currently assigned to the processor cluster element j, and V a value conveyed by the message M1. Alternatively other update functions may be performed by the update module 1402, for example addition with a fixed value.
The value computed by update module 1402 is (temporarily) stored in a register 1404. With a second control signal L2, the first control module 120M1 activates a computation module 1406 to compute a quantized state change value O, for example in accordance with steps S3, S4, S5 in FIGS. 5 and 6. In response to the computation module 1406 having computed the value for the quantized state change value O, a comparator 1408 determines whether the value O differs from 0. Also another comparator 1410 determines whether the operational mode indicator OM stored in entry 110j indicates that transmission is enabled (OME). If the output of AND-gate 1412 indicates that these both conditions are complied with, then disable module 1414 resets the indicator in the transmission enable indicator OM in entry 110j to transmission disabled (OMD). Also in that case, the transmission module 130M2 transmits a message M2(X) with the state value X stored in entry 110j. Control signal L3 from control module 120M1 then causes the storage module 1409 to save the update value X in the storage entry 110j reserved for the processor cluster element j.

[0043] Upon receipt by the message handling utility 120 of message M2(X) after the predetermined delay, the control module 120M2 initiates the following operations. With a signal RF1 it causes module 1416 to copy the current state value X stored in entry 110j into the register 1404. Then with a signal RF2, it stores the state value conveyed by the message M2 into that entry 110j. With control signal RF3, it causes computation utility 1406 to compute the quantized state change value O on the basis of the value conveyed by the message M2, now stored in entry 110j and the value stored in the register 1404. In response to the computation module 1406 having computed the value for the quantized state change value O, the comparator 1408 determines whether the value O differs from 0. Control module 120M2 further provides a control signal RF4 to AND-gate 1418. This control signal indicates message M2 received=TRUE. If further the comparator 1408 has determined that the value for the quantized state change value O differs from 0 the AND-gate causes signal transmission module 130M1 of the signal handling utilities 130 to issue a message M1(O) conveying quantized state change value O. The message may be transmitted by the designated processor element to one or more destination processor cluster elements, which may include itself, one or more other processor cluster elements in the same cluster or in another cluster. Finally control module 120M2 issues signal RF4 to storage module 1409 to write the temporary updated state value X into the addressable storage space 110j for the relevant cluster processor element j.

[0044] The method as described in FIG. 5 and FIG. 6, may be extended to respond to other message types and to additional message parameters. Examples thereof are presented in FIG. 8. Steps therein corresponding to those in FIG. 5 and FIG. 6 have the same reference. Accordingly, upon receipt of a message M2, the same step S2B is performed as in FIG. 5, and FIG. 6 and the method proceeds from point A in FIG. 5 or FIG. 6 onwards.

[0045] If a message M1 is received, then step S2A is performed, wherein the temporary updated state value X is computed. Then, as an additional step S20 it is determined whether a control parameter Trig conveyed by the message M1 is TRUE. If this is not the case, then the method proceeds as usual from point A in FIG. 5 or FIG. 6 onwards. However, if the control parameter Trig is True, it resets the quantized state value Xq in step S21, and continues from point B in FIG. 5 or FIG. 6 onwards. This implies that the quantized state change value O is in fact the quantized state value O of the updated value computed in step S2A. Therewith the processor cluster element addressed by the message M1 will communicate an absolute indicator of its state instead of a relative indicator of its state.

[0046] As shown also in FIG. 8, the method may be configured to handle a third type of messages M3, for example associated with a separate input port. Upon receipt of a message M3, the method may for example perform a specific operation, such as a reset operation S23 or a leakage operation S24. In the example shown, either of these operations can be performed dependent on the value of the parameter Trigg. For one value (0) of this parameter, the operation Reset is performed. Therewith the state value is reset to a bias value. The method then continues at point C in FIG. 5 or 6, wherein the computed bias value is stored into the state register (e.g. 110j of a processor cluster element j). In case the parameter Trigg has another value (1), a leakage operation is performed. This operation mimics the behavior of a neuron of which the excitation state gradually drops to 0 in the absence of input.

[0047] In an embodiment the operations in steps S2A, S23, S24 may be based on a scale function. I.e. the following is computed:

In step S2A: X=X+Scale((WZP)*V,SC)=X+SC*V(WZP)

In step S23: X=Scale((WZP),SC)=SC*(WZP)

In step S24: X=XScale((XW),SC)=XSC*(XW)

In this way, the dynamic range of the cluster can be adapted to the input by the choice of the values for the parameters ZP and SC.

[0048] In interpreting the appended claims, it should be understood that the word comprising does not exclude the presence of other elements or acts than those listed in a given claim; the word a or an preceding an element does not exclude the presence of a plurality of such elements; any reference signs in the claims do not limit their scope; several means may be represented by the same or different item(s) or implemented structure or function; any of the disclosed devices or portions thereof may be combined together or separated into further portions unless specifically stated otherwise. Where one claim refers to another claim, this may indicate synergetic advantage achieved by the combination of their respective features. But the mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot also be used to advantage. The present embodiments may thus include all working combinations of the claims wherein each claim can in principle refer to any preceding claim unless clearly excluded by context.