Highly Physical Ion Resistive Spacer To Define Chemical Damage Free Sub 60nm Mram Devices

Abstract

A magnetic tunneling junction (MTJ) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same the second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.

Claims

1. A device comprising: a stack of magnetic tunneling junction (MTJ) layers, the stack of MTJ layers including a first portion having a first width and a second portion having a second width that is different than the first width, the second portion disposed over the first portion of the stack of MTJ layers; a first metal re-deposition layer disposed directly on a surface of the first portion of the stack of MTJ layers; a second metal re-deposition layer disposed directly on a surface of the second portion of the stack of MTJ layers; and a dielectric layer extending from the second metal re-deposition layer to the first metal re-deposition layer.

2. The device of claim 1, wherein the first portion of the stack of MTJ layers includes a pinned layer and tunnel barrier layer, and wherein the second portion of the stack of MTJ layers includes a free layer and a first electrode layer.

3. The device of claim 2, wherein the first metal re-deposition layer is disposed directly on the pinned layer and the tunnel barrier layer, and wherein the second metal re-deposition layer is disposed directly on the free layer and the first electrode layer.

4. The device of claim 2, further comprising a second electrode layer, and wherein the second electrode layer has a third width that is different than the first and second widths.

5. The device of claim 1, further comprising a spacer disposed directly on the dielectric layer.

6. The device of claim 5, wherein the dielectric layer is disposed between the spacer and the first and second metal re-deposition layers thereby preventing the spacer from interfacing with either of the first and second metal re-deposition layers.

7. The device of claim 5, further comprising a metal contact interfacing with the spacer, the dielectric layer, the second metal re-deposition layer and the second portion of the stack of MTJ layers.

8. The device of claim 5, wherein the spacer includes a carbon containing material.

9. A device comprising: a stack of magnetic tunneling junction (MTJ) layers, the stack of MTJ layers including a first portion and a second portion; a first metal re-deposition layer disposed directly on a first side of the first portion of the stack of MTJ layers; and a second metal re-deposition layer disposed directly on a second side of the second portion of the stack of MTJ layers, the first side of the first portion of the stack of MTJ layers and the second side of the second portion of the stack of MTJ layers facing the same direction, wherein the second metal re-deposition layer is electrically isolated from the first metal re-deposition layer.

10. The device of claim 9, further comprising: a first dielectric layer disposed directly on the first metal re-deposition layer and the second metal re-deposition layer; and a second dielectric layer disposed directly on the first metal re-deposition layer without being disposed directly on the second metal re-deposition layer.

11. The device of claim 10, further comprising a spacer feature disposed between the first dielectric layer and the second dielectric layer such that the spacer feature interfaces with both the first dielectric layer and the second dielectric layer.

12. The device of claim 11, wherein the spacer feature includes an aluminum containing material.

13. The device of claim 11, wherein neither of the first and second metal re-deposition layers interface with the spacer feature.

14. The device of claim 9, wherein the stack of MTJ layers includes a first electrode layer and a second electrode layer, and wherein the first metal re-deposition layer is disposed directly on the first electrode layer and wherein the second metal re-deposition layer is disposed directly on the second electrode layer.

15. The device of claim 9, further comprising a metal contact disposed directly on the stack of MTJ layers and the second metal re-deposition layer.

16. A device comprising: a first electrode; a pinned layer on the first electrode, the pinned layer having a first width; a barrier layer on the pinned layer, the barrier layer having a second width, a first metal re-deposition layer on sidewalls of at least one of the barrier layer and the pinned layer, a free layer on the barrier layer, the free layer having a third width, the third width being different than at least one of the first and second widths; a second electrode on the free layer; a second metal re-deposition layer on sidewalls of at least one of the free layer and the second electrode; and a first dielectric layer disposed between the first and second metal re-deposition layers thereby electrically isolating from the first metal re-deposition layer from the second metal re-deposition layer.

17. The device of claim 16, wherein the first metal re-deposition layer is on sidewalls of both the barrier layer and the pinned layer, and wherein the second metal re-deposition layer is on sidewalls of both the free layer and the second electrode layer.

18. The device of claim 16, further comprising a spacer feature disposed on and interfacing with the first dielectric layer, the spacer feature including a material selected from the group consisting of a carbon containing material and an aluminum containing material.

19. The device of claim 16, further comprising a second dielectric layer disposed on and interfacing with the first metal re-deposition, the first dielectric layer and the spacer feature.

20. The device of claim 16, wherein the first and second widths are greater than the third width.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the accompanying drawings forming a material part of this description, there is shown:

[0011] FIGS. 1 through 8 illustrate in cross-sectional representation steps in a preferred embodiment of the present disclosure.

DETAILED DESCRIPTION

[0012] In the present disclosure, a spacer assisted pure physical etch can create chemical damage free MTJ sidewalls and also eliminate conductive metal re-deposition induced shorted devices. More specifically, the free layer is physically etched by pure Ar RIE or IBE, then covered by a spacer. Next, the pinned layer is physically etched using the spacer as a hard mask. The spacer material can be made of carbon or TaC, which is highly resistant to this type of etch, thus ensuring that enough of the spacer remains to protect the free and barrier layers. This method is particularly useful for high density sub 60 nm MRAM devices, where chemical damage and re-deposition on the MTJ sidewall become very severe for these smaller MRAM chips.

[0013] In a typical MRAM fabrication process, the whole MTJ stack consisting of free, barrier, and pinned layers is patterned by one single step etch, either by chemical RIE or physical IBE. It therefore creates either chemical damage or physical shorts on the MTJ sidewall. However, in the process of the present disclosure, we firstly etch the free layer by pure Ar RIE or IBE, cover it with a highly physical etch resistant spacer, and then etch the pinned layer by pure Ar RIE or IBE using the spacer as a hard mask. By this method, both issues are solved simultaneously, greatly enhancing the device performance.

[0014] The preferred embodiment of the present disclosure will be described in more detail with reference to FIGS. 1-8. FIG. 1 illustrates a bottom electrode layer 12 formed on a semiconductor substrate, not shown. Now, the MTJ stack, comprising at least a pinned layer 14, a tunnel barrier layer 16, and a free layer 18, are deposited on the bottom electrode. A top electrode 20 comprising Ta, TaN, Ti, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni or their alloys is deposited over the MTJ stack to a thickness h1 of 10-100 nm, and preferably 50 nm. A dielectric hard mask 22 of SiO.sub.2, SiN, SiON, SiC or SiCN is deposited on the top electrode to a thickness of 20 nm. Finally a photoresist mask 24 is formed over the hard mask 20 forming pillar patterns with size dl of approximately 70-80 nm and height h2 of 200 nm.

[0015] Now, as shown in FIG. 2, the hard mask 22 is etched by a fluorine carbon based plasma such as CF.sub.4 or CHF.sub.3 alone, or mixed with Ar and N.sub.2. O.sub.2 can be added to reduce the pillar size further to d2 of about 50-60 nm.

[0016] Next the top electrode is etched by RIE or IBE, followed by a pure Ar RIE or IBE etch of the free layer. If RIE is used to etch the top electrode, the top electrode and free layer etching must be in separate steps since RIE causes chemical damages and cannot be applied to the free layer. If IBE is used, the top electrode and free layer can be etched by one single etch step using the same recipe. The free layer etch step can stop at the interface between the free layer 18 and the tunneling barrier 16 or within the tunneling barrier. Because of the nature of a physical etch, there is no chemical damage after this etching step, but only a thin layer of conductive metal re-deposition 26 on the free layer's sidewall, as shown in FIG. 3.

[0017] The photoresist 24 is stripped away by oxygen alone or mixed with N.sub.2 or H.sub.2O. Then, as illustrated in FIG. 4, an encapsulation layer 28, made of Al.sub.2O.sub.3, SiON, or SiN, is deposited over the partially etched MTJ stack and the bottom electrode by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) to a thickness of 5-30 nm. The deposition may be either in-situ or ex-situ. This non-conductive encapsulation layer will protect the free layer from shorting by encapsulating the conductive metal re-deposition 26.

[0018] Now, as shown in FIG. 5, a spacer material layer 30 is deposited over the encapsulation layer 28. The spacer material 30 is carbon, TaC, or Al which has a very low etch rate under physical etching. The spacer material layer 30 is deposited in-situ or ex-situ by CVD, PVD, or ALD to a thickness of 10-30 nm.

[0019] Next the portion of the spacer layer 30 that is on horizontal surfaces is etched away by RIE, leaving spacers 32 having a thickness of 5-20 nm only on the sidewalls of the pattern, as shown in FIG. 6. Dependent on the material that is used for the spacer, different plasmas can be used for this step. For example, O.sub.2 can be applied for carbon, fluorine carbon such as CF.sub.4 or a Halogen such as Cl.sub.2 can be used for TaC, and a Halogen such as Cl.sub.2 can be used for Al .

[0020] Referring to FIG. 7, using the spacer 32 left on the encapsulated free layer sidewall as a self-aligned hard mask, the barrier layer 16 and pinned layer 14 are etched by the same type of physical etch as was used to etch the free layer. By doing this, one can again avoid forming any chemical damage layer but only generate a thin layer of conductive metal re-deposition 34 on the pinned layer's sidewall. Since the pinned layer is thin, the re-deposition from it would not cover the whole spacer but at most the bottom portion of the spacer 32. Here it should be noted that, as shown in Table 1, carbon's IBE etch rate is only ˜60 A/s, much lower than those commonly used metals in the MTJ hard mask and stack, which are usually larger than 200 A/s. That is, the spacer's etch rate would be ⅓ the etch rate of the pinned layer. Therefore after this etch step, enough of the spacer 32, ≤1 nm, would remain to protect the encapsulated free layer.

TABLE-US-00001 TABLE 1 Summary of various materials' IBE etch rate in Angstroms/minute (from http://www.microfabnh.com/ion_beam_etch_rates.php) Etch Rate Material (A/min) Ag 1050 Al 48 Au 630 AZ 1350 117 C 64 CdS 1283 Co 262 Cr 309 Cu 513 Fe 204 Si 216 SiC 204 Si02 192 Hf 385 InSb 887 Ir 344 Ge 537 Mg 131 Mn 507 Mo2C 163 Nb 274 Ni 309 NiCr 309 Pb 1517 PbTe 2199 Pd 642 Rb 2333 Re 303 Rh 420 Riston 14 146 Ru 356 Sb 1889 Ni80Fe2O 292 Ni 309 Zr 332 Ta 245 Ta2O5 350 TaC 87 TaN 233 Ti 192 Ti or TiW 195 W 198 Y 554 Zr 332

[0021] The re-deposition from the free and pinned layer etches, 26 and 34, respectively, are separated by the encapsulation 28 and spacer 32 materials, without forming a continuous path to short the devices. This approach is of particular use for sub 60 nm MRAM devices where the spacer has to be thin enough to maintain the pattern geometry for the self-aligned etch, but still be capable of protecting the previously defined free layer. Another benefit of this spacer etch is that the pinned layer has a larger volume than the free layer, about 50-60 nm for the pinned layer and about 40-50 nm for the free layer, so that the pinned layer has strong enough pinning strength to stabilize the magnetic state in the free layer.

[0022] After the pinned layer etch, the whole device can be filled with dielectric material 36 and flattened by chemical mechanical polishing (CMP) to expose the top electrode 20, as shown in FIG. 8. The remaining spacer 32 on the sidewall can stay within the structure without affecting the device integrity and device performance. A top metal contact 38 contacts the top electrode 20.

[0023] The process of the present disclosure employs a physical etch to eliminate chemical damage on the MTJ sidewall and prevents the conductive re-deposition from shorting the devices. It has been considered to be difficult to achieve these two results simultaneously, but the process of the present disclosure provides these results.

[0024] The process of the present disclosure will be used for MRAM chips of size smaller than 60 nm as problems associated with chemically damaged sidewalls and re-deposition from the bottom electrode become very severe for these smaller sized MRAM chips.

[0025] Although the preferred embodiment of the present disclosure has been illustrated, and that form has been described in detail, it will be readily understood by those skilled in the art that various modifications may be made therein without departing from the spirit of the disclosure or from the scope of the appended claims.