LOADLINE MODULATION POWER MANAGEMENT CIRCUIT

Abstract

A loadline modulation power management circuit is provided. The loadline modulation power management circuit includes a power amplifier circuit and an acoustic filter circuit. Specifically, the power amplifier circuit is configured to amplify a signal to a time-variant output power based on a modulated voltage and the acoustic filter circuit is configured to pass the amplified signal for transmission in a transmit frequency. Herein, the power amplifier circuit is further configured to dynamically modulate a loadline impedance based on the time-variant output power to prevent the modulated voltage from exceeding a maximum level, whereas the acoustic filter circuit can help reduce overall transmit loss in the amplified signal. As a result, the loadline modulation power management circuit can operate with optimal efficiency and with reduced overall transmit loss.

Claims

1. A loadline modulation power management circuit comprising: a power amplifier circuit, comprising: a differential amplifier always activated and configured to: receive an envelope tracking (ET) voltage having a dynamic range defined by a minimum voltage level and a maximum voltage level; and amplify a signal from a time-variant input power to a time-variant output power that is inversely related to a default loadline impedance based on the ET voltage; and a single-ended amplifier activated when the time-variant output power is higher than or equal to a threshold level to reduce the default loadline impedance to thereby prevent the ET voltage from exceeding the maximum voltage level when the time-variant output power of the signal is higher than the threshold level; and an acoustic filter circuit comprising an acoustic impedance inverter circuit and an acoustic network circuit and configured to pass the amplified signal in a transmit frequency and reject the signal outside the transmit frequency.

2. The loadline modulation power management circuit of claim 1, wherein the single-ended amplifier is deactivated when the time-variant output power is lower than the threshold level.

3. The loadline modulation power management circuit of claim 1, further comprising: a transformer circuit configured to couple the differential amplifier to an input of the acoustic impedance inverter circuit; and an impedance transformation circuit coupled between the single-ended amplifier and an output of the acoustic impedance inverter circuit and configured to reduce the default loadline impedance when the single-ended amplifier is activated.

4. The loadline modulation power management circuit of claim 1, wherein: the acoustic impedance inverter circuit comprises an acoustic impedance inverter comprising: a pair of inductors coupled in series between an input node and an output node; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle shunt resonator coupled between a middle node and the ground; and the acoustic network circuit comprises an acoustic ladder network coupled to the output node.

5. The loadline modulation power management circuit of claim 1, wherein: the acoustic impedance inverter circuit comprises an acoustic impedance inverter comprising: a pair of inductors coupled in series between an input node and an output node; a parallel acoustic resonator coupled between the input node and the output node in parallel to the pair of inductors; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle node coupled to the ground; and the acoustic network circuit comprises an acoustic ladder network coupled to the output node.

6. The loadline modulation power management circuit of claim 1, wherein: the acoustic impedance inverter circuit comprises an acoustic impedance inverter comprising: a pair of inductors coupled in series between an input node and an output node; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle shunt resonator coupled between a middle node and the ground; and the acoustic network circuit comprises a plurality of acoustic ladder networks each coupled to the output node.

7. The loadline modulation power management circuit of claim 1, wherein: the acoustic impedance inverter circuit comprises an acoustic impedance inverter comprising: a pair of inductors coupled in series between an input node and an output node; a parallel acoustic resonator coupled between the input node and the output node in parallel to the pair of inductors; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle node coupled to the ground; and the acoustic network circuit comprises a plurality of acoustic ladder networks each coupled to the output node.

8. The loadline modulation power management circuit of claim 1, wherein: the acoustic impedance inverter circuit comprises a plurality of acoustic impedance inverters each corresponding to a respective frequency band and comprising: a pair of inductors coupled in series between an input node and an output node; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle shunt resonator coupled between a middle node and the ground; and the acoustic network circuit comprises a plurality of acoustic ladder networks each coupled to the output node of a respective one of the plurality of acoustic impedance inverters.

9. The loadline modulation power management circuit of claim 1, wherein: the acoustic impedance inverter circuit comprises a plurality of acoustic impedance inverters each comprising: a pair of inductors coupled in series between an input node and an output node; a parallel acoustic resonator coupled between the input node and the output node in parallel to the pair of inductors; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle node coupled to the ground; and the acoustic network circuit comprises a plurality of acoustic ladder networks each coupled to the output node of a respective one of the plurality of acoustic impedance inverters.

10. A wireless device comprising a loadline modulation power management circuit, the loadline modulation power management circuit comprises: a power amplifier circuit, comprising: a differential amplifier always activated and configured to: receive an envelope tracking (ET) voltage having a dynamic range defined by a minimum voltage level and a maximum voltage level; and amplify a signal from a time-variant input power to a time-variant output power that is inversely related to a default loadline impedance based on the ET voltage; and a single-ended amplifier activated when the time-variant output power is higher than or equal to a threshold level to reduce the default loadline impedance to thereby prevent the ET voltage from exceeding the maximum voltage level when the time-variant output power of the signal is higher than the threshold level; and an acoustic filter circuit comprising an acoustic impedance inverter circuit and an acoustic network circuit and configured to pass the amplified signal in a transmit frequency and reject the signal outside the transmit frequency.

11. The wireless device of claim 10, wherein the single-ended amplifier is deactivated when the time-variant output power is lower than the threshold level.

12. The wireless device of claim 10, wherein the loadline modulation power management circuit further comprises: a transformer circuit configured to couple the differential amplifier to an input of the acoustic impedance inverter circuit; and an impedance transformation circuit coupled between the single-ended amplifier and an output of the acoustic impedance inverter circuit and configured to reduce the default loadline impedance when the single-ended amplifier is activated.

13. The wireless device of claim 10, wherein: the acoustic impedance inverter circuit comprises an acoustic impedance inverter comprising: a pair of inductors coupled in series between an input node and an output node; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle shunt resonator coupled between a middle node and the ground; and the acoustic network circuit comprises an acoustic ladder network coupled to the output node.

14. The wireless device of claim 10, wherein: the acoustic impedance inverter circuit comprises an acoustic impedance inverter comprising: a pair of inductors coupled in series between an input node and an output node; a parallel acoustic resonator coupled between the input node and the output node in parallel to the pair of inductors; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle node coupled to the ground; and the acoustic network circuit comprises an acoustic ladder network coupled to the output node.

15. The wireless device of claim 10, wherein: the acoustic impedance inverter circuit comprises an acoustic impedance inverter comprising: a pair of inductors coupled in series between an input node and an output node; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle shunt resonator coupled between a middle node and the ground; and the acoustic network circuit comprises a plurality of acoustic ladder networks each coupled to the output node.

16. The wireless device of claim 10, wherein: the acoustic impedance inverter circuit comprises an acoustic impedance inverter comprising: a pair of inductors coupled in series between an input node and an output node; a parallel acoustic resonator coupled between the input node and the output node in parallel to the pair of inductors; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle node coupled to the ground; and the acoustic network circuit comprises a plurality of acoustic ladder networks each coupled to the output node.

17. The wireless device of claim 10, wherein: the acoustic impedance inverter circuit comprises a plurality of acoustic impedance inverters each corresponding to a respective frequency band and comprising: a pair of inductors coupled in series between an input node and an output node; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle shunt resonator coupled between a middle node and the ground; and the acoustic network circuit comprises a plurality of acoustic ladder networks each coupled to the output node of a respective one of the plurality of acoustic impedance inverters.

18. The wireless device of claim 10, wherein: the acoustic impedance inverter circuit comprises a plurality of acoustic impedance inverters each comprising: a pair of inductors coupled in series between an input node and an output node; a parallel acoustic resonator coupled between the input node and the output node in parallel to the pair of inductors; an input shunt resonator coupled between the input node and a ground; an output shunt resonator coupled between the output node and the ground; and a middle node coupled to the ground; and the acoustic network circuit comprises a plurality of acoustic ladder networks each coupled to the output node of a respective one of the plurality of acoustic impedance inverters.

19. The wireless device of claim 10, further comprising: an ET integrated circuit (ETIC) configured to generate the ET voltage based on an ET target voltage; and a transceiver circuit configured to generate the signal in the time-variant input power and the ET target voltage that tracks the time-variant input power.

20. A method for performing loadline modulation comprising: receiving, by a differential amplifier that is always activated, an envelope tracking (ET) voltage having a dynamic range defined by a minimum voltage level and a maximum voltage level; amplifying, by the differential amplifier, a signal from a time-variant input power to a time-variant output power that is inversely related to a default loadline impedance based on the ET voltage; activating a single-ended amplifier when the time-variant output power is higher than or equal to a threshold level to reduce the default loadline impedance to thereby prevent the ET voltage from exceeding the maximum voltage level when the time-variant output power of the signal is higher than the threshold level; and passing the amplified signal in a transmit frequency and rejecting the signal outside the transmit frequency.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0010] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0011] FIG. 1 is a schematic diagram of an exemplary loadline modulation power management circuit wherein a power amplifier circuit is configured to perform loadline modulation and an acoustic filter circuit is configured to reduce transmit loss;

[0012] FIG. 2 is a graphic diagram providing an exemplary illustration of the loadline modulation being performed by the loadline modulation power management circuit of claim 1;

[0013] FIGS. 3A-3D are schematic diagrams illustrating various embodiments of the acoustic filter circuit in FIG. 1;

[0014] FIG. 4 is a schematic diagram of an exemplary communication device wherein the loadline modulation power management circuit of FIG. 1 can be provided; and

[0015] FIG. 5 is a flowchart of an exemplary process whereby the loadline modulation power management circuit of FIG. 1 can be configured to perform the loadline modulation.

DETAILED DESCRIPTION

[0016] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0017] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0018] It will be understood that when an element such as a layer, region, or substrate is referred to as being on or extending onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being over or extending over another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over or extending directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

[0019] Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022] Embodiments of the disclosure relate to a loadline modulation power management circuit. The loadline modulation power management circuit includes a power amplifier circuit and an acoustic filter circuit. Specifically, the power amplifier circuit is configured to amplify a signal to a time-variant output power based on a modulated voltage and the acoustic filter circuit is configured to pass the amplified signal for transmission in a transmit frequency. Herein, the power amplifier circuit is further configured to dynamically modulate a loadline impedance based on the time-variant output power to prevent the modulated voltage from exceeding a maximum level, whereas the acoustic filter circuit can help reduce overall transmit loss in the amplified signal. As a result, the loadline modulation power management circuit can operate with optimal efficiency and with reduced overall transmit loss.

[0023] FIG. 1 is a schematic diagram of an exemplary loadline modulation power management circuit 10 wherein a power amplifier circuit 12 is configured to perform loadline modulation and an acoustic filter circuit 14 is configured to reduce transmit loss. The power amplifier circuit 12 includes a differential amplifier 16 and a single-ended amplifier 18. In context of the present disclosure, the single-ended amplifier 18 can be any amplifier except a differential amplifier.

[0024] Herein, the differential amplifier 16 is always active to amplify a signal 20 from a time-variant input power P.sub.IN to a time-variant output power P.sub.OUT based on an envelope tracking (ET) voltage V.sub.CC. In an embodiment, the ET voltage V.sub.CC is generated by an ET integrated circuit (ETIC) 22 in accordance with an ET target voltage V.sub.TGT that is provided by a transceiver circuit 24. Since the transceiver circuit 24 also generates the signal 20 in the time-variant input power P.sub.IN, the transceiver circuit 24 can thus generate the ET target voltage V.sub.TGT in accordance with the time-input power P.sub.IN. Accordingly, the ETIC 22 can generate the ET voltage V.sub.CC to closely track the time-variant input power P.sub.IN. Specifically, the ET voltage V.sub.CC is confined within a dynamic range 26 as defined by a minimum voltage level V.sub.MIN (e.g., 0.8 V) and a maximum voltage level V.sub.MAX (e.g., 5.5 V).

[0025] The differential amplifier 16 is typically configured to operate according to a default loadline impedance Z.sub.L for better efficiency. FIG. 2 is a graphic diagram providing an exemplary illustration of a loadline 28 representing the default loadline impedance Z.sub.L.

[0026] According to the loadline 28, the time-variant output power P.sub.OUT is approximately a function of the ET voltage V.sub.CC and the default loadline impedance Z.sub.L (P.sub.OUTV.sub.CC.sup.2/Z.sub.L). As illustrated, the ET voltage V.sub.CC (V.sub.CC{square root over (P.sub.OUT*Z.sub.L)}) reaches the maximum voltage level V.sub.MAX when the time-variant output power P.sub.OUT reaches a threshold level P.sub.TH. Beyond the threshold level P.sub.TH, the ET voltage V.sub.CC must continue rising beyond the maximum voltage level V.sub.MAX (e.g., V.sub.EXTRA) to drive the time-variant output power P.sub.OUT to a peak power level P.sub.PEAK. This can create a significant impact on the ETIC 22 in terms of current consumption and heat dissipation. As such, it is desirable to prevent the ET voltage V.sub.CC from exceeding the maximum voltage level V.sub.MAX when the time-variant output power P.sub.OUT is at the peak power level P.sub.PEAK.

[0027] In this regard, the single-ended amplifier 18 is activated to modulate the default loadline impedance Z.sub.L when the time-variant output power Pour is higher than or equal to the threshold level P.sub.TH (e.g., P.sub.TH=P.sub.PEAK3 dB). Herein, the single-ended amplifier 18 can change the default loadline impedance Z.sub.L to a modified loadline impedance Z.sub.L-MOD (Z.sub.L-MOD<Z.sub.L). Accordingly, the differential amplifier 16 will operate based on a modified loadline 30, wherein the time-variant output power P.sub.OUT is approximately a function of the ET voltage V.sub.CC and the modified loadline impedance Z.sub.L-MOD (P.sub.OUTV.sub.CC.sup.2/Z.sub.L-MOD). As illustrated herein, since the modified loadline impedance Z.sub.L-MOD is smaller than the default loadline impedance Z.sub.L, the ET voltage V.sub.CC (V.sub.CC{square root over (P.sub.OUT*Z.sub.L-MOD)}) for driving the time-variant output power P.sub.OUT to the peak power level P.sub.PEAK can become lower.

[0028] As a result, it is possible to prevent the ET voltage V.sub.CC from exceeding the maximum voltage level V.sub.MAX at the peak power level P.sub.PEAK. In other words, the ET voltage V.sub.CC will stay within the dynamic range 26 when the time-variant output power P.sub.OUT is higher than the threshold level P.sub.TH.

[0029] With reference back to FIG. 1, the power amplifier circuit 12 can include a controller 32, which is configured to provide a bias voltage V.sub.BIAS to the differential amplifier 16 and the single-ended amplifier 18. In an embodiment, the controller 32 can be configured to activate the single-ended amplifier 18 when the time-variant output power P.sub.OUT reaches the threshold level P.sub.TH (P.sub.OUTP.sub.TH) by providing the bias voltage V.sub.BIAS to the single-ended amplifier 18 and deactivate the single-ended amplifier 18 when the time-variant output power P.sub.OUT drops below the threshold level P.sub.TH (P.sub.OUT<P.sub.TH) by removing the bias voltage V.sub.BIAS from the single-ended amplifier 18. As an example, the controller 32 can determine whether to activate or deactivate the single-ended amplifier 18 based on the ET voltage V.sub.CC.

[0030] The power amplifier circuit 12 can also include a splitter 34 that splits the signal 20 into a pair of signals 20A, 20B, each having one-half of the time-variant input power P.sub.IN (P.sub.IN). In an embodiment, the signal 20A is in-phase with the signal 20, whereas the signal 20B has a ninety-degree (90) degree phase offset relative to the signal 20.

[0031] The power amplifier circuit 12 further includes a transformer circuit 36 and an impedance transformation circuit 38. The transformer circuit 36 includes an input coil 40 and an output coil 42. The input coil 40 is coupled to the differential amplifier 16 and the output coil 42 is coupled to the acoustic filter circuit 14. Herein, the modulated voltage V.sub.CC is provided to a center node C.sub.1 of the input coil 40, and the default loadline impedance Z.sub.L is provided by a pair of outer nodes A.sub.1, A.sub.2 of the input coil 40. The output coil 42 is configured to provide the signal 20A, as amplified by the differential amplifier 16, to the acoustic filter circuit 14.

[0032] The impedance transformation circuit 38 is configured to reduce the default loadline impedance Z.sub.L to the modified loadline impedance Z.sub.L-MOD when the single-ended amplifier 18 is activated. The impedance transformation circuit 38 may be coupled to the acoustic filter circuit 14 via a switch 44. In an embodiment, the switch 44 may be closed when the single-ended amplifier 18 is activated and opened when the single-ended amplifier 18 is deactivated. The acoustic filter circuit 14 can be configured to include an acoustic

[0033] impedance inverter circuit 46 and an acoustic network circuit 48. In general, the acoustic filter circuit 14 is configured to pass the amplified signal 20 in a transmit frequency and reject the signal 20 outside the transmit frequency.

[0034] The acoustic filter circuit 14 can be configured according to various embodiments of the present disclosure, as further described below in FIGS. 3A-3D. FIGS. 3A-3D are schematic diagrams illustrating various embodiments of the acoustic filter circuit 14 in FIG. 1. Common elements between FIGS. 1 and 3A-3D are shown therein with common element numbers and will not be re-described herein.

[0035] FIG. 3A illustrates an acoustic filter circuit 14A configured according to one embodiment of the present disclosure. Herein, the acoustic filter circuit 14A includes an acoustic impedance inverter circuit 50 and an acoustic network circuit 52. The acoustic impedance inverter circuit 50 includes an acoustic impedance inverter 54 (e.g., a k-inverter). In an embodiment, the acoustic impedance inverter 54 includes a pair of inductors L.sub.1, L.sub.2, an input shunt resonator 56I, an output shunt resonator 56O, and a middle shunt resonator 56M. The pair of inductors L.sub.1, L.sub.2 are coupled in series between an input node N.sub.I and an output node N.sub.O. The input shunt resonator 56I is coupled between the input node N.sub.I and a ground, the output shunt resonator 56O is coupled between the output node N.sub.O and the ground, and the middle shunt resonator 56M is coupled between a middle node N.sub.M and the ground.

[0036] The acoustic network circuit 52, on the other hand, includes an acoustic ladder network 58 that is coupled to the output node N.sub.O. In an embodiment, the acoustic ladder network 58 can include one or more respective series resonators 60 and one or more respective shunt resonators 62. FIG. 3B illustrates an acoustic filter circuit 14B configured according

[0037] to another embodiment of the present disclosure. Herein, the acoustic filter circuit 14B includes an acoustic impedance inverter circuit 64 that includes an acoustic impedance inverter 66. The acoustic impedance inverter 66 includes a parallel acoustic resonator 68, an input shunt resonator 70I, and an output shunt resonator 70O. The parallel acoustic resonator 68 is coupled between the input node N.sub.I and the output node N.sub.O in parallel to the pair of inductors L.sub.1, L.sub.2. The input shunt resonator 70I is coupled between the input node N.sub.I and the ground, the output shunt resonator 70O is coupled between the output node N.sub.O and the ground, whereas the middle node N.sub.M is coupled directly to the ground. FIG. 3C illustrates an acoustic filter circuit 14C configured according

[0038] to another embodiment of the present disclosure. Herein, the acoustic filter circuit 14C can include an acoustic network circuit 72 that includes multiple acoustic ladder networks 74(1)-74(N). In an embodiment, each of the acoustic ladder networks 74(1)-74(N) is identical or functionally equivalent to the acoustic ladder network 58 in FIGS. 3A and 3B. Each of the acoustic ladder networks 74(1)-74(N) is configured to pass the signal 20 in a respective one of multiple transmit frequencies f.sub.1-f.sub.N.

[0039] FIG. 3D illustrates an acoustic filter circuit 14D configured according to another embodiment of the present disclosure. Herein, the acoustic filter circuit 14D can include an acoustic impedance inverter circuit 76. The acoustic impedance inverter circuit 76 includes multiple acoustic impedance inverters 78(1)-78(N). Herein, each of the acoustic impedance inverters 78(1)-78(N) can be configured according to a respective frequency band (e.g., among multiple different transmit frequency bands). In an embodiment, each of the acoustic impedance inverters 78(1)-78(N) can be identical or functionally equivalent to any of the acoustic impedance inverter 54 in FIG. 3A and the acoustic impedance inverter 66 in FIG. 3B. The acoustic impedance inverters 78(1)-78(N) are coupled to the acoustic ladder networks 74(1)-74(N), respectively.

[0040] The loadline modulation power management circuit 10 of FIG. 1 can be provided in a communication device to enable the embodiments described above. In this regard, FIG. 4 is a schematic diagram of an exemplary communication device 100 wherein the loadline modulation power management circuit 10 of FIG. 1 can be provided.

[0041] Herein, the communication device 100 can be any type of communication device, such as mobile terminal, smart watch, tablet, computer, navigation device, access point, base station (e.g., eNB, gNB, etc.), and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0042] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0043] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 110. The multiple antennas 112 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0044] In an embodiment, the loadline modulation power management circuit 10 may be provided between the transmit circuitry 106 and the antenna switching circuitry 110. Accordingly, the transmit circuitry 106 can be configured to function as the transceiver circuit 24 in FIG. 1.

[0045] In an embodiment, the loadline modulation power management circuit 10 of FIG. 1 can be configured to perform loadline modulation according to a process. In this regard, FIG. 5 is a flowchart of an exemplary process 200 whereby the loadline modulation power management circuit 10 of FIG. 1 can be configured to perform the loadline modulation.

[0046] Herein, the process 200 includes receiving, by the differential amplifier 16 that is always activated, the ET voltage V.sub.CC having the dynamic range 26 defined by the minimum voltage level V.sub.MIN and the maximum voltage level V.sub.MAX (step 202). The process 200 also includes amplifying, by the differential amplifier 16, the signal 20 from the time-variant input power P.sub.IN to the time-variant output power P.sub.OUT that is inversely related to the default loadline impedance Z.sub.L based on the ET voltage V.sub.CC (step 204). The process 200 also includes activating the single-ended amplifier 18 when the time-variant output power P.sub.OUT is higher than or equal to the threshold level P.sub.TH to reduce the default loadline impedance Z.sub.L to thereby prevent the ET voltage V.sub.CC from exceeding the maximum voltage level V.sub.MAX when the time-variant output power P.sub.OUT of the signal 20 is higher than the threshold level P.sub.TH (step 206). The process 200 also includes passing the amplified signal 20 in the transmit frequency and rejecting the signal 20 outside the transmit frequency (step 208).

[0047] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.