MANUFACTURING METHOD, MANUFACTURING DEVICE OF MULTI-LAYER METALENS AND MULTI-LAYER METALENS

Abstract

A manufacturing method, manufacturing device, a multi-layer metalens are provided. The the multi-layer metalens comprises a plurality of N structured surfaces arranged in a vertical direction on one surface of a wafer, N2. The manufacturing method includes: when a target surface to be manufactured is a first structured surface, manufacturing the first structured surface on a target surface of the wafer; the first structured surface includes a plurality of nanostructures and a location marker; and the plurality of nanostructures are arranged in an array; when the target surface to be manufactured is an M.sub.th structured surface, manufacturing an alignment window based on the location marker of the structured surface manufactured previously; and through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the structured surface manufactured previously.

Claims

1. A manufacturing method of a multi-layer metalens, wherein the multi-layer metalens comprises a plurality of N structured surfaces arranged in a vertical direction on one surface of a wafer, N2; the manufacturing method comprises: when a target surface to be manufactured is a first structured surface, manufacturing the first structured surface on a target surface of the wafer; the first structured surface comprises a plurality of nanostructures and a location marker; and the plurality of nanostructures are arranged in an array; when the target surface to be manufactured is an M.sub.th structured surface, manufacturing an alignment window based on the location marker of the structured surface manufactured previously; and through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the structured surface manufactured previously; wherein the M.sub.th structured surface comprises a plurality of nanostructures; and the plurality of nanostructures are arranged in an array; a position of the array of nanostructures in the M.sub.th structured surface matches with a position of the array of nanostructures in the structured surface manufactured previously in a perpendicular direction; MN, and M>1.

2. The manufacturing method of claim 1, wherein manufacturing an alignment window based on the location marker of the structured surface manufactured previously comprises: manufacturing the alignment window based on the location marker of the first structured surface; wherein a projection of the location marker of the first structured surface on a parallel surface of the wafer is located inside a projection of the alignment window on a parallel surface of the wafer; through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the structured surface manufactured previously comprises: through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the first structured surface.

3. The manufacturing method of claim 1, wherein manufacturing the alignment window based on the location marker of the structured surface manufactured previously comprises: manufacturing the alignment window of the M.sub.th structured surface based on the location marker of the M1.sub.th structured surface; wherein a projection of the location marker of the M1.sub.th structured surface on a parallel surface of the wafer is located inside a projection of the alignment window on a parallel surface of the wafer; through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the structured surface manufactured previously comprises: through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the M1.sub.th structured surface; wherein, when M<N, the M.sub.th structured surface further comprises a location marker.

4. The manufacturing method of claim 3, wherein the projections of the location markers of the structured surfaces on the parallel surface of the wafer don't overlap with each other.

5. The manufacturing method of claim 1, wherein manufacturing the first structured surface on a target surface of the wafer comprises: manufacturing a first structured layer on the target surface, and lithographing and etching the first structured layer, so as to obtain the array of nanostructures and the location marker on the target surface; filling a first filler material between the adjacent nanostructures, and between the nanostructures and the location marker on the target surface to obtain the first structured surface.

6. The manufacturing method of claim 1, wherein manufacturing an alignment window based on the location marker of the structured surface manufactured previously comprises: manufacturing an M.sub.th structured layer on the upper surface on the M-1.sub.th structured surface, and lithographing and etching the M.sub.th structured layer to obtain the alignment window; through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the structured surface manufactured previously comprises: through the alignment window, pre-locating the array of nanostructures to be manufactured in the M.sub.th structured layer based on the location marker of structured surface manufactured previously; based on the pre-location of the array of nanostructures in the M.sub.th structured surface, lithographing and etching the M.sub.th structured layer, so as to obtain the array of nanostructures on the upper surface of the M1.sub.th structured surface; filling an M.sub.th filler material between the arrays of nanostructures on the upper surface of the M1.sub.th structured surface, so as to obtain the M.sub.th structured surface.

7. The manufacturing method of claim 5, wherein after filling a filler material to obtain the corresponding structured surface, the manufacturing method comprises: thinning and polishing an upper surface of the obtained corresponding structured surface.

8. The manufacturing method of claim 6, wherein after filling a filler material to obtain the corresponding structured surface, the manufacturing method comprises: thinning and polishing an upper surface of the obtained corresponding structured surface.

9. The manufacturing method of claim 5, wherein after lithographing and etching the structured layer, the obtained nanostructures on the structured layer are positive nanostructures.

10. The manufacturing method of claim 6, wherein after lithographing and etching the structured layer, the obtained nanostructures on the structured layer are positive nanostructures.

11. The manufacturing method of claim 5, wherein after lithographing and etching the structured layer, the obtained nanostructures in the structured layer are negative nanostructures.

12. The manufacturing method of claim 6, wherein after lithographing and etching the structured layer, the obtained nanostructures in the structured layer are negative nanostructures.

13. A manufacturing device, wherein the multi-layer metalens comprises an N structured surfaces arranged in a vertical direction on the same surface of a wafer, N2; a manufacturing module of the first structured surface, the manufacturing module of the first structured surface is configured to manufacture the first structured surface on a target surface of the wafer, when the target surface to be manufactured is the first structured surface; wherein the first structured surface comprises the array of nanostructures and location marker; a manufacturing module of the M.sub.th structured surface, the manufacturing module of the M.sub.th structured surface is configured to manufacture an alignment window based on the location marker of the structured surface manufactured previously; and through the alignment window, to manufacture the M.sub.th structured surface based on the location marker of the structured surface manufactured previously; the M.sub.th structured surface comprises a plurality of nanostructures, and the plurality of nanostructures are arranged in an array; a position of the array of nanostructures in the M.sub.th structured surface matches with a position of the array of nanostructures in the M1.sub.th structured surface in the perpendicular direction; MN, and M>1.

14. A multi-layer metalens, wherein the multi-layer metalens is obtained by using the manufacturing method claimed as claim 1.

15. The multi-layer metalens of claim 14, wherein the multi-layer metalens comprises an N structured surfaces arranged in a vertical direction on the same surface of a wafer, N2; the N structured surfaces comprise: the first structured surface, the second layer, . . . , the N.sub.th structured surface; the first structured surface comprises the plurality of nanostructures and the location marker, and the plurality of nanostructures are arranged in an array; the M.sub.th structured surface comprises an alignment window, and the alignment window corresponds to the location marker of the structured surface manufactured previously; the M.sub.th structured surface comprises a plurality of nanostructures, and the plurality of nanostructures are arranged in an array; a position of the array of nanostructures in the M.sub.th structured surface matches with a position of the array of nanostructures in the M1.sub.th structured surface in a perpendicular direction; MN, and M>1.

16. The multi-layer metalens of claim 15, wherein a projection of the location marker of the structured surface manufactured previously on a parallel surface of the wafer is located inside a projection of the alignment window in the structured surface manufactured previously on a parallel surface of the wafer.

17. The multi-layer metalens of claim 15, wherein a projection of the location marker of the structured surface manufactured previously on a parallel surface of the wafer is located inside a projection of the alignment window in the structured surface manufactured previously on a parallel surface of the wafer; wherein, when M<N, the M.sub.th structured surface further comprises a location marker.

18. The multi-layer metalens of claim 17, wherein the projections of the location markers in the structured surfaces on the parallel surface of the wafer don't overlap with each other.

19. An electronic device, the electronic device comprises: a bus, a transceiver, a memory, a processor and a computer program; wherein the computer program is stored in the memory and executable on the processor; the transceiver, the memory and the processor are connected through the bus; the computer program is executed by the processor, so as to implement the manufacturing method of claim 1.

20. A non-transitory computer-readable storage medium, the non-transitory computer-readable storage medium in which a computer program is stored, wherein the computer program is executed by a processor, so as to implement the manufacturing method of claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to explain more clearly, the technical scheme in the application technology or the background technology, the attached drawings required in the application embodiment or the background technology will be explained below.

[0052] FIG. 1 shows a structural diagram of the multi-layer metalens provided by the present application.

[0053] FIG. 2 shows a flowchart of the manufacturing method of a multi-layer metalens provided by the present application.

[0054] FIG. 3 shows a structural diagram of an obtained structure after the first structured layer being manufactured on the target surface of the wafer.

[0055] FIG. 4 shows a structural diagram of an array of nanostructures and the location marker after lithographing the first structured layer.

[0056] FIG. 5 shows a structural diagram of the array of nanostructures and the location marker after etching the first structured layer in one embodiment.

[0057] FIG. 6 shows a structural diagram of the first structured surface after filling the first filler material between the array of nanostructures of the location marker.

[0058] FIG. 7 shows a structural diagram of a structured surface after thinning and polishing the upper surface of the first structured surface.

[0059] FIG. 8 shows a schematic diagram of the obtained structure after manufacturing the second structured layer on the upper surface of the first structured surface.

[0060] FIG. 9 shows a schematic diagram of the obtained structure after lithographing the second structured layer to manufacture an alignment window in an embodiment of the present application.

[0061] FIG. 10 shows a schematic diagram of the obtained structure after etching the second structured layer to manufacture the alignment window in an embodiment of this application.

[0062] FIG. 11 shows a schematic diagram of the obtained structure after lithographing the second structured layer to manufacture an array of nanostructures in an embodiment of this application.

[0063] FIG. 12 shows a schematic diagram of the obtained structure after etching the second structured layer to manufacture the array of nanostructures in an embodiment of this application.

[0064] FIG. 13 shows a schematic diagram of the obtained second layer after filling the second filler material between the array of nanostructures located on the upper surface of the first structured surface.

[0065] FIG. 14 shows a schematic diagram of the obtained structure after thinning and polishing the upper surface of the second structured surface in an embodiment of this application.

[0066] FIG. 15 shows a schematic diagram of the obtained structure after the lithography of the array of negative nanostructures in the first structured layer.

[0067] FIG. 16 shows a schematic diagram of the obtained structure after etching the array of negative nanostructures in the first structured layer.

[0068] FIG. 17 shows a schematic diagram of the obtained structure after etching of array of negative nanostructures in the second structured layer.

[0069] FIG. 18 shows a schematic diagram of the obtained structure after lithographing of array of negative nanostructures in the second structured layer.

[0070] FIG. 19 shows a schematic diagram of the obtained structure after filling the second filler material in the array of negative nanostructures.

[0071] FIG. 20 shows a schematic diagram of the obtained structure after thinning and polishing the array of negative nanostructures on the upper surface of the second structured surface.

[0072] FIG. 21 shows a top view of the first structured surface provided by the present application.

[0073] FIG. 22 shows a top view of the second structured surface provided by the present application.

[0074] FIG. 23 shows a block diagram of a manufacturing device for a multi-layer metalens provided in the present application.

DETAILED DESCRIPTION OF DISCLOSURED EMBODIMENTS

[0075] An embodiment will be described in detail below, the examples of which are represented in the accompanying drawings. When the following description involves the drawings, the same numbers in different drawings indicate the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiment do not represent all embodiments consistent with the present disclosure. Instead, they are only examples of devices and methods consistent with some aspects of the present disclosure, as detailed in the attached claim.

[0076] Furthermore, the described features, structures or features may be combined in one or more exemplary embodiments in any suitable manner. In the following description, many specific details are provided to give a full understanding of the exemplary embodiments of this application. However, those skilled in the art will be aware that the technical solution of the present application may be practiced to omit one or more of the specific details described, or that other methods, groups, steps, and the like may be adopted. In other cases, aspects of the present application are blurred without detailed showing or describing the public structure, method, implementation, or operation to avoid over-dominance.

[0077] Some of the box plots shown in the accompanying drawings are functional entities and do not necessarily have to correspond to physically or logically separate entities. These functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or micro-controller devices.

[0078] A manufacturing method of the multi-layer metalens is provided by the present application, when manufacturing a multi-layer metalens by the manufacturing method provided by the present application, the relative position between the array of nanostructures in different structured surfaces can be controlled accurately.

[0079] In detail, FIG. 1 shows a structural diagram of the multi-layer metalens provided by the present application. In one embodiment, the multi-layer metalens provided by the present embodiment is mainly used at a visible waveband or a near-infrared waveband. In this situation, the wafer 10 may be made of transparent material at the visible waveband or the near-infrared waveband. For example, the wafer may be made of quartz that has a smaller optical absorption at the visible waveband and the near-infrared waveband.

[0080] Further, in the present application, on one surface of the wafer 10, the multi-layer metalens includes a plurality of N structured surfaces arranged in a vertical direction on one surface of a wafer, N2. FIG. 1 shows a multi-layer metalens with the first structured surface and the second structured surface (N=2). However, it doesn't mean that the multi-layer metalens manufactured by the manufacturing method provided in this application can only have two structured surfaces.

[0081] FIG. 2 shows a flowchart of the manufacturing method of a multi-layer metalens provided by the present application. As shown in FIG. 2, the manufacturing method provided in this application includes:

[0082] S21. when the target surface to be manufactured is a first structured surface, manufacturing the first structured surface on a target surface of the wafer; the first structured surface includes a plurality of nanostructures and a location marker; and the plurality of nanostructures are arranged in an array;

[0083] S22. when the target surface to be manufactured is an M.sub.th structured surface, manufacturing an alignment window based on the location marker of the structured surface manufactured previously; and through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the structured surface manufactured previously; wherein the M.sub.th structured surface includes a plurality of nanostructures; and the plurality of nanostructures are arranged in an array; and the position of the array of nanostructures in the M.sub.th structured surface matches with the position of the array of nanostructures in the structured surface manufactured previously in the perpendicular direction; MN, and M>1.

[0084] Specifically, in the present application, the structured surfaces of the multi-layer metalens are divided into the first structured surface 11 and the M.sub.th structured surface. The M.sub.th structured surface is a structured surface to be manufactured after the first structured surface 11 has been manufactured.

[0085] When the target surface to be manufactured is a first structured surface, the first structured surface including the array of nanostructures and the location marker is manufactured on the target surface of the wafer. The location marker of the first structured surface 11 is capable of providing a location reference for the array of nanostructures in the M.sub.th structured surface.

[0086] When the target surface to be manufactured is an M.sub.th structured surface, an alignment window is manufactured based on the location marker of the structured surface manufactured previously. The alignment window is capable of exposing the location marker of the structured surface manufactured previously within the detection range at a specific waveband. Therefore, through the alignment window, the array of nanostructures of the M.sub.th structured surface is pre-located accurately to manufacture based on the location markers in the structured surfaces manufactured previously and obtain the M.sub.th structured surface. In this way, the position of the array of nanostructures in the M.sub.th structured surface matches with the position of the array of nanostructures in the structured surface manufactured previously.

[0087] It should be noted that for the M.sub.th structured surface, the structured surface manufactured previously may be the first structured surface 11 or the M1.sub.th structured surface. For example, for the third structured surface, the structured surface manufactured previously may be the first structured surface 11, or the the structured surface manufactured previously may be the second structured surface 12.

[0088] It also should be noted that the position of array of nanostructures in the M.sub.th structured surface matches with the position of the array of nanostructures in the structured surface manufactured previously refers to for the M.sub.th structured surface and the structured surface manufactured previously, the deviation of the projections of the array of nanostructures of those structured surfaces on the parallel surface of the wafer is equal to 0, or the deviation of the projections of the array of nanostructures of those structured surfaces on the parallel surface of the wafer is less than a pre-set position tolerance.

[0089] It can be seen that the manufacturing method provided by the present application the position of the array of nanostructures in the M.sub.th structured surface matches with the position of the array of nanostructures in the structured surface manufactured previously. Therefore, the relative position between the array of nanostructures in the different structured surfaces can be controlled accurately.

[0090] In one embodiment, manufacturing the first structured surface on a target surface of the wafer includes:

[0091] manufacturing the first structured surface on the target surface, and lithographing and etching the first structured surface, so as to obtain the array of nanostructures and location marker on the target surface;

[0092] filling a first filler material between the nanostructures and the location marker on the target surface to obtain the first structured surface.

[0093] Specifically, FIG. 3 shows a structural diagram of an obtained structure after the first structured layer 111 is manufactured on the target surface of the wafer 10. FIG. 4 shows a structural diagram of an array of nanostructures 114 and the location marker 113 after lithographing the first structured layer 111. FIG. 5 shows a structural diagram of the array of nanostructures 114 and location marker 113 after etching the first structured layer 111 in one embodiment. FIG. 6 shows a structural diagram of the first structured surface in one embodiment after filling the first filler material between the array of nanostructures 114 of the location marker 113.

[0094] As shown from FIG. 3 to FIG. 6, in on embodiment, firstly the first structured layer 111 is manufactured on the target surface of the wafer 10. Then the photoresist 112 is coated to an upper surface of the first structured layer 111, and next the photoresist 112 is exposed and developed according to the distribution position of the array of nanostructures and the shape of nanostructures 114, and the distribution position and shape of the location marker 113. In this way, the pattern of the residual photoresist 112 will form the array of the nanostructures 114 obtained by the target (when the photoresist is a positive photoresist, the part of the exposure area is dissolved in the developing solution and the portion of the non-exposure area remains as the residual photoresist 112; when the photoresist is a negative photoresist, the portion of the non-exposure area remains as the residual photoresist 112), and the pattern of the location marker 113. The pattern of the array of the nanostructures 114 obtained by the target and the pattern of the location marker 113 are complementary patterns, or the pattern of the obtained array of the nanostructures 114 and the pattern of the location marker 113 are complementary patterns.

[0095] Then the portion exposing outside of the photoresist 112 of the first structured layer 111 is etched, so as to obtain the array of nanostructures 114 and location marker 113. Then the residual photoresist 112 is removed, and the first filler material 115 is filled between the array of nanostructures 114 and location marker 113, so as to obtain the first structured surface 11.

[0096] The first filler material 115 is used to protect the array of nanostructures 114 and location marker 113. The first filler material 115 is used to increase the transmittance of the first structured surface 11 for lights. And the first filler material 115 can provide the necessary support for the structured surface to be manufactured.

[0097] It should be noted that in the actual manufacturing process, when the structured layers are manufactured, different locations of the etching depth will have differences. It will leads to the heights of different nanostructures has a bit of difference. Although in the figures of the present application different nanostructures obtained by etching are neat and uniform, it should be understood that the figures are only used for example instructions and should not limit the scope of projection for the present application. In the present application, the sizes of different nanostructures obtained by etching are within a certain error range.

[0098] It should be noted that in the actual manufacturing process, after filling the filler material, the obtained structured surfaces are still uneven. Although in the figures provided by the present application, the upper surface of the structured surface after filling the filler material are even and smooth, it should be understood that the figures are only used for example instructions and should not limit the scope of projection for the present application. In the present application, the upper surface of the structured surface after filling the filler material may be uneven.

[0099] FIG. 7 shows a structural diagram of a structured surface after thinning and polishing the upper surface of the first structured surface. As shown in FIG. 7, in one embodiment, for the array of nanostructures 114 and location marker 113 of the first structured surface, after filling the first filler material 115, the upper surface of the first structured surface 11 is thinned and polished, so as to make the distance between the upper surface of the first structured surface 11 and the upper surface of the array of nanostructures 114 is less than a pre-set threshold. In this way, the upper surface of the first structured surface 11 has a high plainness.

[0100] When the target surface to be manufactured is the M.sub.th structured layer, in one embodiment, manufacturing an alignment window based on the location marker of the structured surface manufactured previously includes:

[0101] manufacturing the M.sub.th structured layer on the target surface on the M1.sub.th structured surface, and lithographing and etching the M.sub.th structured layer to obtain the alignment window.

[0102] through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the structured surface manufactured previously includes:

[0103] through the alignment window, pre-locating the array of nanostructures to be manufactured in the M.sub.th structured layer based on the location marker of structured surface manufactured previously;

[0104] based on the pre-location of the array of nanostructures in the M.sub.th structured surface, lithographing and etching the M.sub.th structured layer, so as to obtain the array of nanostructures of the M1.sub.th structured surface;

[0105] filling an M.sub.th filler material between the arrays of nanostructures on the upper surface of the M1.sub.th structured surface, so as to obtain the M.sub.th structured surface.

[0106] Specifically, in one embodiment, when the M.sub.th structured surface is manufactured, firstly the M.sub.th structured layer is manufactured on the M1.sub.th structured surface, and then the photoresist is coated to the upper surface on the M.sub.th structured layer. Then the photoresist is exposed and developed according to the distribution position and size of the alignment window obtained by the target, so that the pattern composed of the residual photoresist just constitutes the complementary pattern of the alignment window obtained by the target. Then, the part of the M.sub.th structured layer exposed to the photoresist is etched to obtain the alignment window.

[0107] It should be understood that the alignment window obtained by the manufacturing method makes the upper surface of the M1.sub.th structured surface expose in the outside directly. Therefore, through the alignment window, the location marker of the structured surface manufactured previously can be located accurately. Then, based on the location marker of the structured surface manufactured previously, the array of nanostructures to be manufactured in the M.sub.th structured layer can be pre-located accurately, and the distribution position of the array of nanostructures and the shape of nanostructures to be manufactured can be determined accurately.

[0108] Then according to the distribution position of the array of nanostructures and the shape of nanostructures to be manufactured, the photoresist is exposed and developed again, so that the pattern of the residual photoresist just constitutes the pattern of the array of nanostructures obtained by the target, or the complementary pattern of the array of nanostructures obtained by the target (if the area of the alignment window is excluded). Then the portion of the M.sub.th structured layer exposing to the photoresist is etched, that is, an array of nanostructures located on the upper surface of the structured surface manufactured previously.

[0109] Then the residual photoresist is removed, and the M.sub.th filler material is filled between the adjacent nanostructures on the M-1.sub.th structured surface, and between the array of nanostructures and the location marker on the M1.sub.th structured surface, and the M.sub.th structured surface is obtained.

[0110] Similar to the function of the first filler material 115, the function of the M.sub.th filler material will not be described here.

[0111] It should be noted that the M.sub.th filler material filled in the M.sub.th structured surface may be the same material as the first filler material 115 filled in the first structured surface 11, or the M.sub.th filler material filled in the M.sub.th structured surface may be a different material from the first filler material 115 filled in the first structured surface 11.

[0112] It should also be noted that the M.sub.th structured surface may be set with the location marker, or may not be set with the location marker. When the M.sub.th structured surface needs to be set with a location marker, based on the location marker of the structured layer manufactured previously, the array of nanostructures in the M.sub.th structured layer to be manufactured is pre-located. Thus, the position distribution of the array of nanostructures, the shape of the nanostructures and the location marker to be manufactured can be determined simultaneously. Therefore, according to the location distribution of the array of nanostructures to be manufactured and the shape of the location marker, after exposing and developing the photoresist, so that the pattern formed by the residual photoresist may be the pattern of the array of nanostructures and location marker, or may be a complementary pattern of the array of nanostructures and location marker (when the alignment window is excluded), therefore, the array of nanostructures located on the upper surface and the location marker on the structured surface manufactured previously is obtained by etching.

[0113] In one embodiment, for the array of the nanostructures in the M.sub.th structured surface, after filling the M.sub.th filler material, the upper surface of the M.sub.th structured surface is thinned and polished, so as to ensure that the distance between the upper surface of the M.sub.th structured surface and the upper surface of the array of nanostructures in the M.sub.th structured surface is less than a pre-set threshold, thus the upper surface of the M.sub.th structured surface has a high plainness.

[0114] FIG. 8 shows a schematic diagram of the obtained structure after manufacturing the second structured layer 121 on the upper surface of the first structured surface 11. FIG. 9 shows a schematic diagram of the obtained structure after lithographing the second structured layer 122 to manufacture an alignment window in an embodiment of the present application. FIG. 10 shows a schematic diagram of the obtained structure after etching the second structured layer 122 to manufacture the alignment window 123 in an embodiment of this application. FIG. 11 shows a schematic diagram of the obtained structure after lithography of the second structured layer 122 to manufacture an array of nanostructures 124 in an embodiment of this application. FIG. 12 shows a schematic diagram of the obtained structure after etching the second structured layer 122 to manufacture the array of nanostructures 124 in an embodiment of this application. FIG. 13 shows a schematic diagram of the second layer of structure surface 12 after filling the second filler material 125 between the array of the nanostructures 124 located on the upper surface of the first structured surface 11.

[0115] As shown from FIG. 8 to FIG. 13, in one embodiment, when the second structured surface 12 is manufactured, firstly the second structured layer 121 is manufactured on the first structured surface 11, then the photoresist is coated to the upper surface of the second structured layer 121. According to the position distribution and size of the alignment window 123 obtained by the target, the photoresist is exposed and developed, so that the pattern of the residual photoresist 122 exactly forms a complementary pattern of the alignment window 123 obtained by the target. Then the alignment window 123 is obtained by etching the portion of the second structure layer 121 exposed outside the photoresist 122.

[0116] Therefore, through the alignment window 123, the location marker of the first structured surface 11 is located accurately. The array of nanostructures 124 of the second structured surface is pre-located accurately based on the location marker 113, thus the position distribution of the array of nanostructures 124 and the shape of nanostructures 124 to be manufactured of the second structured layer 121 are determined accurately.

[0117] Then according to the position distribution of the array of nanostructures 124 and the shape of nanostructures 124 to be manufactured, the photoresist 122 is exposed and developed again, so that the pattern of the residual photoresist just constitutes the pattern of the array of nanostructures 124 obtained by the target, or the complementary pattern of the array of nanostructures 124 obtained by the target (if the area of the alignment window 123 is excluded). Then the portion of the second structured layer exposed to the photoresist 122 is etched, that is, an array of nanostructures 124 located above the upper surface of the structured surface manufactured previously.

[0118] Then the residual photoresist 122 is removed, and the second structured surface 12 is obtained after the second filler material 125 is filled between the array of nanostructures 124 and the location marker.

[0119] FIG. 14 shows a schematic diagram of the obtained structure after polishing the upper surface of the second structured surface 12 in an embodiment of this application. As shown in FIG. 14, in one embodiment, for the array of nanostructures 124 in the second structured surface 12, after filling the second filler material 125, the upper surface of the second structured surface 12 is thinned and polished, so that the distance between the upper surface of the second structured surface 12 and the upper surface of the array of nanostructures 124 is less than or equal to pre-set threshold, thus the upper surface of the second structured surface 12 has a high plainness.

[0120] In one embodiment, the filler material to be filled includes a silica dioxide (SiO.sub.2), alumina (Al.sub.2O.sub.3), titanium dioxide (TiO.sub.2).

[0121] In one embodiment, the structured layers to be manufactured includes a silicon nitride (Si.sub.3N.sub.4), poly-crystalline silicon (Poly), titanium dioxide (TiO.sub.2), alumina (Al.sub.2O.sub.3), silicon dioxide (SiO.sub.2), indium tin oxide (ITO), niobium oxide (Ni.sub.2O.sub.5), magnesium fluoride (MgF.sub.2).

[0122] In one embodiment, after lithographing and etching the structured layer, the obtained array of the nanostructures in the structured surface may be positive nanostructures, or the obtained array of the nanostructures in the structured surface may be negative nanostructures.

[0123] In one embodiment, the positive nanostructures refer to the nanostructures consisting of the residual nanostructured layer after etching; in this situation, the pattern of the residual photoresist after lithographing and etching and the pattern of the nanostructures consisting of the residual nanostructured layer after etching are the same. The negative nanostructures refer to the nanostructures consisting of the removed nanostructured layer after etching. In this situation, the pattern of the residual photoresist after lithographing and etching and the pattern of the residual structured layer after etching are complementary.

[0124] If the array of positive nanostructures obtained by etching, the pattern of the residual photoresist after exposing and developing the photoresist, the pattern of the residual photoresist will be complementary patterns with the pattern of the array of nanostructures. Therefore, the structured layer according to the residual photoresist, the array of positive nanostructures with the same pattern is obtained by etching. If the array of negative nanostructures is obtained by etching, the pattern of the residual photoresist after exposing and developing the photoresist, the pattern of the residual photoresist will be complementary patterns with the pattern of the array of nanostructures. Therefore, the structured layer according to the residual photoresist, the array of negative nanostructures with the same pattern is obtained by etching.

[0125] FIG. 15 shows a schematic diagram of the obtained structure after the lithography of array of negative nanostructures in the first structured layer 111. FIG. 16 shows a schematic diagram of the obtained structure after etching the array of negative nanostructures in the first structured layer 111.

[0126] As shown from FIG. 15 to FIG. 16, in the present embodiment, similar to the array of negative nanostructures, the location marker 113 to be manufactured in the first structured surface is the negative structure. In this situation, after manufacturing the first structured layer 111, the upper surface of the first structured layer 111 is coated with the photoresist 112. Therefore, the photoresist 112 is exposed and developed according to the obtained location distribution and the array of nanostructures 114, and the shape of the nanostructures 114, so that the pattern of the residual photoresist 112 just constitutes the pattern of the array of nanostructures 114 obtained by the target, or the complementary pattern of the array of nanostructures 114 obtained by the target. Then the portion of the M.sub.th structured surface exposed to the photoresist 112 is etched, that is, an array of negative nanostructures 114 and the negative location marker 113 located above the upper surface of the structured surface manufactured previously.

[0127] In one embodiment, in the N structured surfaces in the multi-layer metalens, there is at least one structured surface consisting of positive nanostructures, and there is at least one structured surface consisting of negative nanostructures.

[0128] Because the dispersion curve of positive nanostructures has the opposite trend with the dispersion curve of negative nanostructures, it is beneficial to realize the chromatic aberration compensation of the multi-layer metalens by setting the multiple structured surfaces with positive and negative nanostructures.

[0129] FIG. 17 shows a schematic diagram of the obtained structure after the lithography of the array of negative nanostructures 124 in the second structured layer 121. FIG. 18 shows a schematic diagram of the obtained structure after lithographing the array of negative nanostructures 124 in the second structured layer 121. FIG. 19 shows a schematic diagram of the obtained structure after filling the second filler material 125 in the array of negative nanostructures 124. FIG. 20 shows a schematic diagram of the obtained structure after polishing the array of negative nanostructures 124 on the upper surface of the second structured surface 12.

[0130] As shown from FIG. 3 to FIG. 10, and the description above from FIG. 3 to FIG. 10, the first structured surface 11 with the array of the nanostructures 114 is composed of positive structures. Further, referring to FIG. 17 to FIG. 20, in one embodiment, a first structured surface 11 with the array of nanostructures 114 consisting of positive nanostructures have been manufactured, a second structured layer 121 has also been manufactured on the first structured surface 11, and the alignment window 123 has also been manufactured on the second structured layer 121.

[0131] Therefore, through the alignment window 123, based on the location marker 113, the array of nanostructures 124 to be manufactured is pre-located accurately. Then according to the position distribution of the array of nanostructures 124 and the shape of nanostructures 124 to be manufactured, the residual photoresist 122 after manufacturing the alignment window 123 is exposed and developed again, so that the pattern of the residual photoresist 122 just constitutes the pattern of the array of nanostructures obtained by the target, or the complementary pattern of the array of nanostructures obtained by the target when the area of the alignment window 123 is excluded. Then the portion of the second structured layer 121 exposed to the photoresist 122 is etched, that is, an array of negative nanostructures 124 located above the upper surface of the structured surface manufactured previously.

[0132] Then the second filler material 125 is filled between the array of the negative nanostructures 124, therefore the second structured surface 12 is obtained. Then the upper surface of the second structured surface 12 is thinned and polished, so as to obtain the multi-layer metalens as shown in FIG. 20.

[0133] As shown in FIG. 20, the multi-layer metalens includes two structured surfaces. The array of nanostructures in the first structured surface 11 consists of the positive nanostructures, and the array of nanostructures in the second structured surface 12 consists of the negative nanostructures.

[0134] In one embodiment, manufacturing the alignment window based on the marker location in the structured surface manufactured previously includes: manufacturing the alignment window based on the marker location in the first structured surface. A projection of the location marker of the structured surface manufactured previously on a parallel surface of the wafer is located inside a projection of the alignment window in the structured surface manufactured previously on a parallel surface of the wafer.

[0135] In one embodiment, through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the structured surface manufactured previously includes: through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the first structured surface.

[0136] Specifically, in one embodiment, in the N structured surfaces in the multi-layer metalens, only the location marker needs to be manufactured in the first structured surface 11. Therefore, when manufacturing the M.sub.th structured surface, according to the position distribution and shape of the location marker 113 in the first structured surface 11, the alignment window is manufactured.

[0137] The projection of the location marker of the first structured surface on a parallel surface of the wafer is located inside a projection of the alignment window in manufactured structured surface on a parallel surface of the wafer. That is, the alignment window matches with the location marker 113 of the first structured surface 11 in the perpendicular direction, and the shape of the location marker 113 is less than the alignment window.

[0138] Therefore, through the alignment window, the location marker 113 of the first structured surface 11 is located accurately. In this way, based on the location marker 113, the M.sub.th structured surface is manufactured, so that the position of array of nanostructures in the M.sub.th structured surface matches with the position of array of nanostructures 114 in the first structured surface 11.

[0139] Since except for the first structured surface 11 in the present embodiment, each structured surface doesn't need to have location marker, the present embodiment can improve the manufacturing speed of the multi-layer metalens effectively.

[0140] It should be noted that if each structured surface doesn't have location marker except for the first structured surface 11, with the increasing of M, the thickness between the alignment window in the M.sub.th structured surface and the location marker of the first structured surface 11 will accumulate gradually. Thus, the location marker 113 is located through the alignment window. It is understandable that the greater the accumulation of location deviation for the location marker 113, the more significant the position deviation will be between the arrays of nanostructures of the first structured surface and the arrays of nanostructures of the M.sub.th structured surface.

[0141] Therefore, to restrain accumulation the location deviation layer by layer as far as possible, in one embodiment, manufacturing the alignment window based on the location marker of the structured surface manufactured previously includes: manufacturing the alignment window based on the location marker of the structured surface manufactured previously; wherein the projection of the location marker of the structured surface manufactured previously is located inside the projection of the alignment window on the parallel surface of the wafer.

[0142] In the present application, through the alignment window, manufacturing M.sub.th structured surface based on the location marker of the structured surface manufactured previously includes: through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the M1.sub.th structured surface; wherein when M<N, the M.sub.th structured surface further includes the location marker.

[0143] Specifically, in the present embodiment, in N structured surfaces of the multi-layer metalens, except for the N.sub.th structured surface manufactured finally doesn't have the location marker, other structured surfaces have been manufactured with location markers. Therefore, when the M.sub.th structured surface is manufactured, according to the position distribution and shape of the location marker of the M1.sub.th structured surface, the alignment window is manufactured.

[0144] The projection of the location marker of the first structured surface on a parallel surface of the wafer 10 is located inside a projection of the alignment window in manufactured structured surface on a parallel surface of the wafer 10. That is, the alignment window matches with the location marker 113 of the first structured surface 11 in the perpendicular direction, and the shape of the location marker 113 is less than the alignment window.

[0145] Therefore, through the alignment window, the location marker of the M1.sub.th structured surface is located accurately. Then based on the location marker of the M1.sub.th structured surface, the M.sub.th structured surface is manufactured, so that position of the array of nanostructures in the M.sub.th structured surface matches with the position of the array of nanostructures in the M1.sub.th structured surface.

[0146] Therefore, in the present application, except for the N.sub.th structured surface manufactured finally, all other structured surfaces have location marker, even with the increasing of M, the thickness between the alignment window in the M.sub.th structured surface and the location marker of the M1.sub.th structured surface will not accumulate. Therefore, when locating the location marker of the structured surface of the previous manufactured layer through the alignment window, the location deviation will not be accumulated layer by layer significantly, due to the increasing of M.

[0147] Therefore, this embodiment effectively suppresses the layer-by-layer accumulation of localization deviations, thus improving the control accuracy of the relative positions between the positions of arrays of nanostructures in different structured surfaces.

[0148] In one embodiment, in N structured surfaces of multi-layer metalens, except for the N.sub.th structured surface manufactured finally, other structured surfaces all have location markers. Moreover, the projections in the structured surfaces on the parallel surface of the wafer 10 will not overlap.

[0149] In one embodiment, for the M.sub.th structured surface, when locating the location marker of the structured surface manufactured previously through the alignment window, it will not be disturbed by the location marker of the T.sub.th structured surface by controlling the location marker of each structured surface does not overlap with each other. The T.sub.th structured surface is located in front of the M1.sub.th structured surface.

[0150] For example, when M=4, T=2 or 1. That is, for the fourth structured surface, when locating the location marker of the third structured surface through the alignment window, it will not be disturbed by the location marker of the second structured surface 12 and the location marker 113 of the first structured surface 11.

[0151] FIG. 21 shows a top view of the first structured surface 11 provided by the present application. FIG. 22 shows a top view of the second structured surface 12 provided by the present application.

[0152] As shown from FIG. 21 to FIG. 22, in one embodiment, for the multi-layer metalens, there are two location markers 113 of the first structured surface 11, and there are two location markers 126 of the second structured surface 12.

[0153] When observing the first structured surface 11 from a specific orientation, the two location markers 113 are arranged up and down. When the second structured surface 12 is viewed from the same orientation, the two location markers 126 of the second structured surface 12 are arranged left and right.

[0154] It can be seen that the projection of the location marker 113 of the first structured surface 11 on the parallel surface of the wafer 10 will not overlap with the projection of the location marker 126 on the second structured surface 12 on the parallel surface of the wafer 10. Therefore, when the third structured surface is manufactured, through the alignment window, the location marker 126 of the second structured surface 12 is located, it is not distributed by the location marker 113 of the first structured surface 11.

[0155] A multi-layer metalens is provided by the present application. As shown in FIG. 1 and the description of FIG. 1, the specific structural details of the multi-layer metalens provided in this application will not be described here. The multi-layer metalens provided in this application is manufactured by the method provided in any of the above method embodiments. Referring to any of the above embodiments of the manufacturing method, the specific implementation details of the multi-layer metalens provided in this application are not described here.

[0156] FIG. 23 shows a block diagram of a manufacturing device for a multi-layer metalens provided in the present application. The multi-layer metalens provided in the present application the multi-layer metalens includes a plurality of N structured surfaces arranged in a vertical direction on one surface of a wafer, N2; the manufacturing device includes:

[0157] A manufacturing module of the first structured surface 31, the manufacturing module of the first structured surface is configured to manufacture the first structured surface on the target surface of the wafer when the first structured surface to be manufactured; wherein the first structured surface includes the array of nanostructures and location marker;

[0158] A manufacturing module of the M.sub.th structured surface 32, the manufacturing module of the M.sub.th structured surface is configured to manufacture an alignment window based on the location marker manufactured previously; and through the alignment window, manufacturing the M.sub.th structured surface based on the location marker of the structured surface manufactured previously; the M.sub.th structured surface includes a plurality of nanostructures; and the plurality of nanostructures are arranged in an array; the array of nanostructures in the M.sub.th structured surface matches with the array of nanostructures in the M1.sub.th structured surface; MN, and M>1.

[0159] In one embodiment, the manufacturing module of the M.sub.th structured surface 32 is configured to manufacture the alignment window of the M.sub.th structured surface based on the location marker of the M1.sub.th structured surface; through the alignment window, based on the location marker to manufacture the M.sub.th structured surface. A projection of the location marker of the structured surface manufactured previously on a parallel surface of the wafer is located inside a projection of the alignment window of the structured surface manufactured previously on a parallel surface of the wafer.

[0160] In one embodiment, the manufacturing module of the M.sub.th structured surface 32 is configured to manufacture the alignment window based on the location marker of the manufactured M1.sub.th structured surface; wherein the projection of the location marker of the M1.sub.th structured surface on the parallel surface of the wafer is located inside the projection of the alignment window of the parallel surface of the wafer;

[0161] through the alignment window, the manufacturing module of the first structured surface 31 is configured to manufacture the M.sub.th structured surface based on the location marker of the structured surface manufactured previously; when M<N, the M.sub.th structured surface further includes a location marker.

[0162] In one embodiment, the projections of the location markers in the structured surfaces on the parallel surface of the wafer will not overlap with each other.

[0163] In one embodiment, the manufacturing module of the first structured surface 31 is configured to manufacture the first structured surface on the target surface of the wafer, and lithography and etch the first structured surface, so as to obtain the array of nanostructures and location marker on the target surface;

[0164] and the manufacturing module of the first structured surface 31 is configured to fill a first filler material between the nanostructures and the location marker to obtain the first structured layer.

[0165] In one embodiment, the manufacturing module of the M.sub.th structured surface 32 is configured to manufacture the M.sub.th structured surface based on the location marker of the manufactured M1.sub.th structured surface, and lithograph and etch the M.sub.th structured surface to obtain the alignment window;

[0166] through the alignment window, the manufacturing module of the M.sub.th structured surface 32 is configured to pre-locate the array of nanostructures to be manufactured in the M.sub.th structured surface based on the location marker of the structured surface manufactured previously;

[0167] and the manufacturing module of the M.sub.th structured surface 32 is configured to fill an M.sub.th filler material between the nanostructures on the M1.sub.th structured surface to obtain the M.sub.th structured layer.

[0168] In one embodiment, the manufacturing device provided by the present application is configured to thin and polish an upper surface of the obtained structured surface after filling.

[0169] In one embodiment, after lithographing and etching the structured surface, the obtained nanostructures on the structured surface are positive nanostructures. In one embodiment, after lithographing and etching the structured surface, the obtained nanostructures on the structured surface are negative nanostructures.

[0170] This application also provides an electronic device. The electronic device is in the form of a universal computing device. The components of an electronic device may include, but are not limited to, at least one processor, at least one memory, and a bus connecting different system components (including memory and processor). The processor may include each of the modules in the apparatus as shown in FIG. 23.

[0171] The memory is stored with a program code, which may be executed by the processor, causing the processor to perform the steps of the exemplary embodiments described in the various exemplary embodiments described above. For example, the processor may perform each of the steps of the manufacturing method as shown in FIG. 2.

[0172] The memory may include readable media in the form of volatile memory, such as random access memory (RAM) and/or cache memory, and may further include a read-only memory (ROM).

[0173] The memory may also include a program/utility having a set of (at least one) of program modules including, but not limited to, the operating system, one or more applications, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0174] A bus may be a local bus representing one or more of several types of bus structures, including a memory bus or memory controller, peripheral bus, graphics acceleration port, processor, or using any bus structure in a variety of bus structures.

[0175] The present application also provides a computer readable storage medium storing computer readable instructions that cause the computer to execute the manufacturing method provided by any of the manufacturing method embodiment when executed by the processor of the computer.

[0176] The above is only a specific embodiment of the embodiment of this disclosure, but the scope of protection of the embodiment of this disclosure is not limited to this, any person familiar with the scope of the change or substitution, should be covered within the protection scope of the embodiment of this disclosure. Therefore, the scope of the protection of the present disclosure shall depend to the scope of the claim.