LOW-POWER MAGNETIC SENSING DEVICE AND MAGNETIC SWITCH DEVICE COMPRISING THE MAGNETIC SENSING DEVICE
20250247095 ยท 2025-07-31
Assignee
Inventors
Cpc classification
G01R33/0088
PHYSICS
G01R33/098
PHYSICS
International classification
Abstract
Magnetic sensing device integrated in a magnetic switch device that makes or breaks contact in the presence of an external magnetic field, comprising: a first transistor biased at a first terminal by a first bias voltage and a first magnetoresistive element having a first resistance variable with the external magnetic field. At a reference field strength, the first resistance has a first reference resistance value, and the first bias voltage is adjustable to control a first current at the second terminal of the first transistor at a first reference current value. When the external magnetic field is varied around the reference field strength, the first variable resistance varies around the first reference resistance value by a resistance delta, such that the first current modulates around the first reference current value by a current delta. A magnetic switch device comprising the magnetic sensing device is also disclosed.
Claims
1. A magnetic sensing device configured to be integrated in a magnetic switch device, the magnetic sensing device comprising: at least one tunnel magnetoresistive (TMR) element having a TMR resistance that varies with an external magnetic field; said least one TMR element being coupled to a first power supply rail providing a supply voltage substantially independent of the external magnetic field; said least one TMR element being further coupled to a third terminal of a first transistor, the first transistor being biased at a first terminal by a first bias voltage; wherein, at a reference field strength of the external magnetic field, the TMR resistance has a TMR reference resistance value, and the first bias voltage is adjustable to control a first current at a second terminal of the first transistor at a first reference current value; and wherein said at least one TMR element is configured such that, when the external magnetic field is varied around the reference field strength, the TMR resistance varies around the TMR reference resistance value by a resistance delta, such that the first current modulates around the first reference current value by a current delta.
2. A magnetic switch device configured to generate two distinct logic levels in response to a sensed magnetic field strength of an external magnetic field, the magnetic switch device comprising: at least one TMR element having a TMR resistance that varies with the external magnetic field; said least one TMR element being coupled to a first power supply rail providing a supply voltage substantially independent of the external magnetic field; said least one TMR element being further coupled to a third terminal of a first transistor, the first transistor being biased at a first terminal by a first bias voltage; wherein, at a reference field strength of the external magnetic field, the TMR resistance has a TMR reference resistance value, and the first bias voltage is adjustable to control a first current at a second terminal of the first transistor at a first reference current value; and wherein said at least one TMR element is configured such that, when the external magnetic field is varied around the reference field strength, the TMR resistance varies around the TMR reference resistance value by a resistance delta, such that the first current modulates around the first reference current value by a current delta; wherein the magnetic switch device further comprises a second transistor biased at a first terminal of the second transistor by a second bias voltage, a second terminal of the second transistor being connected to the second terminal of the first transistor at a node; and wherein the second bias voltage is adjustable to control a second current at the second terminal of the second transistor such that the second current is substantially equal to the first reference current value of the first transistor.
3. The magnetic switch device according to claim 2, wherein said at least one TMR element comprises a first TMR element, having a first TMR resistance and coupled to a third terminal of the first transistor and to a first power supply rail; wherein, at a reference field strength of the external magnetic field, the first TMR resistance has a first TMR reference resistance value wherein the first TMR element is configured such that, when the external magnetic field is varied around the reference field strength, the first TMR resistance varies around the first TMR reference resistance value by a resistance delta, such that the first current modulates around the first reference current value by a current delta.
4. The magnetic switch device according to claim 2, wherein, when the external magnetic field is varied around the field strength reference value, an output voltage at the node is substantially equal to the first current delta multiplied by an equivalent output impedance at the node.
5. The magnetic switch device according to claim 3, said at least one TMR element further comprises a second TMR element connected to the second transistor; wherein the second TMR element has a second TMR resistance that varies with the external magnetic field; wherein, at the reference field strength of the external magnetic field, the second TMR resistance has a second TMR reference resistance value, and the second bias voltage is adjustable to control the second current at the second terminal of the second transistor at a second reference current value; and wherein the second TMR element is configured such that, when the external magnetic field is varied around the reference field strength, the second TMR resistance varies around the second TMR reference resistance value by a second resistance delta, such that the second current is modulated around the second reference current value by a current delta.
6. The magnetic switch device according to claim 5, wherein the first and second TMR elements are configured to be sensitive to the external magnetic field in opposite directions, such that, when the external magnetic field varies around the field strength reference value, the second TMR resistance is configured to vary around the second TMR reference resistance value by a second resistance delta having a polarity opposed to the one of the first resistance delta; and wherein an output voltage at the node is substantially equal to twice the value of the current delta multiplied by an equivalent output impedance at the node.
7. The magnetic switch device according to claim 3, further comprises a first cascode transistor, connected to the first transistor and biased by a first cascode bias voltage; and a second cascode transistor, connected to the second transistor and biased by a second cascode bias voltage.
8. The magnetic switch device according to claim 7, further comprising at least one setting resistance element having an adjustable resistance.
9. The magnetic switch device according to claim 8, wherein said at least one setting resistance element comprises a first setting resistance element having an adjustable resistance; wherein the first setting resistance element is connected to a third transistor and a third cascode transistor; wherein the third cascode transistor is connected to a fourth cascode transistor and a fourth transistor; wherein the first and third transistors are biased by the first bias voltage, and the first and third cascode transistors are biased by the first cascode bias voltage; wherein the second and fourth cascode transistors are biased by the second cascode bias voltage, and the second and fourth transistors are biased by the second bias voltage.
10. The magnetic switch device according to claim 9, wherein the first setting resistance element is configured such that its resistance value matches the first TMR resistance value of the first TMR element, and such that the second current controlled by the second transistor and of the second cascode transistor is substantially equal to the first current controlled by the first transistor and of the first cascode transistor.
11. The magnetic switch device according to claim 9, further comprising a second setting resistance element comprising an adjustable resistance, the second setting resistance element being connected the second transistor; and a second TMR element connected to the fourth transistor, the second TMR element having a second TMR resistance that varies with the external magnetic field.
12. The magnetic switch device according to claim 11, wherein the first and second setting resistance elements are configured such that the first and second adjustable resistances have substantially the same value.
13. The magnetic switch device according to claim 2, wherein said at least one TMR element comprises at least a magnetic tunnel junction including a reference layer having a fixed reference magnetization; a ferromagnetic sense layer having a free sense magnetization that is orientable relative to the fixed reference magnetization in the presence of an external magnetic field; and a tunnel barrier layer between the reference layer and the sense layer; and wherein the reference layer comprises a synthetic antiferromagnet structure.
14. The magnetic switch device according to claim 13, wherein said at least one TMR element has a magnetoresistance value larger than 100%.
15. The magnetic switch device according to claim 13, wherein the sense layer is configured to have a vortex configuration of magnetization and to have complete vortex expulsion at a magnetic field that is below 20 mT, notably below 14 mT.
16. The magnetic switch device according to claim 13, wherein the sense layer has a magnetic anisotropy so that the vortex configuration is spontaneously achieved below a positive field threshold.
17. The magnetic switch device according to claim 13, wherein said at least one TMR element comprises a plurality of magnetic tunnel junctions; and wherein a distance between each magnetic tunnel junction is greater than the lateral size of the magnetic tunnel junction.
18. The magnetic switch device according to claim 13, wherein the magnetic tunnel junction has a lateral size larger than 1 m; and wherein the thickness of the magnetic tunnel junction is 30 nm and 80 nm.
19. The magnetic switch device according to claim 8, wherein said at least one setting resistance element comprises a plurality of poly fuses connected in parallel with a plurality of resistance segments, the setting resistance element being programmable to adjust the adjustable setting resistances to a predetermined resistance value by trimming any one of the poly fuses.
20. The magnetic switch device according to claim 19, wherein said at least one setting resistance element comprises a combination of at least two different types of resistors, configured to have substantially the same temperature coefficient of resistance (TCR) as the TCR of the TMR element.
Description
BRIEF DESCRIPTION
[0011] The foregoing features may be more fully understood from the following description of the drawings. The drawings aid in explaining and understanding the disclosed technology. Since it is often impractical or impossible to illustrate and describe every possible embodiment, the provided figures depict one or more illustrative embodiments. Accordingly, the figures are not intended to limit the scope of the broad concepts, systems and techniques described herein. Like numbers in the figures denote like elements.
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DETAILED DESCRIPTION
[0025]
[0026] At a reference field strength H.sub.0 of the external magnetic field, the first TMR resistance R.sub.SNS1 of the first TMR element 31 has a first TMR reference resistance value R.sub.SNS10. At a reference field strength H.sub.0, the first bias voltage V.sub.PBIAS1 at the first terminal of the first transistor P1 can be adjusted to control a first current i.sub.SNS1 at the second terminal of the first transistor P1 at a first reference current value i.sub.SNS10.
[0027] When the external magnetic field is varied around the reference field strength H.sub.0 by a field strength delta h, the first TMR resistance R.sub.SNS1 varies around the first TMR reference resistance value R.sub.SNS10 by a resistance delta R.sub.SNS. The first current i.sub.SNS1 is then modulated around the first reference current value i.sub.SNS10 by a current delta i.sub.SNS. Thus, the sensitivity of the first TMR element 31 corresponds to the ratio of the resistance delta to the field strength delta R.sub.SNS/h. The first bias voltage V.sub.PBIAS1 does not vary with the varying external magnetic field.
[0028] In the configuration of
[0029]
[0030] The node CMP between the first and second transistor P1, N1 is characterized by a high impedance as is formed by the second terminals of first and second transistors P1, N1. In
[0031] When the external magnetic field is varied around the reference field strength H.sub.0 by a field strength delta h, the first TMR resistance R.sub.SNS1 varies around the first TMR reference resistance value R.sub.SNS10 by a resistance delta R.sub.SNS. Since the first bias voltage V.sub.PBIAS1 is constant (e.g., independent of magnetic field strength), the first current i.sub.SNS1 is modulated around the first reference current value i.sub.SNS10 by a first current delta i.sub.SNS1. The second current i.sub.SNS2 is substantially equal to the first reference current value i.sub.SNS10. Consequently, the first current delta i.sub.SNS1 at the high-impedance node CMP develops a large output voltage at node CMP. The output voltage is substantially equal to the first current delta i.sub.SNS1 multiplied by the equivalent output impedance r.sub.cmp at the node CMP. Depending on the polarity of the field strength delta h, the node voltage V.sub.cmp at the node CMP moves towards one of the two voltage levels (positive or negative supply rails), representing two logic levels.
[0032] In one aspect, the magnetic switch device 50 of
[0033]
[0034] At the reference field strength H.sub.0 of the of the external magnetic field, the second TMR resistance R.sub.SNS2 has a second TMR reference resistance value R.sub.SNS20 and the second bias voltage V.sub.PBIAS2 is adjustable to control the second current i.sub.SNS2 at the second terminal of the second transistor P1 at a second reference current value i.sub.SNS20.
[0035] When the external magnetic field is varied around the reference field strength H.sub.0, the second TMR resistance R.sub.SNS2 varies around the second TMR reference resistance value R.sub.SNS20 by a second resistance delta A.sub.RSNS2. The second current i.sub.SNS2 is modulated around the second reference current value i.sub.SNS20 by a second current delta A.sub.iSNS2.
[0036] The second bias voltage V.sub.NBIAS1 at the first terminal of the second transistor N1 can be adjusted to control the second current i.sub.SNS2 at the second terminal of the second transistor N1, such that the second current i.sub.SNS2 is substantially equal to the first current i.sub.SNS1 controlled by the first transistor P1.
[0037] In one aspect, the first and second TMR elements 31, 32 can be programmed to be sensitive to the external magnetic field in opposite directions. In other words, the first TMR resistance R.sub.SNS1 of the first TMR element 31 increases with the increasing external magnetic field and the second TMR resistance R.sub.SNS2 of the second TMR element 32 decreases with the decreasing external magnetic field, or vice-versa.
[0038] In such configuration, when the external magnetic field varies around the field strength reference value H.sub.0 by a field strength delta h, the second TMR resistance R.sub.SNS2 varies around the second TMR reference resistance value R.sub.SNS20 by a resistance delta R.sub.SNS2 having a polarity opposed to the one of the resistance delta R.sub.SNS1 of the first TMR resistance R.sub.SNS1. More generally, a variation in the external magnetic field around the field strength reference value H.sub.0 by a field strength delta h results in the first TMR resistance R.sub.SNS1 of the first TMR element 31 to vary around the first TMR reference resistance value R.sub.SNS10 by a positive (or negative) resistance delta R.sub.SNS1. The second TMR resistance R.sub.SNS2 of the second TMR element 32 varies around the second TMR reference resistance value R.sub.SNS20 by a negative (or positive) resistance delta R.sub.SNS2.
[0039] Since the first and second bias voltages V.sub.PBIAS1, V.sub.PBIAS2 are constant (e.g., independent of magnetic field strength), the first current i.sub.SNS1 is modulated by a positive (or negative) first current delta +i.sub.SNS1 (i.sub.SNS1) and the second current i.sub.SNS2 of the second transistor N1 is modulated by a negative (or positive) second current delta i.sub.SNS2 (+i.sub.SNS2). At the node CMP, the output voltage V.sub.out corresponds to the difference of the values of the first and second current deltas i.sub.SNS1 and i.sub.SNS2, around the first and second currents i.sub.SNS1, i.sub.SNS2, multiplied by an equivalent output impedance r.sub.cmp. If the first current delta i.sub.SNS1 around the first current i.sub.SNS1 is equal to the second current delta i.sub.SNS2 around the second current i.sub.SNS2, the output voltage V.sub.out corresponds to twice the current delta i.sub.SNS (V.sub.out=2* i.sub.sns*r.sub.cmp) at the high-impedance node CMP, where i.sub.SNS=i.sub.SNS1=i.sub.SNS2.
[0040] Depending on the polarity of the external magnetic field variation, the node voltage V.sub.cmp at the node CMP moves towards one of the two voltage levels (positive or negative supply rails), representing two logic levels.
[0041] The configuration of
[0042] In some other embodiments, the first and/or second transistor P1, N1 can be cascoded to increase its output impedance.
[0043]
[0044] The additional first and second cascode transistors P2, N2 allows for increasing the equivalent output impedance r.sub.cmp at the node CMP.
[0045]
[0046] At a reference field strength H.sub.0, the first and second bias voltages V.sub.PBIAS1, V.sub.PBIAS2 at the first terminal of the, respectively, first transistor P1 and first cascode transistor P2 can be adjusted to control the first current i.sub.SNS1 at the second terminal of the transistors P1 and P2 at a first reference current value i.sub.SNS10.
[0047] In one aspect, the first setting resistance element 33 is configured to have a first adjustable resistance R.sub.SET1. The first setting resistance element 33 can be configured such that the first adjustable resistance R.sub.SET1 matches the first resistance R.sub.SNS1 of the first TMR element 31 and such that the second current i.sub.SNS2 controlled by the second transistor N1 and of the second cascode transistor N2 is substantially equal to the first current i.sub.SNS1 controlled by the first transistor P1 and of the first cascode transistor P2. The transistors P3, P4, N3, N4 control a setting current i.sub.SET in the second branch 120.
[0048] The magnetic switch device 50 of
[0049]
[0050] The magnetic switch device 50 of
[0051] In an embodiment, the first and second setting resistance element 33, 34 can comprise a trimmable resistance element. The resistance value of the first and second setting resistance element 33, 34 can then be adjusted by trimming.
[0052] The first and second setting resistance elements 33, 34 can be adjusted such that the respective first and second adjustable resistances R.sub.SET1, R.sub.SET2 have substantially the same value. It should be noted that the first and second setting resistance elements 33, 34 can be adjusted such that the values of the respective first and second adjustable resistances R.sub.SET1, R.sub.SET2 differ by less than 1%, or less than 2%, or less than 5%. The transistors P3, P4, N3, N4 control a setting current i.sub.SET in the second branch 120.
[0053] In another aspect, each of the first and second setting resistance elements 33, 34 can comprise a TMR element which can be programmed to be sensitive to opposite polarity of the external magnetic field. In this configuration, the magnetic sensing device 10 can show an increase in its sensitivity of about four time, compared to the sensitivity of the magnetic sensing device 10 of
[0054] In yet another aspect, the first setting resistance element 33 can be adjusted to have a resistance value that corresponds substantially to the first TMR reference resistance value R.sub.SNS10 of the first TMR element 31 at reference field strength H.sub.0. Similarly, the second setting resistance element 34 can be adjusted to have a resistance value that corresponds substantially to the second TMR reference resistance value R.sub.SNS20 of the second TMR element 32 at reference field strength H.sub.0.
[0055] In yet another aspect, the first setting resistance element 33 can be adjusted to have a resistance value substantially identical to the second setting resistance element 34.
[0056] In the configurations shown in
[0057] Similarly, in the configurations shown in
[0058] Other configurations of the magnetic switch device 50 can be contemplated. For example, any one of the first transistor P1, the first cascode transistor P2, the third transistor P3, and/or the third cascode transistor P4 can comprise any one of a MOSFET transistor of PMOS type or a BJT transistor of PNP type. Similarly, any one of the second transistor N1, the second cascode transistor N2, the fourth transistor N3, and/or the fourth cascode transistor P4 can comprise any one of a MOSFET transistor of NMOS type or a BJT transistor of NPN type.
[0059] Other configurations of the magnetic switch device 50 include having the first transistor P1, the first cascode transistor P2, the third transistor P3, and/or the third cascode transistor P4 having a negative polarity (NMOS or NPN), and the second transistor N1, the second cascode transistor N2, the fourth transistor N3, and/or the fourth cascode transistors N4 having a positive polarity (PMOS or PNP). Depending on the transistor type, the first and/or second TMR element 31, 32 can be connected to the positive or negative supply rail.
[0060] In an embodiment, the TMR element of the first and/or second TMR element 31, 32, and possibly the first and second setting resistance elements 33, 34, comprise a one or a plurality of tunnel magnetic junctions (MTJs).
[0061] An exemplary MTJ 2 is represented in
[0062] Each of the reference and sense layers 21, 23 can include, or be formed of, a magnetic material and a magnetic material of the ferromagnetic type. The sense ferromagnetic layer 23 can include a soft ferromagnetic material, namely one having a relatively low coercivity, while the reference ferromagnetic layer 21 can include a hard ferromagnetic material, namely one having a relatively high coercivity. In such manner, a sense magnetization 230 of the sense ferromagnetic layer can be readily varied under low-intensity magnetic fields at which the reference magnetization 210 of the reference layer 21 remains fixed and is used as a reference layer. Suitable ferromagnetic materials include transition metals, rare earth elements, and their alloys, either with or without main group elements. For example, suitable ferromagnetic materials include iron (Fe), cobalt (Co), nickel (Ni), and their alloys, such as permalloy (or Ni80Fe20); alloys based on Ni, Fe, and boron (B); Co90Fe10; and alloys based on Co, Fe, and B. In some instances, alloys based on Ni and Fe (and optionally B) can have a smaller coercivity than alloys based on Co and Fe (and optionally B).
[0063] The tunnel barrier layer 22 comprises, or is formed of, an insulating material. Suitable insulating materials include oxides, such as aluminum oxide (e.g., Al.sub.2O.sub.3) and magnesium oxide (e.g., MgO). A thickness of the tunnel barrier layer 22 can be in the nm range, such as from about 1 nm to about 10 nm. Large TMR can be obtained for the MTJ 2 comprising a crystalline MgO-based tunnel barrier layer 22.
[0064] The MTJ 2 can be optimized for a magnetic switch application. In an embodiment, the optimized MTJ 2 can have a resistance value that varies over a wide magnetic field range from 0 to 200 mT. Moreover, The TMR element can have a high magnetoresistance (MR) value, such that the TMR element can advantageously achieve a high signal to noise ratio (SNR) and a high degree of accuracy in the magnetic sensing device 10. Preferably, the MTJ 2 has a magnetoresistance value larger than 100% and preferably larger than 200%. Moreover, the resistance value of the MTJ 2 should be large to reduce the power consumption of the device. For example, the resistance value of the MTJ 2 can be greater than 3 M.
[0065] A high MR value can be obtained by the reference layer 21 comprises a synthetic antiferromagnet (SAF) structure. As shown in the example of
[0066] For a given lateral size of the MTJ 2, increasing the thickness of the sense layer 23 or increasing the sense magnetization 230, increase the expulsion field of the vortex. The thickness of the sense layer 23 can be between 10 nm and 60 nm, for example about 30 nm. On the other hand, the vortex nucleation field, below which the vortex configuration of magnetization is always formed, should remain positive and as large as possible, such as be greater than 1 mT.
[0067] In one aspect, the MTJ 2 comprises a sense layer 21 including, or being formed of, a magnetic material of the ferromagnetic type having a sufficiently low magnetic anisotropy so that in the chosen geometry of the TMR element, the magnetic vortex configuration is formed spontaneously (nucleated) with a nucleation field >1 mT. For example, the sense layer 21 includes, or is formed of, a NiFe-based alloy.
[0068] In a preferred embodiment, the lateral size of the magnetic tunnel junction 2, the thickness of the sense layer 23, and the sense magnetization 230 can be chosen such as to result in complete vortex expulsion below an external magnetic field threshold that is equal or below about 20 mT or below about 14 mT.
[0069] Preferably, the MTJ 2 has a lateral size larger than 1 m. The thickness of the magnetic tunnel junction 2 can be between 30 nm and 80 nm, for example about 50 nm.
[0070] The TMR element can comprise one or a plurality of MTJ 2. As illustrated in
[0071]
[0072] Other configurations of the MTJ 2 and/or of the sense layer 23 can be considered (such as different lateral sizes, different arrangements and ferromagnetic material of the sense and reference layers 23, 21), depending on specific field-response threshold requirements of the application.
[0073]
[0074] The TMR element 31, 32 comprising at least one MTJ2 can thus have a narrow linear region. In other words, the complete vortex expulsion occurs below a field threshold that is equal to or below about 20 mT or below about 14 mT. For a magnitude of the external magnetic field above the field threshold the sense magnetization 230 of the TMR element 31, 32 is saturated. The nucleation field H.sub.nucl can be lower than 10 mT, for example, lower than 5 mT or 2 mT. A larger nucleation field, which is always lower than the expulsion field, is advantageous so that the vortex state is easily recovered when the external field is reduced below the high-field threshold field.
[0075] It is understood that the present invention is not limited to the exemplary embodiments described above and other examples of implementations are also possible within the scope of the patent claims.
[0076] For example, the TMR element 31, 32 can comprise at least one MTJ 2, wherein the sense layer 23 of the MTJ 2 does not comprise a vortex configuration, in other words, wherein the MTJ 2 does not operate in a vortex mode. For instance, the MTJ 2 can be operated in a spin-valve mode, with a specific sensitivity axis of the sense layer 23. The sense layer 23 can comprise a single ferromagnetic layer, an unpinned antiferromagnetic-coupled bilayer, trilayer, or multilayer. In that case the sensitivity axis is given by the axis of the reference layer magnetization, and the low-field and high-field thresholds by magnetic field biasing of the sense layer magnetization. This magnetic field biasing can be produced by a permanent magnet, from fringing fields from the reference layer or SAF, or from antiferromagnetic pinning. In another embodiment, the MTJ2 can be operated as a simple magnetic bilayer separated but a tunnel barrier. In that case the reference layer and sense layers are both unpinned, and in zero field are substantially antiparallel to each other due to their mutual magnetic fringing fields. In that case, the sensitivity axis is anywhere in the plane of the layers. In each case, the desired behavior is the achieve a reproducible magnetic configuration with a low corresponding electrical resistance below a low-field threshold, and to achieve another reproducible magnetic threshold with a high corresponding electrical resistance above a high-field threshold.
[0077]
[0078] In one aspect illustrated in
[0079] In some aspects, the first and/or second setting resistance element 33, 34 comprise at least two different types of resistors. For example, the at least two different types of resistors can comprise a combination of a p-type polysilicon resistor and an n-type polysilicon resistor. The first and/or second setting resistance element 33, 34 can be configured to have substantially the same temperature coefficient of resistance (TCR) as the TCR of the first and/or second TMR elements 31, 32. For instance, the first and/or second setting resistance element 33, 34 can be configured to have a TCR of about 600 ppm/ C., corresponding to the TCR of the first and/or second TMR elements 31, 32.
[0080] In some aspects, The first and/or second setting resistance element 33, 34 can be programmed to adjust/set the first and/or second adjustable resistances R.sub.SET1, R.sub.SET2 to a predetermined resistance value that is substantially equal to the TMR resistance R.sub.SNS1, R.sub.SNS2 of the first and/or second TMR elements 31, 32.
[0081] The present disclosure further pertains to a magnetic switch device comprising the magnetic sensing device.
[0082]
[0083] The target can move towards and away from the magnetic sensing device 10 along an axis 61 (arrow A in
[0084] The magnetic switch device 50 can be used to detect proximity of a target 60 to one or more magnetic sensing device 10, where both the target and the magnetic sensing device 10 are capable of motion relative to one another. Example of the magnetic switch device 50 may include a stationary portion to which the magnetic sensing device 10 is attached and a movable portion including a magnet, such as cellular telephones and laptop computers having magnets in moveable door or cover portions. In other examples, the current delta i.sub.SNS from the magnetic sensing device 10 can be used to determine if a pushbutton or other type of switch associated with the target 60 is open or closed.
[0085] Having described exemplary embodiments of the disclosure, it will now become apparent to one of ordinary skill in the art that other embodiments incorporating their concepts may also be used. The embodiments contained herein should not be limited to disclosed embodiments but rather should be limited only by the spirit and scope of the appended claims. All publications and references cited herein are expressly incorporated herein by reference in their entirety.
[0086] Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.
TABLE-US-00001 Reference numbers and symbols 10 magnetic sensing device 110 first branch 120 second branch 2 magnetic tunnel junction 21 reference layer 210 reference magnetization 211 first ferromagnetic reference layer 212 second ferromagnetic reference layer 213 non-magnetic layer 22 tunnel barrier layer 23 sense layer 230 sense magnetization 31 TMR element, first TMR element 310 poly fuse 32 second TMR element 320 resistance segment 33 first setting resistance element 330 trim pad 34 second setting resistance element 40 first power supply rail 50 magnetic switch device 60 target 61 axis h field strength delta i.sub.SNS current delta R.sub.SNS resistance delta d lateral size D distance H.sub.0 field strength reference value i.sub.SET setting current i.sub.SNS10 first reference current value i.sub.SNS1 first current i.sub.SNS2 second current P1 first transistor P2 first cascode transistor P3 third transistor P4 third cascode transistor N1 second transistor N2 second cascode transistor N3 fourth transistor N4 fourth cascode transistor r.sub.cmp equivalent output impedance R.sub.SET1 first adjustable resistance R.sub.SET2 second adjustable resistance R.sub.SNS10 first TMR reference resistance value R.sub.SNS1 first TMR resistance R.sub.SNS20 second TMR reference resistance value R.sub.SNS2 second TMR resistance V.sub.cmp node voltage V.sub.PBIAS1 first bias voltage V.sub.PBIAS2 first cascode bias voltage V.sub.NBIAS1 second bias voltage V.sub.NBIAS2 second cascode bias voltage V.sub.DD bias voltage V.sub.out output voltage