METHOD FOR MANUFACTURING COMPOSITE SUBSTRATE AND COMPOSITE SUBSTRATE

Abstract

A composite substrate capable of improving temperature characteristics while suppressing crack generation and a method for manufacturing such composite substrate is provided. The method for manufacturing composite substrates includes: a step of preparing a piezoelectric material substrate having a rough surface; a step of removing the damaged layer by etching the rough surface of the piezoelectric material substrate using a chemical process; a step of depositing an intervening layer on the rough surface of the piezoelectric material substrate from which the damaged layer has been removed; a step of flattening the surface of the deposited intervening layer; a step of bonding the piezoelectric material substrate to a support substrate having a lower thermal expansion coefficient than the piezoelectric material, with the deposited intervening layer in between; and a step of thinning the piezoelectric material substrate after bonding. Lithium tantalate (LT) or lithium niobate (LN) are suitable as the piezoelectric material.

Claims

1. A method for manufacturing composite substrate comprising: preparing a piezoelectric material substrate having a rough surface; removing the damaged layer by etching the rough surface of the piezoelectric material substrate using a chemical process; depositing an intervening layer on the rough surface of the piezoelectric material substrate from which the damaged layer has been removed; flattening the surface of the deposited intervening layer; bonding the piezoelectric material substrate to a support substrate having a lower thermal expansion coefficient than the piezoelectric material, with the deposited intervening layer in between; and thinning the above after lamination the substrate of piezoelectric material, wherein the piezoelectric material is Lithium tantalate (LT) or lithium niobate (LN).

2. The method for manufacturing composite substrate as claimed in claim 1, wherein chemical etching with solution is performed in the removing the damaged layer.

3. The method for manufacturing composite substrate as claimed in claim 1, wherein dry etching is performed in the removing the damaged layer.

4. The method for manufacturing composite substrate as claimed in claim 1, wherein a surface activation treatment is applied to both or one of the piezoelectric material substrate and the support substrate prior to the bonding.

5. The method for manufacturing composite substrate as claimed in claim 4, wherein the surface activation treatment is any of ozone water treatment, UV ozone treatment, ion beam treatment, and plasma treatment.

6. The method for manufacturing composite substrate as claimed in claim 1, wherein the intervening layer includes any of SiO.sub.2, SiON, SiN, SiC, AlN, Al.sub.2O.sub.3, Y.sub.2O.sub.3, TiO.sub.2, Ta.sub.2O.sub.5, and ZrO.sub.2.

7. The method for manufacturing composite substrate as claimed in claim 1, wherein grinding and/or polishing of the piezoelectric material substrate is performed in the thinning the piezoelectric material substrate.

8. The method for manufacturing composite substrate as claimed in claim 1, wherein ion implantation is applied to the piezoelectric material substrate in advance, and thinning is performed by peeling at the ion implantation interface in the thinning the piezoelectric material substrate after bonding.

9. The method for manufacturing composite substrate as claimed in claim 8, wherein the ions to be implanted contain either H.sup.+ or H.sub.2.sup.+.

10. A composite substrate in which a piezoelectric material substrate and a support substrate whose coefficient of thermal expansion is smaller than that of the piezoelectric material are bonded together with an intervening layer in between, wherein the interface with the intervening layer in the piezoelectric material substrate is a rough surface from which the damage layer has been removed, and the piezoelectric material is Lithium tantalate (LT) or lithium niobate (LN).

11. The composite substrate according to claim 10, wherein the interface with the support substrate in the intervening layer is a flattened surface.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is a graph showing the coefficients of thermal expansion of various materials in contrast.

[0018] FIG. 2 shows the spectrum of reflection coefficient in a resonator fabricated from a conventional composite substrate.

[0019] FIG. 3 shows a result of the thermal shock test for wafers fabricated by a conventional method.

[0020] FIG. 4 shows a cross-sectional TEM image of the near surface of an LT wafer roughened by the lapping process.

[0021] FIG. 5 shows a cross-sectional TEM image of the near surface of an LT wafer after etching.

[0022] FIG. 6 shows the procedure for manufacturing the composite substrate 1.

[0023] FIG. 7 shows the evaluation results of each wafer manufactured in Example 3.

DESCRIPTION OF EMBODIMENTS

[0024] Hereinafter, embodiments of the present invention will be described in detail, but the present invention is not limited thereto.

[0025] To solve the problem, the inventor first conducted a detailed investigation of the defects. The sample used was an LT wafer whose surface was lapped with GC (green silicon carbide) grit with particle size #3000. In cross-sectional observation, although they were not clearly visible with the commonly used surface-observation type SEM (Scanning Electron Microscopy), observation with the transmission type TEM (Transmission Microscopy), which can even observe internal crystal defects, revealed the existence of numerous cracks in the vicinity of the surface. The cross-sectional TEM image is shown in FIG. 4. In the present invention, the cracked layer is removed by chemical etching in the vicinity of this cracked surface by a method that does not use mechanical or physical techniques. This reduces cracking. The cross-sectional TEM image after etching is shown in FIG. 5. Then, by bonding after the chemical etching, the composite wafers can be made thermally shock-resistant.

[0026] The procedure for manufacturing composite substrate 1 using the present invention is described with reference to FIG. 6.

[0027] First, a piezoelectric material substrate 2 with a rough surface (rough surface) 21 is prepared ((a) in FIG. 6). Lithium tantalate (LT) or lithium niobate (LN) are suitable as the piezoelectric material. The rough surface is, for example, a surface whose surface roughness is greater than about 0.03 μm in arithmetic mean roughness Ra. A damaged layer 22 exists in the vicinity of the rough surface 21. The rough surface 21 of the piezoelectric material substrate is then etched using a chemical process to remove the damaged layer 22 ((b) in FIG. 6). The etching may be done as chemical etching with solution (wet etching) or dry etching. Then, an intervening layer 3 is deposited on the rough surface 21 of the piezoelectric material substrate from which the damaged layer has been removed by etching ((c) in FIG. 6). The intervening layer may include any of SiO.sub.2, SiON, SiN, SiC, AlN, Al.sub.2O.sub.3, Y.sub.2O.sub.3,TiO.sub.2, Ta.sub.2O.sub.5, and ZrO.sub.2. It is preferable if the intervening layer 3 is deposited thick enough to fill the unevenness of the rough surface, and it is even more preferable if it is thick enough to provide sufficient polishing allowance. The surface of the deposited intervening layer 3 becomes a rough surface that follows the rough surface 21 of the piezoelectric substrate 2. The surface of the deposited intervening layer 3 is then flattened to make a bonding surface 31 ((d) in FIG. 6). The flattening method is arbitrary, but for example, flattening by polishing is advisable.

[0028] In parallel with preparing the piezoelectric material substrate 2 with the intervening layer 3 as described above, the support substrate 4 is separately prepared ((e) in FIG. 6). The support substrate 4 is a substrate made of a material whose thermal expansion coefficient is smaller than that of the piezoelectric material (LT or LN), for example, Si, sapphire, glass, or quartz is appropriate.

[0029] Then, the prepared piezoelectric material substrate 2 and the support substrate 4 are bonded together, with the intervening layer 3 of the substrate 2 in between ((f) in FIG. 6). Prior to the bonding, it is preferable to apply a surface activation treatment to both or one of the piezoelectric material substrate 2 and the support substrate 4. The surface activation treatment may be ozone water treatment, UV ozone treatment, ion beam treatment, plasma treatment, or a combination of these treatments.

[0030] The piezoelectric material substrate 2 after bonding is then thinned to obtain composite substrate 1 ((g) in FIG. 6). At this time, for example, the piezoelectric material substrate 2 may be thinned by grinding and/or polishing. Alternatively, ion implantation may be applied to the piezoelectric material substrate in advance at any stage prior to bonding, and thinning may be performed by peeling at the ion implantation interface after the bonding.

EXAMPLES

Example 1

[0031] As-sliced (cut from ingot into wafer shape) wafers were prepared and lapped with GC (green silicon carbide) No. 3000 (#3000) abrasive. Then, chemical etching was applied to remove the damaged portions of the surface layer. The solution used for etching was a solution with HF: HNO.sub.3=2:3 as described in the Proceedings of the Japan Society of Applied Physics Spring Meeting 11p-D5-7 (2015). A cross-sectional TEM image after etching shown in FIG. 5 reveals that the micro cracks that existed near the surface have disappeared.

Example 2

[0032] As-sliced (cut from ingot into wafer shape) wafers were prepared and lapped with GC (green silicon carbide) No. 3000 abrasive. Then, dry etching was applied to remove the damaged portions of the surface layer. The dry etching equipment RIE-10NR manufactured by Samco Inc. was used for dry etching, and a mixture of CF.sub.4 and O.sub.2 gas was used as etching gas. Observation of the cross-section after etching revealed that, as in Example 1, the micro cracks that existed near the surface disappeared. This indicates that the removal of the damaged layer can be done by any chemical method.

Example 3

[0033] Various roughing treatments (as-sliced, grinding wheel #1700, grinding wheel #4000, GC #1000 lap, GC #2500 4lap, and GC #4000 lap) were applied to LT wafers. For each roughening level, wafers were produced with the etching of Example 1 for 0, 2, 4, or 6 hours. Then, after each wafer was cleaned, about 6 μm of SiO.sub.2 was deposited by chemical vapor deposition (CVD). The surface was subsequently mirror-finished by polishing the surface by 3 to 4 μm after heat treatment at 300° C. The wafers thus obtained and the silicon wafers that are the support wafers are bonded together after plasma activation. Then, after heat treatment at 120° C., the LT wafer side was ground and polished to thin the LT to 10 μm. Each of the wafers thus obtained was subjected to 300 thermal shock tests from −50 to 135 degrees Celsius. In the thermal shock test, the time maintained at each temperature was 10 minutes. The transition time for each temperature was about 15 seconds. The number of defects was then counted visually from the LT side under a focusing light. Note that cracks that have elongated and reached the surface layer become bright spots under the focusing light, which can be visually evaluated. The evaluation results for each wafer are shown in FIG. 7.

[0034] From this result, it can be seen that etching can reduce crack-induced defects. It can also be seen that the larger the roughness before etching, the longer the etching process time required to remove the defects.

Example 4

[0035] Various roughing treatments (as-sliced, grinding wheel #1500, grinding wheel #4000, GC #1000 lap, GC #3000 lap, and GC #4000 lap) were applied to LT wafers. For each roughening level, wafers were produced with the etching of Example 2 for 0, 10, 20, or 40 minutes. After each wafer was cleaned, about 6 μm of SiO.sub.2 was deposited by chemical vapor deposition (CVD). The surface was subsequently mirror-finished by polishing the surface by 3 to 4 μm after heat treatment at 300° C. The wafers thus obtained and the silicon wafers that are the support wafers are bonded together after plasma activation. Then, after heat treatment at 120° C., the LT wafer side was ground and polished to thin the LT to 10 μm. Each of the wafers thus obtained was subjected to 300 thermal shock tests from −50 to 135 degrees Celsius. In the thermal shock test, the time maintained at each temperature was 10 minutes. The transition time for each temperature was about 15 seconds. The number of defects was then counted visually from the LT side under the focusing light. Note that cracks that have elongated and reached the surface layer become bright spots under the focusing light, which can be visually evaluated. The results are almost the same as in FIG. 7, and it was found that removing the damaged layer by a chemical method can improve the characteristics.

Example 5

[0036] Various roughing treatments (grinding wheel #1500, grinding wheel #4000, GC #1000 lap, GC #3000 lap, and GC #4000 lap) were applied to LT wafers. For each roughening level, wafers were produced with the etching of Example 1 for 0, 2, 4, or 6 hours. After each wafer was cleaned, about 6 μm of any of SiO.sub.2, SiON, SiN, SiC, AlN, Al.sub.2O.sub.3, Y.sub.2O.sub.3, TiO.sub.2, Ta.sub.2O.sub.5, and ZrO.sub.2 were deposited by physical chemical vapor deposition (PVD). The surface was subsequently mirror-finished by polishing the surface by 3 to 4 μm after heat treatment at 300° C. The wafers thus obtained and the silicon wafers that are the support wafers are bonded together after plasma activation. Then, after heat treatment at 120° C., the LT wafer side was ground and polished to thin the LT to 10 μm. Each of the wafers thus obtained was subjected to 300 thermal shock tests from −50 to 135 degrees Celsius. In the thermal shock test, the time maintained at each temperature was 10 minutes. The transition time for each temperature was about 15 seconds. The number of defects was then counted from the LT side under the focusing light. The results were similar to Example 3. The results show that this method was found to be not sensitive to the type and deposition method of intervening layer.

Example 6

[0037] The support wafers were changed to sapphire, glass, and quartz, and wafers were otherwise fabricated and evaluated under the same conditions as in Example 3. In this case, the same tendency as in Example 3 was observed. In other words, etching could reduce crack-induced defects, and the larger the roughness before etching, the longer the etching process time required to remove defects. Thus, this method was found to be not sensitive to the support wafer.

[0038] According to the embodiments and examples described above, it can be seen that the manufacturing method for the present invention can be used to obtain a composite substrate in which crack generation is suppressed and temperature characteristics can be improved.

[0039] The above embodiments and examples are examples only, and any configuration that is substantially the same as the technical concept described in the claims of the present invention and that produces similar effects is included in the technical scope of the present invention.

REFERENCE SIGNS LIST

[0040] 1 Composite substrate

2 Substrate

[0041] 3 Intervening layer
4 Support substrate