Analog-to-digital converter and method for analog-to-digital conversion

Abstract

An analog-to-digital converter is provided which is configured to output an n-bit signal in response to an analog input signal. n is greater than 1. The converter comprises n comparators, where each comparator is configured to output one bit of the n-bit signal and comprising a first input and a second input. A first comparator is configured to receive the analog input signal at its first input and a reference value at its second input and to output the first, most significant bit of the n-bit signal. For the remaining comparators, an i-th comparator, is configured to output an i-th bit, the analog-to-digital converter comprises a respective i-th input device. The i-th input device is configured to selectively provide one of 2.sup.i−1 reference values to one of the first or second input of the i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator, such that the n-bit signal is a Gray code representation of the analog input signal.

Claims

1. An analog-to-digital converter configured to output an n-bit signal in response to an analog input signal, where n is greater than 1, the analog-to-digital converter comprising: n comparators, each comparator configured to output one bit of the n-bit signal and comprising a first input and a second input, wherein a first comparator is configured to receive a reference value at its first input and the analog input signal at its second input and to output the first, most significant bit of the n bit signal, wherein for an i-th comparator, where i=2 . . . n, configured to output an i-th bit, the analog-to-digital converter comprises a respective i-th input device configured to selectively provide one of 2.sup.i−1 reference values to one of the first or second input of the i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator such that the n-bit signal is a Gray code representation of the analog input signal.

2. The analog-to-digital converter of claim 1, wherein each i-th input device, i=2 . . . n, is configured to be controlled by a logic combination of output signals of the first through (i−1)-th comparators.

3. The analog-to-digital converter of claim 2, wherein the i-th input device is configured to switch the providing of the one of 2.sup.i−1 reference values and the analog input signal between the first and second inputs of the i-th comparator based on an XOR combination of the output signals of the first through (i−1)-th comparators.

4. The analog-to-digital converter of claim 3, wherein the input device of the i-th comparator, i=2 . . . n, comprises a switch device, which is configured to couple in a first position the first input of the i-th comparator to a first reference set and the second input of the i-th comparator to the analog input signal and to couple in a second position the second input of the i-th comparator to a second reference set and the first input of the i-th comparator to the analog input signal.

5. The analog-to-digital converter of claim 4, wherein for the i-th comparator, i=2 . . . n, the first reference set is configured to provide one of first 2.sup.i−2 reference values based on a logic combination of the outputs of the first through (i−2)-th comparators and wherein the second reference set is configured to provide one of second 2.sup.i−2 reference values different from the first 2.sup.i−2 reference values based on the logic combination.

6. The analog-to-digital converter of claim 1, wherein for providing one of 2.sup.i−1 reference values the analog-to-digital converter includes a digital-to-analog converter.

7. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter is configured to operate independently from a clock signal.

8. The analog-to-digital converter of claim 1, further comprising a peak detection logic coupled to receive the n-bit signal and to determine a peak value of the n-bit signal over time.

9. The analog-to-digital converter of claim 8, wherein the peak detection logic is configured to operate independently from a clock signal.

10. The analog-to-digital converter of claim 9, wherein the peak detection logic, for each i-th bit, i=1−n, comprises an i-th latch configured to receive the 1-th bit, wherein the peak detection logic is configured such that of the n latches at most one latch, the k-th latch, is switched to transparent providing its input to its output at a given time, wherein the k-th latch is selected from the first to n-th latch with decreasing priority as the latch where for the first to k−1 latches the input corresponds to the output and for the k-th bit the decoded Gray code indicates a higher value of the k-th bit than stored in the k-th latch when the peak detection logic is a maximum peak detection logic, or indicates a lower value of the k-th bit than stored in the k-th latch when the peak detection logic is a minimum peak detection logic.

11. An analog-to-digital conversion method for outputting an n-bit signal in response to an analog input signal, where n is greater than 1, the analog-to-digital conversion method comprising: n comparators (11), each comparator configured to output one bit of the n-bit signal and comprising a first input and a second input, providing a reference value to a first input of a first comparator and the analog input signal to a second input of the first comparator, and obtaining the 1.sup.st, most significant bit of the n bit signal, at the output of the first comparator, and, for each i-th bit, where i=2 . . . n: selectively providing one of 2.sup.i−1 reference values to one of the first or second input of a respective i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator, and obtaining the i-th bit of the n bit signal at the output of the i-th comparator, such that the n-bit signal is a Gray code representation of the analog input signal.

12. The method of claim 11, wherein the selectively providing for the i-th bit is based on a logic combination of output signals of the first through (i−1)-th comparators.

13. The method of claim 12, wherein, for the i-th bit, the selectively providing comprises switching the providing of the one of 2.sup.i−1 reference values and the analog input signal between the first and second inputs of the i-th comparator based on an XOR combination of the output signals of the first through (i−1)-th comparators.

14. The method of claim 13, further comprising compensating delays caused by the XOR combinations.

15. The method of claim 11 further comprising: detecting a peak in the n-bit signal over time.

16. An analog-to-digital converter comprising: a first comparator operative to receive an analog input signal and a first reference value, the first comparator operative to output a first bit value of a multi-bit signal based on a comparison of the analog input signal to the first reference value; a second comparator operative to receive the analog input signal and a second reference value, the second comparator operative to output a second bit value of the multi-bit signal based on a comparison of the analog input signal to the second reference value; and signal path switch circuitry operative to control selection of inputting the analog input signal to a first input or a second input of the second comparator.

17. The analog-to-digital converter as in claim 16, wherein the signal path switch circuitry includes: first switch circuitry operative to control input of the analog input signal to the first input of the second comparator or the second input of the second comparator; and second switch circuitry operative to control input of the second reference value to the first input of the second comparator and input of a third reference value to the second input of the second comparator.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Various embodiments will be described referring to the attached drawings, wherein:

[0017] FIG. 1 is a block diagram of an analog-to-digital converter according to an embodiment,

[0018] FIG. 2 is a block diagram of a stage of an analog-to-digital converter according to an embodiment,

[0019] FIG. 3 is a circuit diagram of an analog-to-digital converter according to an embodiment,

[0020] FIGS. 4A to 4D are diagrams illustrating the operation of analog-to-digital converters according to some embodiments,

[0021] FIG. 5 is a circuit diagram of an analog-to-digital converter according to an embodiment,

[0022] FIG. 6 illustrates a stage of an analog-to-digital converter according to an embodiment,

[0023] FIG. 7 illustrates an example implementation of a comparator usable in some embodiments,

[0024] FIG. 8 illustrates an implementation of a peak detector usable in conjunction with an analog-to-digital converter according to some embodiments, and

[0025] FIG. 9 is a flowchart illustrating a method according to an embodiment.

DETAILED DESCRIPTION

[0026] In the following, various embodiments will be described referring to the attached drawings. These embodiments are to be taken as examples only and are not to be construed as limiting in any way. For example, while embodiments may be described including a plurality of features (components, elements, devices, acts, events, steps or the like), in other embodiments some of these features may be omitted or replaced by alternative features. In addition to the features explicitly shown and described, further features may be provided, for example features used in conventional analog-to-digital converters. Features from different embodiments may be combined to form further embodiments. Variations, modifications or details described with respect to one of the embodiments may also be applied to other embodiments and will therefore not be described repeatedly.

[0027] Connections or couplings described with respect to the figures refer to electrical connections or couplings. Such connections or couplings may be modified, for example by additional intervening elements or by removing elements, as long as the general purpose of the connection or coupling, for example to provide a certain signal, to supply a voltage or a current etc. is essentially maintained.

[0028] In the following, n-bit analog-to-digital converters will be described. For ease of explanation, the most significant bit (MSB) will be referred to as bit 1, followed by the next most significant bit as bit 2, and so on, until bit n, which is the least significant bit. This somewhat differs from the naming convention most frequently used, where the least significant bit is referred to as bit 0, but facilitates explanation of the operation of analog-to-digital converters described herein. As a matter of course, changing the naming convention does not change the function of the analog-to-digital converter per se.

[0029] Turning now to the figures, FIG. 1 is a block diagram illustrating an analog-to-digital converter 10 according to an embodiment. Analog-to-digital converter 10 receives an analog input signal anin and outputs an n-bit signal with bits b1 to bn, wherein n is greater than 1, for example 3 or more. For each bits b1 to bn, a comparator 11 is provided, labeled 11_1 for bit b1, 11_2 for bit b2 . . . until 11_n for bit bn, and collectively referred to as comparators 11.

[0030] Comparator 11_1 receives the analog input signal anin at a positive input thereof and a reference value received from a reference value generation circuit 13 at a negative input thereof. Typically, the reference value for comparator 11_1 will be half of the full scale of signal anin. For example, if anin has a range from 0 to 10 V, the reference value provided to the negative input of comparator 11_1 would be about 5 V.

[0031] Furthermore, each comparator 11_i, i=2 . . . n (in case of n=2 to be understood as only the second comparator 11_2), has a respective input device 12_i assigned thereto. The input device 12_i receives the analog input signal anin and 2.sup.i−1 reference values (for example two reference values for input device 12_2, four reference values for input device 12_3 etc.). The reference values provided to input device 12_i may be set to a value between the reference values provided to the previous input device 12_i−1 (or the reference value provided to comparator 11_1 for i=2), zero and full scale. For example, as for comparator 11_1 the reference value may be half of full scale, for input device 12_2 the reference values are between zero and half of full scale (e.g. 1/4 full scale) and between half of full scale and full scale (e.g. 3/4 full scale). For input device 12_3, the reference values would then be arranged between the reference values of the previous comparators, zero and full scale, for example at 1/8, 3/8, 5/8 and 7/8 of full scale for input device 12_3.

[0032] The respective input device provides the analog input signal anin selectively to either the positive or the negative input of the respective comparator and provides a selected reference value of the assigned 2.sup.i−1 reference values to the other one of the positive or negative input of the i-th comparator. The selections which reference value is provided and to which of the respective inputs of the i-th comparator the selected reference value and the analog input signal anin are provided, are made based on output signals of the comparator for the previous (more significant) bits, i.e. based on the output signals of comparator 11_1 to 11_i−1 for each i-th input device 12_i, as illustrated by corresponding connections in FIG. 1. The selection is performed such that the output signal b1 . . . bn represents the analog input signal as a Gray code. The Gray code is a code in which adjacent code words differ in one bit only, i.e. for example for a continuously increasing input signal anin only one bit changes at a given time. Specific examples for the implementation of input devices to achieve this will be discussed further below.

[0033] FIG. 2 illustrates a stage of an analog-to-digital converter according to an embodiment, which illustrates a possible implementation of input devices 12 including a switch device 20, a first reference set 21 and a second reference set 22. First reference set 21 and second reference set 22 each provide, in case of a comparator 11_i of FIG. 1, one of 2.sup.i−2 reference values (i.e. in case of comparator 11_2 each reference set 21, 22 provides only a single value, for example 1/4 full scale and 3/4 full scale, respectively, as explained above, for comparator 11_3 each reference set 21, 22 selectively provides one of two reference values etc.).

[0034] The reference values of the first and second reference set differ from each other and may be interleaved with each other, such that starting from zero up to full scale the reference values are alternatingly assigned to first reference set 21 or second reference set 22. The selection of the reference value in each reference set, and the selection from which reference set a reference value is used, depends on output signals of previous (higher bit) comparators, as explained with reference to FIG. 1. Switch device 20, in a first switch position, provides analog signal anin to the positive input of comparator 11, and a reference value of first reference set 21 to the negative input of comparator 11. In a second switch position, switch 20 provides a reference value provided by second reference set 22 to the positive input of comparator 11, and the analog input signal anin to the negative input of comparator 11. This selection is again based on outputs from previous, more significant bit comparators, for example based on an exclusive OR combination thereof.

[0035] FIG. 3 illustrates an embodiment of an analog-to-digital converter according to an embodiment, which in the example shown in FIG. 3 is a 4-bit converter with four comparators 11_1 to 11_4.

[0036] Reference values are indicated in FIG. 3 and in the description of FIGS. 3 to 5 below in relation to a full scale of input signal anin, i.e. “1/2” for comparator 11_1, “1/4” and “3/4” for comparator 11_2 etc., meaning 1/2 of full scale, 1/4 of full scale and 3/4 of full scale, respectively. The reference values may for example be provided using a resistive divider from a common reference voltage generator (not shown).

[0037] Comparator 11_1, at a positive input thereof, receives analog input signal anin, and at a negative input thereof receives a reference value “1/2”, i.e. 1/2 of full scale. The output of comparator 11_1 is output as most significant bit, bit 1, of the Gray code, which is 1 if anin exceeds 1/2 full scale and 0 otherwise.

[0038] Comparator 11_2 has a switch device 31_2 assigned thereto, the function of which corresponds to switch device 20 of FIG. 2. In a first position of switch device 31_2, reference value “1/4” is provided to the negative input of comparator 11_2, and analog input signal anin is provided to a positive input of comparator 11_2. In a second position of switch device 31_2, analog input signal anin is provided to the negative input of comparator 11_2, and reference value “3/4” is provided to the positive input of comparator 11_2. In this case, therefore, “1/4” corresponds to first reference set 21, and “3/4” corresponds to the second reference set 22 of FIG. 2.

[0039] Switch devices corresponding to switch device 31_2 are provided to comparators 11_3 and 11_4, as switch devices 31_3 and 31_4, respectively. Switch device 31_3 is controlled via an XOR combination of the output signals of comparators 11_1, 11_2 provided by an XOR gate 30_2, and switch device 31_4 is controlled by an XOR combination of the output signals of comparators 11_1, 11_2, 11_3 provided by XOR gate 30_2 and a further XOR gate 30_3, as shown.

[0040] Furthermore, the reference values provided to switch devices 31_3, 31_4 are selected, i.e. here the first reference set 21 and the second reference set 22 comprise more than one reference value, which are selected. For switch device 31_3, a switch stage 32_3 controlled by the output signal of comparator 11_1 selects, on the one hand, one of reference values “1/8” and “5/8” for providing to switch device 31_3 (first reference set) and on the other hand one of reference values “3/8” and “7/8” (second reference set). For switch device 31_4, two switch stages 32_4a and 32_4b are provided as shown, where stage 32_4a is controlled by the output signal of comparator 11_1, and stage 32_4b is controlled by the output signal of comparator 11_2. A first reference value of a first reference set is therefore selected from “1/16”, “13/16”, “5/16” and “9/16” to be provided to switch device 31_4, and from a second reference set including “3/16”, “15/16”, “7/16” and “11/16” also a second reference value is selected to be provided to switch device 31_4.

[0041] It should be noted that the switch logic of FIG. 3 is merely an example for implementing the respective provision of reference values and analog input signal to the comparators, and other circuits may also be used. For example, in some embodiments, as will be described later referring to FIG. 6, the reference values may be generated by a digital-to-analog converter.

[0042] To further illustrate the operation of embodiments, example signals are shown in FIGS. 4A to 4D, for a 4-bit converter as shown in FIG. 3 (or implemented for n=4 in FIG. 1).

[0043] In FIGS. 4A to 4D, a curve 40 in each of the figures represents an input signal anin for values ranging from zero to a full scale thereof, e.g. rising over time.

[0044] FIG. 4A relates to first comparator 11_1. Here, as indicated by a curve 41, a reference value corresponding to half of full scale (“1/2”) is provided. In FIGS. 4A to 4D, dotted curves or portions of curves indicate that the respective signal is provided to the positive input of the respective comparator, and a dashed curve or portion of a curve indicates that the respective signal is provided to the negative (inverting) input of the respective comparator. In case of first comparator 11_1, the analog input signal anin according to curve 40 is provided to the positive input of comparator 11_1 for the complete range of the input signal, and the reference value according to curve 41 is applied to the negative input throughout. A curve 42 shows the value of bit 1 resulting. As soon as the analog input signal according to curve 40 exceeds the reference value represented by curve 41, bit 1 toggles and goes from low to high, as shown by curve 42.

[0045] FIG. 4B shows corresponding curves for the second comparator 11_2. Curve 40 again represents the analog input signal, and curve 43 represents the reference value applied to comparator 11_2, which in this case may be either “1/4” or “3/4”.

[0046] As shown in FIG. 4B, as soon as the analog input signal represented by curve 40 exceeds the reference value “1/4”, bit 2 represented by a curve 44 toggles and goes from low to high. At the time where bit 1 toggles according to curve 42 (see FIG. 4A, i.e. when the analog input signal exceeds the reference value “1/2”), the inputs of the second comparators are switched, i.e. now the analog input signal according to curve 40 is applied to the negative input of the comparator. Furthermore, the reference value switches from “1/4” to “3/4”, such that now the reference value of “3/4” is applied to the positive input, while previously the reference value of “1/4” was applied to the negative input. This corresponds for example to the operating of switch device 31_2 of FIG. 3 or input device 12_2 of FIG. 1. It should be noted that at this point the output of comparator represented by curve 44 does not toggle, as in both cases the positive comparator input receives a higher input than the negative comparator input.

[0047] This has the consequence that as soon as the analog input signal exceeds the reference value of “3/4”, bit 2 toggles again and goes from high to low, as can be seen by curve 44 in FIG. 4B.

[0048] FIG. 4C shows the situation for comparator 11_3. Here, according to a curve 45 one of four different reference values, “1/8”, “3/8”, “5/8” and “7/8”, are applied. The reference value changes each time bit 1 or bit 2 toggles, corresponding to the operation of switches 32_3 and 31_3 of FIG. 3. Furthermore, also whether the analog input signal according to curve 40 is applied to the positive or negative input changes based on an exclusive OR combination of bits 1 and 2. This results in a bit 3 as represented by a curve 46 in FIG. 4C.

[0049] Finally, FIG. 4D shows the situation for bit 4, where according to curve 47 one of eight reference values is applied, depending on the state and toggling of bits 1, 2 and 3. This results in a bit 4 as illustrated by a curve 48 in FIG. 4D. Bits 1 to 4 represent the analog input signal as a Gray code. As can be seen in FIG. 4D, with rising input signal anin according to curve 40, at each given point in time at most one of bits 1 to 4 toggles, i.e. there is no situation where two bits toggle simultaneously, unlike a conventional bit coding.

[0050] For transitions of the input signal anin, as can be seen in FIG. 4D from curves 42 to 48, the output of the analog-to-digital converter is always valid if the input signal anin changes slowly enough that the corresponding comparator output, all switch positions and all comparator input levels can settle within the time when the input signal crosses any reference value to the time when the input signal crosses the next higher or lower reference value. In case the analog input signal anin changes faster, at least the comparators for the more significant bits (bit 1, bit 2) can follow the input and are always valid. Generally, therefore, an error may be introduced if the input changes faster than the comparators can follow due to the propagation delays.

[0051] The Gray code may be converted to a conventional binary code using a series of exclusive OR gates, as known to a skilled person. Such a binary code may then, if needed for a certain application, be converted again to analog using a conventional digital-to-analog converter like an R/2R digital-to-analog converter. Furthermore, a Gray code digital signal if needed may be converted directly back to analog using a resistive string and a cascade of switches, also in a conventional manner.

[0052] Next, variations and additions to the above embodiments will be described.

[0053] The XOR gates 30_2, 30_3 have a certain propagation delay, for example in case of implementation in CMOS technology of a few nanoseconds, while comparators have a propagation delay in the order of 100 nanoseconds. Therefore, in many implementations the propagation delays of the XOR gate do not adversely affect the operation of the comparators, the effect may be negligible.

[0054] Nevertheless, to mitigate the influence of this delay further, FIG. 5 illustrates an analog-to-digital converter according to a further embodiment, where dummy XOR gates (with one input always zero) 50_1, 50_2, 50_3, 50_4 are added as shown, such that the propagation delays for the control signals for a specific bit (for switch device 31_3 or 31_4, respectively, and switch stages 32_3, 32_4A, 32_4B, respectively) are more similar to each other for a specific bit. For example, for bit 4 all these control signals controlling switches pass two XOR gates. As the delay of XOR gates also depends on the direction the gate switches (from output logic 1 to 0 or vice versa), this may not provide a full delay compensation, but at least a partial delay compensation.

[0055] As mentioned, reference values may be provided for example by a resistive divider, and then may be selected via switches as shown in FIG. 3 or 5. In another embodiment shown in FIG. 6, reference values may be provided via a digital-to-analog converter. FIG. 6 illustrates a corresponding stage, i.e. combination of comparator and input device. The stage of FIG. 6 may be applied to all comparators 11_i, i>2. Here, a switch device 60 is coupled to comparator 11, which selectively provides the analog input signal anin to one of the positive or negative input of comparator 11 and a reference value provided by a digital-to-analog converter 61 to the other one of the positive or negative input. Digital-to-analog converter 61 obtains a digital reference value based on the number of the bit (i) and the outputs of previous comparators by some logic circuit (for example, for bit 2 either a reference value of digital 1/4 or 3/4 full scale) and then outputs a corresponding analog value based on the digital reference value as the reference value.

[0056] As mentioned above referring to FIG. 5, with additional XOR gates delays may be partially compensated. In some embodiments, furthermore comparators which allow increasing the propagation delay and therefore are more tolerant against propagation delays for the switching signals may be used. An example implementation of such a comparator is shown in FIG. 7. The comparator of FIG. 7 includes a positive input (+), a negative input (−), a supply input 70, a current source 71, two transistor stages as shown, an output capacitor 72 and a Schmitt trigger 73, where an output of the comparator is provided at the output of Schmitt trigger 73. The capacitor 72 in combination with a hysteresis of Schmitt trigger 73 filters out glitches caused by delay variations at the inputs of the comparator. The example comparator of FIG. 7 uses a Wilson current mirror in the second stage prior to the Schmitt trigger 73. Compared to widely used cascade current mirrors, this solution consumes less current at high differential voltages at the comparator inputs.

[0057] However, other comparator implementations may also be used.

[0058] The output bits of the analog-to-digital converter may be stored and held for example by a set of latches or registers. Latching or registering Gray code data requires no setup or hold times, as only one bit changes at a time and the stored result represents either the state before the bit change or the state after the bit change, but no other combination corresponding to a completely different level, unlike binary code that must not be stored or latched without applying setup and hold times.

[0059] One example for further processing the resulting Gray code is to detect a maximum value of the output over time. A corresponding embodiment of an asynchronous maximum detector is shown in FIG. 8. “Asynchronous” refers to the fact that the detector requires no clock signal. The maximum detector of FIG. 8 receives the bits of the Gray code, in the example of FIG. 8 four bits bit 1 to bit 4, and outputs corresponding bits bit 1 max to bit 4 max of a maximum value. For each bit, the maximum detector of FIG. 8 includes a respective latch 80, i.e. 80_1 for bit 1, 80_2 for bit 2, 80_3 for bit 3 and 80_4 for bit 4. Each of latches 80 is set to transparent if the input of the respective latch represents a higher analog value than the output and is set back to hold (not transparent) if input and output of the respective latch are equal or if the input represents a lower value than the output. This is ensured by feedbacks from the outputs to a control input of the latch via logic gates. To take values of higher bits into account, switches 81_2, 81_3, 81_4 are used which are controlled via XOR gates 82_3, 82_4 (or directly by bit 1 in case of switch 81_2). While switches 81 are shown in FIG. 8, these may be implemented as digital multiplexers. The shown logic in this way ensures that only one latch can be set to transparent at a given time. Setting a lower value latch to transparent requires that all higher value inputs and outputs are equal.

[0060] In particular, for the latch of the most significant bit 1, latch 80_1, one logic gate is used to switch it to transparent or hold. This series of XOR gates is similar to the generation of the Gray code illustrated in FIG. 3. In other words, for each i-th bit, i=1−n, a respective i-th latch 80_i is configured to receive the i-th bit. The logic shown in FIG. 8 is configured such that of the n latches (n=4 in the example) at most one latch, the k-th latch 80_k, is switched to transparent providing its input to its output at a given time, wherein the k-th latch is selected from the first to n-th latch with decreasing priority as the latch where for the first to k−1 latches 80_1 to 80_k−1 the input corresponds to the output and for the k-th bit the decoded Gray code [0061] indicates a higher value of the k-th bit than stored in the k-th latch when the peak detection logic is a maximum peak detection logic, as shown, or [0062] alternatively indicates a lower value of the k-th bit than stored in the k-th latch when the peak detection logic is a minimum peak detection logic, which is an alternative implementation.

[0063] FIG. 9 is a flowchart illustrating a method according to an embodiment. The method of FIG. 9 may be implemented in the analog-to-digital converters described previously and, in order to avoid repetitions, will be described referring thereto.

[0064] At 90, for a bit 1, the most significant bit, the method comprises providing an analog input signal to a first input (positive input in case of FIG. 1) of a first comparator and a reference value to a second input of the first comparator. At 91, for the remaining bits i=2 . . . n, the method comprises selectively providing a selective reference value to one of the first or second input of the i-th comparator and provide the analog input signal to the other one of the first or second input of the i-th comparator, as described above. Based on this, at 92 the method includes outputting a Gray code at the outputs of the comparators.

[0065] Some embodiments are defined by the following examples.

[0066] Example 1. An analog-to-digital converter configured to output an n-bit signal in response to an analog input signal, where n is greater than 1, comprising: [0067] n comparators, each comparator configured to output one bit of the n-bit signal and comprising a first input and a second input, [0068] wherein a first comparator is configured to receive a reference value at its first input and the analog input signal at its second input and to output the first, most significant bit of the n bit signal, [0069] wherein for an i-th comparator, i=2 . . . n, configured to output an i-th bit, the analog-to-digital converter comprises a respective i-th input device configured to selectively provide one of 2.sup.i−1 reference values to one of the first or second input of the i-th comparator and the analog input signal to the other one of the first or 20 second input of the i-th comparator such that the n-bit signal is a Gray code representation of the analog input signal.

[0070] Example 2. The analog-to-digital converter of example 1, wherein each i-th input device, i=2 . . . n, is configured to be controlled by a logic combination of output signals of the first through (i−1)-th comparators.

[0071] Example 3. The analog-to-digital converter of example 2, wherein the i-th input device is configured to switch the providing of the one of 2.sup.i−1 reference values and the analog input signal between the first and second inputs of the i-th comparator based on an XOR combination of the output signals of the first through -th comparators.

[0072] Example 4. The analog-to-digital converter of example 3, wherein the input device of the i-th comparator, i=2 . . . n, comprises a switch device, which is configured to couple in a first position the first input of the i-th comparator to a first reference set and the second input of the i-th comparator to the analog input signal and to couple in a second position the second input of the i-th comparator to a second reference set and the first input of the i-th comparator to the analog input signal.

[0073] Example 5. The analog-to-digital converter of example 4, wherein for the i-th comparator, i=2 . . . n, the first reference set is configured to provide one of first 2.sup.i−2 reference values based on a logic combination of the outputs of the first through (i−2)-th comparators and wherein the second reference set is configured to provide one of second 2.sup.i−2 reference values different from the first 2.sup.i−2 reference values based on the logic combination. For i=2 this means no logic combination (and therefore always the same reference value), as i-2=0 in this case.

[0074] Example 6. The analog-to-digital converter of any one of examples 3 to 5, further comprising delay compensation elements to mitigate differences in switching times of different stages by compensating delays caused by the XOR combinations.

[0075] Example 7. The analog-to-digital converter of any one of examples 1 to 6, wherein for providing one of 2.sup.i−1 reference values the analog-to-digital converter includes a digital-to-analog converter.

[0076] Example 8. The analog-to-digital converter of any one of examples 1 to 7, wherein the analog-to-digital converter is configured to operate independently from a clock signal.

[0077] Example 9. The analog-to-digital converter of any one of examples 1 to 8, further comprising a peak detection logic coupled to receive the n-bit signal and to determine a peak value of the n-bit signal over time.

[0078] Example 10. The analog-to-digital converter of example 9, wherein the peak detection logic is configured to operate independently from a clock signal.

[0079] Example 11. The analog-to-digital converter of example 9 or 10, wherein the peak detection logic, for each i-th bit, i=1−n, comprises an i-th latch configured to receive the 1-th bit, wherein the peak detection logic is configured such that of the n latches at most one latch, the k-th latch, is switched to transparent providing its input to its output at a given time, wherein the k-th latch is selected from the first to n-th latch with decreasing priority as the latch where for the first to k−1 latches the input corresponds to the output and for the k-th bit the decoded Gray code [0080] indicates a higher value of the k-th bit than stored in the k-th latch when the peak detection logic is a maximum peak detection logic, or [0081] indicates a lower value of the k-th bit than stored in the k-th latch when the peak detection logic is a minimum peak detection logic.

[0082] Example 12. An analog-to-digital conversion method for outputting an n-bit signal in response to an analog input signal, where n is greater than 1, comprising: [0083] n comparators, each comparator configured to output one bit of the n-bit signal and comprising a first input and a second input, [0084] providing a reference value to a first input of a first comparator and the analog input signal to a second input of the first comparator, and obtaining the 1st, most significant bit of the n bit signal, at the output of the first comparator, [0085] and, for each i-th bit, i=2 . . . n: [0086] selectively providing one of 2.sup.i−1 reference values to one of the first or second input of a respective i-th comparator and the analog input signal to the other one of the first or second input of the i-th comparator, and obtaining the i-th bit of the n bit signal at the output of the i-th comparator, such that the n-bit signal is a Gray code representation of the analog input signal.

[0087] Example 13. The method of example 12, wherein the selectively providing for the i-th bit is based on a logic combination of output signals of the first through (i−1)-th comparators.

[0088] Example 14. The method of example 13, wherein, for the i-th bit, the selectively providing comprises switching the providing of the one of 2.sup.i−1 reference values and the analog input signal between the first and second inputs of the i-th comparator based on an XOR combination of the output signals of the first through (i−1)-th comparators.

[0089] Example 15. The method of example 14, further comprising compensating delays caused by the XOR combinations.

[0090] Example 16. The method of any one of examples 12 to 15, further comprises detecting a peak in the n-bit signal over time.

[0091] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.