CONTROL CIRCUIT FOR AN ELECTRONIC CONVERTER, RELATED INTEGRATED CIRCUIT, ELECTRONIC CONVERTER AND METHOD

Abstract

In a control circuit for a switching stage of an electronic converter, a phase detector generates a drive signal in response to a phase difference between first and second clock signals. The first and second clock signals are generated by first and second current-controlled oscillators, respectively. An operational transconductance amplifier generates first and second control currents in response to a difference between a reference and a feedback of the electronic converter, with the first and second currents applied to control the first and second current-controlled oscillators. In response to a switching clock having a first state, a switching circuit applies first and second bias currents to the control inputs of the first and second current-controlled oscillators, respectively. Conversely, in response to the switching clock having a second state, the switching circuit applies the second and first bias currents to the control inputs of the first and second current-controlled oscillators, respectively.

Claims

1. A control circuit for a switching stage of an electronic converter configured to provide an output voltage, the control circuit comprising: a first terminal configured to provide a drive signal to a corresponding electronic switch of said switching stage; a second terminal configured to receive a first feedback signal proportional to said output voltage from a feedback circuit; a driver circuit configured to generate said drive signal as a function of a Pulse-Width Modulation (PWM) signal; and a PWM signal generator circuit configured to generate said PWM signal as a function of said first feedback signal and a reference voltage, wherein said PWM signal generator circuit comprises: a first current-controlled oscillator having an input terminal configured to receive a first current and generate a first clock signal as a function of said first current; a second current-controlled oscillator having an input terminal configured to receive a second current and generate a second clock signal as a function of said second current; a first operational transconductance amplifier configured to provide at a first amplifier output a third current indicative of a difference between said reference voltage and said first feedback signal, wherein said first amplifier output of said first operational transconductance amplifier is connected to said input terminal of said first current-controlled oscillator; and a phase detector having inputs coupled to said first oscillator and said second oscillator and providing at an output said PWM signal; wherein said PWM signal generator circuit further comprises: a first bias current generator configured to provide a first bias current at a first bias output; a second bias current generator configured to provide a second bias current at a second bias output; and a switching circuit configured to receive a switch clock signal and: when a logic level of said switch clock signal has a first logic level, connect the first bias output of said first bias current generator to the input terminal of said first current-controlled oscillator and connect the second bias output of said second bias current generator to the input terminal of said second current-controlled oscillator, and when the logic level of said switch clock signal has a second logic level, connect the first bias output of said first bias current generator to the input terminal of said second current-controlled oscillator and connect the second bias output of said second bias current generator to the input terminal of said first current-controlled oscillator.

2. The control circuit according to claim 1, wherein said switch clock signal is derived from said first clock signal or said second clock signal.

3. The control circuit according to claim 2, wherein said switch clock signal corresponds to one of said first clock signal or said second clock signal.

4. The control circuit according to claim 1, wherein said PWM signal generator circuit further comprises: a first delay line connected between said first current-controlled oscillator and said phase detector, and a second delay line connected between said second current-controlled oscillator and said phase detector.

5. The control circuit according to claim 4, wherein one or more of said first delay line and second delay line is driven as a function of the difference between said reference voltage and said first feedback signal.

6. The control circuit according to claim 4, comprising a terminal configured to receive from an analog differentiator a second feedback signal proportional to a derivative of said output voltage, and wherein one or more of said first delay line and second delay line is driven as a function of the difference between said reference voltage and said second feedback signal.

7. The control circuit according to claim 6, comprising at least one of: said one or more electronic switches of said switching stage; said feedback circuit; and said analog differentiator.

8. The control circuit according to claim 6, wherein each of said first delay line and said second delay line is a current-controlled delay line, and wherein said PWM signal generator circuit further comprises: a second operational transconductance amplifier configured to generate a fourth current indicative of a difference between said reference voltage and said first feedback signal; a third operational transconductance amplifier configured to generate a fifth current indicative of a difference between said reference voltage and said second feedback signal; wherein said fourth current and said fifth current are provided to one or more of the first delay line and the second delay line.

9. The control circuit according to claim 1, wherein said first operational transconductance amplifier is a differential operational transconductance amplifier configured to provide at a second amplifier output a sixth current, wherein a difference between said sixth current and said third current is proportional to a difference between a reference voltage and said first feedback signal, and wherein said second amplifier output of said first operational transconductance amplifier is connected to said input terminal of said second current-controlled oscillator.

10. The control circuit according to claim 1, wherein said electronic converter is a buck or boost converter.

11. The control circuit according to claim 1, where a frequency of the switch clock signal is outside a bandwidth of a control loop for the control circuit.

12. An integrated circuit comprising a control circuit according to claim 1.

13. An electronic converter, comprising: a switching stage, and a control circuit according to claim 1.

14. A control circuit for a switching stage of an electronic converter configured to generate an output voltage, comprising: a feedback circuit configured to generate a feedback signal from said output voltage; an operational transconductance amplifier configured to generate, in response to a difference between a reference voltage and said feedback signal, a first output current and a second output current; a first current-controlled oscillator having an input coupled to receive the first output current and configured to generate a first clock signal; a second current-controlled oscillator having an input coupled to receive the second output current and configured to generate a second clock signal; a phase detector circuit configured to generate a drive signal for the switching stage of the electronic converter in response to a phase difference between the first and second clock signals; a first bias current generator configured to generate a first bias current; a second bias current generator configured to generate a second bias current; and a switching circuit controlled by a switch clock signal to: when the switch clock signal has a first logic level, apply the first bias current to the input of said first current-controlled oscillator and apply the second bias current to the input of the said second current-controlled oscillator, and when the switch clock signal has a second logic level, apply the second bias current to the input of said first current-controlled oscillator and apply the first bias current to the input of the said second current-controlled oscillator.

15. The control circuit according to claim 14, wherein a frequency of the switch clock signal is outside a bandwidth of a control loop for the control circuit.

16. The control circuit according to claim 14, wherein said switch clock signal is derived from said first clock signal.

17. The control circuit according to claim 14, wherein said switch clock signal is derived from said second clock signal.

18. The control circuit according to claim 14, wherein said switch clock signal corresponds to said first clock signal.

19. The control circuit according to claim 14, wherein said switch clock signal corresponds to said second clock signal.

20. The control circuit according to claim 14, wherein said electronic converter is a buck or boost converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The embodiments of the present disclosure will now be described with reference to the annexed plates of drawings, which are provided purely to way of non-limiting example and in which:

[0048] The features and advantages of the present invention will become apparent from the following detailed description of practical embodiments thereof, shown by way of non-limiting example in the accompanying drawings, in which:

[0049] FIG. 1 shows an example of an electronic converter;

[0050] FIG. 2 shows an example of a buck converter;

[0051] FIG. 3 shows exemplary waveforms of the buck converter of FIG. 2;

[0052] FIG. 4A shows waveforms when the buck converter of FIG. 2 is operated in a CCM mode;

[0053] FIG. 4B shows waveforms when the buck converter of FIG. 2 is operated in a DCM mode;

[0054] FIG. 5 shows an example of a boost converter;

[0055] FIG. 6 shows an example of an electronic converter using a PWM signal;

[0056] FIG. 7 shows an example of PWM signal of the electronic converter of FIG. 6;

[0057] FIG. 8 shows a first example of a time-based control circuit for the electronic converter of FIG. 6;

[0058] FIG. 9 shows exemplary waveforms of the control circuit of FIG. 8;

[0059] FIG. 10 shows a second example of a time-based control circuit for the electronic converter of FIG. 6;

[0060] FIG. 11 shows exemplary waveforms of the control circuit of FIG. 10;

[0061] FIG. 12 shows a possible implementation of the time-based control circuit of FIG. 10;

[0062] FIG. 13 shows an embodiment of a modified time-based control circuit; and

[0063] FIG. 14 shows an embodiment of a switching circuit used in the time-based control circuit of FIG. 13.

DETAILED DESCRIPTION

[0064] In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.

[0065] Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0066] The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

[0067] In FIGS. 8 to 14 described below, parts, elements or components that have already been described with reference to FIGS. 1 to 7 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description.

[0068] As explained in the foregoing, various embodiments of the present disclosure relate to an improved time-based control circuit 22a for an electronic converter. For a general description of electronic converters using a PWM signal reference can be made to the previous description of FIGS. 1 to 7. Conversely, for a general description of time-based PID regulators, reference can be made to the previously cited United States Patent Application Publication No. 2021/0226531 A1 (incorporated by reference).

[0069] For example, FIG. 8 schematically shows an example of a time-based control circuit 22a, e.g., in the form of an integrated circuit. Specifically, also in this case, the control circuit 22a comprises: a PWM signal generator 220a configured to generate a PWM signal DRV as a function of a feedback signal FB indicative of the output voltage V.sub.out generated by the switching stage (SS) 26 of the electronic converter and a reference voltage V.sub.REF; and a driver circuit 222 configured to drive a switching stage 26 as a function of the PWM signal DRV.

[0070] Specifically, in the embodiment considered, the PWM signal generator 220a comprises: a first voltage-controlled oscillator 2220 configured to generate a first clock signal CLK1 as a function of the feedback signal FB; an analog differentiator 2222 configured to generate a signal indicative of (and preferably proportional to) the derivative of the feedback signal FB, e.g., implemented with a capacitor C.sub.D and a resistor R.sub.D connected in series between the feedback signal FB and a reference voltage, e.g., ground (which may correspond e.g., to the negative input terminal 200b or the negative output terminal 202b), wherein the intermediate node between the capacitor C.sub.D and the resistor R.sub.D corresponds to the signal indicative of the derivative of the feedback signal FB; a first delay line 2224 having a delay as a function of the feedback signal FB and a second delay line 2226 having a delay as a function of the signal indicative of the derivative of the feedback signal FB, wherein the first and second delay lines are connected in cascade and generate a delayed first clock signal CLK1′; a second voltage-controlled oscillator 2228 configured to generate a second clock signal CLK2 as a function of the reference voltage V.sub.REF; and a phase detector (PD) circuit 2230 configured to generate the PWM signal DRV, wherein the duty cycle of the PWM signal DRV is determined as a function of the phase difference Φ between the clock signal CLK2 and the delayed clock signal CLK1′.

[0071] Delay lines having a programmable delay as a function of a voltage or current signal are well known in the art. For example, in this context may be cited U.S. Pat. Nos. 5,650,739 A and 7,696,799 B2 (incorporated by reference).

[0072] For example, as shown in FIG. 9, the phase detector circuit 2230 may be configured to set the signal DRV to high when the second clock signal CLK2 is high and the delayed first clock signal CLK1′ is low. For example, the phase detector 2230 may be implemented with one or more logic gates and/or one or more latches.

[0073] In the embodiment considered, the second voltage-controlled oscillator 2228 provides thus a clock signal CLK2 having a given (fixed or settable) frequency as a function of the reference voltage V.sub.REF. Conversely, the first voltage-controlled oscillator 2220 varies the frequency of the first clock signal CLK1 until the feedback signal FB corresponds to the reference voltage V.sub.REF, and in this steady condition the frequency of the first clock signal CLK1 corresponds to the frequency of the second clock signal CLK2, but the clock signals are phase shifted by a given phase Φ.sub.I. The first oscillator 2220 thus implements a regulator with I (integral) component of the phase Φ.sub.I. Conversely, the first delay line 2224 and the second delay line 2226 introduce an additional phase Φ.sub.P being proportional to the feedback signal FB and an additional phase Φ.sub.D being proportional to the derivative of the feedback signal FB, i.e., the total phase shift Φ corresponds to: Φ=Φ.sub.I+Φ.sub.P+Φ.sub.D; wherein, as shown in FIG. 9, the phase shift Φ is proportional to (and preferably corresponds to) the switch on duration T.sub.ON (e.g., T.sub.ON=T.sub.SW(Φ/2π), i.e., the signal DRV is a PWM signal wherein the switch-on duration T.sub.ON/the duty cycle is varied via a time-based control (with PID regulation) of the phase shift Φ as a function of the feedback signal FB and the reference voltage V.sub.REF. Accordingly, the phase detector 2230 may also perform other operations, such as a down-scaling operation of the frequency of the clock signals CLK1/CLK2, and it is only relevant that the phase detector 2230 is configured to generate a PWM signal DRV, wherein the switch-on duration T.sub.ON of the signal DRV is determined as a function of the phase shift Φ.

[0074] FIG. 10 shows a second example of a time-based PWM signal generator 220a.

[0075] Specifically, in the embodiment considered, the following modifications have been performed, which also may be used separately: the voltage-controlled oscillators 2220 and/or delay lines 2224 and 2226 have been replaced with current-controlled oscillators and/or delay lines; the delay lines 2224 and 2226 have been combined into the same delay line 2234; and a differential approach is used, wherein the oscillators 2220/2228 and/or the delay lines 2234/2235 are driven with differential signal.

[0076] Specifically, in the embodiment considered, again a feedback circuit 24 is used to determine a feedback signal FB proportional to the output voltage V.sub.out. For example, in various embodiments, the feedback circuit 24 is implemented with a voltage divider 24 comprising two or more resistors R.sub.FB1 and R.sub.FB2 connected in series between the terminals 202a and 202b, wherein the voltage V.sub.FB at one of the resistors, e.g., resistor R.sub.FB2, corresponds to the feedback signal FB.

[0077] In the embodiment considered, the feedback signal FB and the reference voltage V.sub.REF are provided to a first differential transconductor 2236, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2236 provides: a first current i.sub.I+=i.sub.I0+i.sub.I/2; and a second current i.sub.I−=i.sub.I0−i.sub.I/2.

[0078] Specifically, in a differential transconductor 2236 the difference i.sub.I=i.sub.I+−i.sub.I− between the currents and is proportional to the difference between the respective input voltages, i.e., the reference voltage V.sub.REF and the feedback voltage V.sub.FB, i.e., i.sub.I=G.sub.MI(V.sub.REF−V.sub.FB).

[0079] In the embodiment considered, the current i.sub.I+ is provided to the current-controlled oscillator 2228 and the current i.sub.I− is provided to the current-controlled oscillator 2220, such as two ring-oscillators. Accordingly, the oscillator 2228 generates a clock signal CLK2 having a frequency proportional to the current and the oscillator 2220 generates a clock signal CLK1 having a frequency proportional to the current i.sub.I−. Thus, when the feedback voltage V.sub.FB corresponds to the reference voltage V.sub.REF, both oscillators are supplied with the current i.sub.I0, which thus determines the steady state frequency of the clock signals CLK1 and CLK2.

[0080] Similarly, the feedback signal FB and the reference voltage V.sub.REF are provided to a second differential transconductor 2238, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2238 provides: a first current i.sub.P+=i.sub.P0+i.sub.P/2; and a second current i.sub.P−=i.sub.P0−i.sub.P/2.

[0081] Specifically, in the differential transconductor 2238 the difference i.sub.P=i.sub.P+−i.sub.P− between the currents i.sub.P+ and i.sub.P− is proportional to the difference between the respective input voltages, i.e., the reference voltage V.sub.REF and the feedback voltage V.sub.FB, i.e., i.sub.P=G.sub.MP(V.sub.REF−V.sub.FB).

[0082] In the embodiment considered, again an analog differentiator 2222 is used to generate a signal V.sub.D proportional to the derivative of the output voltage V.sub.out. For example, in the embodiment considered, the analog differentiator 2222 is implemented with a capacitor C.sub.D and a resistor R.sub.D connected between the output voltage V.sub.out or the feedback signal FB, and a reference voltage, such as ground or preferably the reference voltage V.sub.REF. For example, when connecting the resistor R.sub.D to the reference voltage V.sub.REF the derivative signal V.sub.D has an offset of V.sub.REF to which the derivative component of the output voltage V.sub.out is added.

[0083] In the embodiment considered, the derivative signal V.sub.D, e.g., the voltage at the intermediate node between the capacitor C.sub.D and the resistor R.sub.D, and the reference voltage V.sub.REF are provided to a third differential transconductor 2240, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2240 provides: a first current i.sub.D+=i.sub.D0+i.sub.D/2; and a second current i.sub.D−=i.sub.D0−i.sub.D/2.

[0084] Specifically, in the differential transconductor 2240 the difference i.sub.D=i.sub.D+−i.sub.D− between the currents i.sub.D+ and i.sub.D− is proportional to the difference between the respective input voltages, i.e., the reference voltage V.sub.REF and the derivative signal V.sub.D, i.e., i.sub.P=G.sub.MD(V.sub.REF−V.sub.D).

[0085] Similar to the description of FIG. 8, the currents i.sub.P+ and i.sub.D+ and/or the currents i.sub.P− and i.sub.D−, i.sub.D− may be provided to respective delay lines, such as: two delay lines connected in series (essentially corresponding to the delay lines 2224 and 2226) may be configured to generate a delayed version CLK1′ of the clock signal CLK1 as a function of the currents i.sub.P− and i.sub.D−, respectively; and/or two delay lines connected in series may be configured to generate a delayed version CLK2′ of the clock signal CLK2 as a function of the currents i.sub.P+ and i.sub.D+.

[0086] Generally, the term “and/or” highlights the possibility that these delay lines may be provided for each clock signal (as shown in FIG. 10 for a differential approach) or only for a single clock signal (as shown in FIG. 8).

[0087] Conversely, in the embodiment considered, the currents i.sub.P+ and i.sub.D+ are provided to a first summation node, which thus provides a current I.sub.R=i.sub.P++i.sub.D+, and/or the currents i.sub.P− and i.sub.D− are provided to a second summation node, which thus provides a current I.sub.F=i.sub.P−+i.sub.D−. In the embodiment considered, the current I.sub.R is provided to the delay line 2235 and/or the current I.sub.F is provided to the delay line 2234, such as a sequence of delay stages having a delay as a function of a respective supply current, i.e., the currents I.sub.F and I.sub.R.

[0088] Accordingly, in the embodiment considered and as also shown in FIG. 11, the delay stage 2235 generates a delayed clock signal CLK2′ having a delay t.sub.d2 with respect to the clock signal CLK2 and/or the delay stage 2234 generates a delayed clock signal CLK1′ having a delay tai with respect to the clock signal CLK1.

[0089] In the embodiment considered, the delayed clock signals CLK2′ and CLK1′ are then provided to a phase detector, which e.g., is configured to: set the signal DRV to a first logic level (e.g., high) at the rising edge of CLK2′; and set the signal DRV to a second logic level (e.g., low) at the rising edge of the signal CLK1′.

[0090] Thus, in the embodiment considered, in steady state, the feedback signal V.sub.FB corresponds to the reference voltage V.sub.REF, and by connecting the analog differentiator to the reference voltage V.sub.REF, also the signal V.sub.D corresponds to the reference voltage V.sub.REF. Thus, in the steady state, the differential currents i.sub.D, i.sub.P and i.sub.I are zero, and (when using a differential approach) the delay t.sub.d1 of the delay line 2234 corresponds to the delay t.sub.d2 of the delay line 2235. Moreover, the oscillators 2220 and 2228 provide two clock signals CLK1 and CLK2 having the same frequency and a phase-shift Φ.sub.I. Due to the fact, that the delay lines 2234 and 2235 introduce the same delay t.sub.d1=t.sub.d2 in the embodiment considered, the phase shift Φ between the delayed clock signals CLK1′ and CLK2′ corresponds to Φ.sub.I, e.g., the duration T.sub.ON corresponds to (or is proportional to) the delay Φ.sub.I, e.g., T.sub.ON=T.sub.SW(Φ.sub.I/2π). Accordingly, the duty cycle D=T.sub.ON/T.sub.SW of the signal DRV corresponds thus to Φ.sub.I/2π. For example, in a buck converter, the duty cycle may be determined (approximately) as a function of the input and output voltage, i.e., D=Φ.sub.I/2π=V.sub.out/V.sub.in.

[0091] As mentioned before, also only one of the delay lines 2234 or 2235 could be used or one of the delay lines could introduce a constant delay, i.e., one of the delays t.sub.d1 to or t.sub.d2 could be zero or at least constant. In fact, in this case, the oscillators 2220 and 2228 would generate clock signals having a phase shift Φ.sub.I which also compensate the constant delay t.sub.d1 or t.sub.d2. Thus, in general, in various embodiments, one or more first delay lines 2234 are connected between the oscillator 2220 and the phase detector 2230 and/or one or more second delay lines 2235 are connected between the oscillator 2228 and the phase detector 2230, wherein the one or more first delay lines 2234 and/or the one or more second delay lines 2235 are driven via the currents i.sub.P and i.sub.D.

[0092] As mentioned before, in various embodiments, the feedback signal FB and the reference voltage V.sub.REF are provided to a first differential transconductor 2236, such as a differential operational transconductance amplifier (OTA). For example, in various embodiments, the differential transconductor 2236 provides: a first current i.sub.I+=i.sub.I0+i.sub.I/2; and a second current i.sub.I−=i.sub.I0−i.sub.I/2.

[0093] FIG. 12 shows in this respect an embodiment for implementing the above biasing of the current i.sub.I0.

[0094] Specifically, in the embodiment considered, the differential transconductor 2236 just provides the differential component i.sub.I, i.e.: a first (positive) terminal of the differential transconductor 2236 provides a first current i.sub.I/2, wherein the first terminal is connected to the current controlled oscillator 2228; and a second (negative) terminal of the differential transconductor 2236 provides a first current −i.sub.I/2, wherein the first terminal is connected to the current controlled oscillator 2220.

[0095] In the embodiment considered, a first current source 2250 providing a current I.sub.BIAS+=i.sub.I0 is thus connected to the first terminal of the differential transconductor 2236, whereby the current controlled oscillator 2228 receives a current i.sub.I+=i.sub.I0+i.sub.I/2. Similarly, a second current source 2252 providing a current I.sub.BIAS−=i.sub.I0 is connected to the second terminal of the differential transconductor 2236, whereby the current controlled oscillator 2220 receives a current i.sub.I−=i.sub.I0−i.sub.I/2.

[0096] Generally, the differential transconductor 2236 may also provide a common mode current, which thus would also be added to the currents provided to the current controlled oscillators 2220 and 2228. However, without loss of generality, this common mode current is usually small and will be neglected in the following. Accordingly, neglecting the common mode current provided by the differential transconductor 2236, the current controlled oscillators 2220 and 2228 are equally biased with a common-mode current I.sub.BIAS+=I.sub.BIAS−, so that in steady state (i.e., when the loop is closed, FB=V.sub.REF) the differential current i.sub.I provided by the differential transconductor 2236 is zero, i.e., the current controlled oscillators 2220 and 2228 oscillate with the same frequency F.sub.SW. Accordingly, the frequency F.sub.SW is nominally constant across the entire input and output voltage range and only determined by the bias currents I.sub.BIAS+ and I.sub.BIAS− (and the actual common mode current of the differential transconductor 2236). This applies also in case of the single ended configuration, when the differential amplifier 2236 just provides a current I.sub.I to one of the current controlled oscillators 2220 or 2228.

[0097] Conversely, focusing on the delay-lines 2234 and 2235, in steady-state the (differential) currents i.sub.D and i.sub.P provided by the (differential) transconductors 2238 and 2240 are zero. Supposing the delay lines are matched, they both introduce the same delay t.sub.d1=t.sub.d2 and therefore the same phase-shift.

[0098] In this respect, in steady state, the regulator circuit should generate a PWM signal DRV, which ensures that the electronic converter generates the requested output voltage V.sub.out. As mentioned before, in this case, the two oscillators 2220 and 2228 provide two clock signals CLK1 and CLK2 with the same frequency F.sub.SW and the phase-shift Φ is related to the converter duty-cycle D.sub.PWM, e.g., in case of a buck and without considering efficiency:

D.sub.PWM=T.sub.ON/(T.sub.ON+T.sub.OFF))=Φ/2π=V.sub.out/V.sub.in

[0099] Again, it is important to note that the phase-shift Φ is dictated by the integral Φ.sub.I action only, while the proportional Φ.sub.P and derivative Φ.sub.P actions have effects just during transients.

[0100] However, it will be noted that, in the steady state condition, the output voltage V.sub.out may be subject to an offset.

[0101] On the one hand, as mentioned before, typically a resistive voltage divider R.sub.FB1 and R.sub.FB2 is used to generate the feedback signal FB, which is provided to the transconductor 2236 (and similarly the transconductor 2238). Such a voltage divider may thus introduce an offset due to an unexpected divider ratio. However, thanks to the integral action, the regulator circuit varies the currents I.sub.I− and I.sub.I+ until the feedback signal FB corresponds to the reference voltage V.sub.REF. Accordingly, a mismatch between the resistors R.sub.FB1 and R.sub.FB2, translates into an offset error of the regulated output voltage V.sub.out. Similar issues may also exist with other feedback circuits 24, such as level-shifters. Such a feedback mismatch is well-known in the context of PID regulators, and is not limited to time-based controllers. Although integrated resistors may be matched very well, trimming actions on the feedback divider 24 or other calibration methods may be exploited to minimize the residual output voltage offset.

[0102] On the other hand, in time-based controllers, another major source of an offset of the output voltage V.sub.out are possible unequal common-mode currents of the current-controlled oscillators 2220 and 2228. For example, when the bias currents I.sub.BIAS+ and I.sub.BIAS− are not equal, the control loop has to take care of such an unbalanced bias of the current-controlled oscillators 2220 and 2228. Substantially, in this case, the control loop has to provide, even in the steady state, a current I.sub.I being different from zero, thereby imposing again currents I.sub.I+=I.sub.I− on the current-controlled oscillators, whereby an undesired offset is introduced in the output voltage V.sub.out.

[0103] Similar issues do not apply to the delay lines (for the proportional and derivative regulation), because even though the delays t.sub.d1 and t.sub.d2 may not be equal (e.g., due to an unequal common mode current), such an effect is compensated by the integral regulation and therefore does not contribute to the output offset.

[0104] In this respect, the offset introduced via such unmatched bias currents may also be rather significant. Accordingly, in order to reduce such a voltage offset, the bias current sources 2250 and 2252 should be matched.

[0105] For example, in various embodiments, the current sources 2250 and 2252 may be implemented via two output stages of the same current mirror, wherein the two output transistors of the current mirror are matched transistors. However, also in this case, the currents I.sub.BIAS+ and I.sub.BIAS− may not be perfectly matched and, e.g., a trimming or calibration operation of the currents I.sub.BIAS+ and I.sub.BIAS− may be required.

[0106] However, unfortunately, the nominal operating frequency F.sub.SW of such a time-based regulator circuit should often be settable, e.g., programmable, which thus implies that also the current sources 2250 and 2252 should provide settable currents I.sub.BIAS+ and I.sub.BIAS−. For example, in various embodiments, the current generators 2250 and 2252 may be variable current generators, wherein the values of the currents I.sub.BIAS+ and I.sub.BIAS− are settable/programmable, e.g., as a function of a digital or analog control signal. For example, in the context of a current mirror with two output transistors, the current fed to the input stage of the current mirror may be settable.

[0107] Such a programming may be required, e.g., due to changing operating conditions, and may often be performed also dynamically (i.e., on-the-fly, in real-time). This translates into an output regulation offset that usually changes with the operating frequency F.sub.SW.

[0108] Moreover, the current offset between the current sources 2250 and 2252 is usually process-voltage-temperature (PVT) dependent. Accordingly, a robust solution is required in order to avoid this uncontrolled output offset over various operating conditions of the regulator circuit 220a.

[0109] In this respect, simply performing a trimming action to compensate such offset may thus be practically impossible, especially in case of multiple applicative scenarios as discussed above. Moreover, trimming solutions are, by definition, time consuming and add extra cost for the final test. Finally, a trimming solution usually is not robust and reliable, because it is an open-loop solution that does not take into account temperature variations, aging and all the other possible phenomena that may occur after the final testing (e.g., packaging and assembly, soldering, etc.). In addition, the discrete and finite nature of a trimming action usually does not permit to reach a zero residual error.

[0110] FIG. 13 shows an embodiment of a different solution.

[0111] As mentioned before, a mismatch between the current I.sub.BIAS+ and I.sub.BIAS− usually cannot be avoided, in particular over all operation condition.

[0112] In the embodiment considered, the regulator circuit 220a is configured to perform an averaging operation of the bias currents provided to the current controlled oscillators 2220 and 2228. Specifically, for this purpose is used a time-based averaging operation, wherein over a given time period the current I.sub.BIAS+ is provided for 50% to the current-controlled oscillator 2220 and for 50% to the current-controlled oscillator 2228. Similarly, the current I.sub.BIAS− is provided for 50% to the current-controlled oscillator 2228 and for 50% to the current-controlled oscillator 2220.

[0113] For example, this is schematically shown in FIG. 13, wherein the current generators 2250 and 2252 are connected via a switching circuit 2254, such as a butterfly switching circuit, to the output terminals of the differential transconductor 2236, i.e., the input terminals of the current-controlled oscillators 2220 and 2228.

[0114] Accordingly, as schematically shown in FIG. 14, such a switching circuit 2254 comprises four terminals, wherein: a terminal N1 is connected to the positive output terminal of the transconductor 2236/the current-controlled oscillator 2228; a terminal N2 is connected to the negative output terminal of the transconductor 2236/the current-controlled oscillator 2220; a terminal N3 is connected to the current generator 2250; and a terminal N4 is connected to the current generator 2252.

[0115] Moreover, the switching circuit 2254 is configured to: in a first switching condition, connect the terminal N1 to the terminal N4, i.e., the current generator 2252 to the oscillator 2228, and the terminal N2 to the terminal N3, i.e., the current generator 2250 to the oscillator 2220; and in a second switching condition, connect the terminal N1 to the terminal N3, i.e., the current generator 2250 to the oscillator 2228, and the terminal N2 to the terminal N4, i.e., the current generator 2252 to the oscillator 2220.

[0116] For example, as schematically shown in FIG. 14, the switching circuit 2254 may comprise for this purpose two deviator switches SW1 and SW2. For example, a deviator switch be implemented with two electronic switches, such as FET.

[0117] As mentioned before, the switching between these two switching conditions should be performed based on the logic level of a PWM signal having a 50% duty cycle, such as a clock signal CLK.

[0118] In an embodiment of the implementation, averaging may be performed with a frequency, which remains outside of the bandwidth of the control loop, i.e., so that the averaging process should not influence the control-loop. It will be noted that the clock signal CLK should not be too high, in order to allow the currents provided to the oscillators 2220 and 2228 to correctly settle within half of the clocking period (at least).

[0119] In an example embodiment, the clock signal CLK may correspond to one of the clock signals already used within the regulator circuit 220a, such as the clock signal CLK1 or the clock signal CLK2 generated by the oscillators 2220 and 2228, respectively. In this respect, the selection of the clock signal CLK1 or the clock signal CLK2 is rather irrelevant, because in steady state, both clock signals should have the same frequency. Generally, the clock signal CLK may also correspond to a down-scaled version of the clock signal CLK1 or CLK2, i.e., the clock signal CLK may be generated via a frequency divider receiving at input the clock signal CLK1 or CLK2, whereby the period of the clock signal CLK is a multiple of the period of the clock signal CLK1 or CLK2.

[0120] On the one hand, this avoids the need of an additional clock generator. On the other hand, this ensures that the averaging action is automatically performed according to the converter switching frequency F.sub.SW, which is usually also higher than the loop bandwidth. In this way, if the DC-DC converter supports different switching frequencies F.sub.SW (i.e., different common-mode bias currents I.sub.BIAS+ and I.sub.BIAS− feeding the oscillators 2220 and 2228), there is no need to recalibrate/retune the averaging action, because it remains automatically aligned with the DC-DC switching frequency F.sub.SW.

[0121] Accordingly, the proposed solutions allow to avoid mismatches and non-idealities of the common-mode current generators 2250 and 2252, thus ensuring in steady state average values of the current I.sub.I− and I.sub.I+, which correspond, i.e., AVG(I.sub.I−)=AVG(I.sub.I+). As a consequence, the negative feedback loop does not need to provide any balancing action and therefore the (differential) current I.sub.I provided by the transconductor 2236 remains zero in steady state (i.e., I.sub.I=0). This also implies that no offset is produced in the output voltage V.sub.out due to this mismatch.

[0122] In various embodiments, the proposed solution is auto consistent and automatically performs the averaging action ensuring that, steadily, the output offset is zeroed. Being the solution based on an averaging operation, the output offset is cancelled irrespective of any PVT variation, aging, components derating or any other phenomena that may happen after the final test and packaging/assembly. Accordingly, the solution is robust with respect to the operating conditions, in particular the switching frequency F.sub.SW, the input and output voltages V.sub.in and V.sub.out, and the values of the inductance(s) L.sub.26 and capacitance(s) C.sub.26 of the switching stage 26, and loop compensation choices, in particular the gain G.sub.mI of the transconductor 2236.

[0123] It will be noted that the proposed solution has practically a zero impact on the quiescent current consumption (nor efficiency and neither power consumption). In fact, in various embodiments, the solution requires only the actuation of a butterfly switch 2254, without the need of any other complex analog or digital circuits. Moreover, in various embodiments, also no separated clock signal CLK has to be generated. Accordingly, in terms of system complexity and area, basically there are no substantial difference with respect to an implementation without the proposed solution.

[0124] It will also be noted that the proposed solution not only improves the static performances of the converter, but also the dynamic performances. In fact, without a matching of the bias currents, the transconductor 2236 would remain unbalanced in steady state. Accordingly, the transconductor 2236 would be forced to operate in a bias condition that inherently exacerbates its non-linearity and emphasizes its non-idealities. Non-linearities within the loop negatively affect the whole DC-DC transient response and should be always minimized. Conversely, with the proposed averaging solution, the unbalancing of the transconductor 2236 due to different common-mode bias currents I.sub.BIAS+ and I.sub.BIAS− for the oscillators 2220 and 2228 is mitigated, and therefore the system linearity is improved, as well as the converter transient response.

[0125] Finally, as mentioned before, the current generators 2250 and 2252 may be implemented as two output stages of the same current mirror. In this respect, the proposes solutions permit that this current mirror may have a less complex design, because also bigger mismatches between the output stages of the current mirror are compensated by the disclosed averaging operation.

[0126] Of course, without prejudice to the principle of the invention, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.

[0127] For example, while the previous embodiments have been described with respect to a PID regulator, the embodiments mainly relate to the implementation of the I component with the transconductor 2236 and the current-controlled oscillators 2220 and 2228. Accordingly, the D and/or P components are purely optional. For example, this implies that one or even both of the transconductor 2238 and 2240 may be omitted.

[0128] Moreover, the solutions may also be applied to the PID regulator shown in FIG. 8 by simply replacing the oscillators 2220 and 2228 with current controlled oscillators. For example, this implies that also voltage-controlled delay lines may be used. Moreover, instead of using differential amplifiers, also a single ended configuration may be used for one or more of the components P, I and D.

[0129] The claims form an integral part of the technical teaching of the description provided herein.