MOS DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

A method of manufacturing a MOS device includes: providing a substrate having a source region and a drain region; forming a sandwich structure on the substrate, which includes a first SiO.sub.2 layer, a high-k dielectric layer, and a second SiO.sub.2 layer stacked sequentially from bottom up; forming a groove in the sandwich structure between the source region and the drain region, the depth of the groove extends from a top surface of the second SiO.sub.2 layer to inside the sandwich structure, wherein the depths at two sides of the groove are shallower than the depth at the center of the groove; forming a gate conductive layer, which fills the groove, wherein a top surface of the gate conductive layer is higher than that of the second SiO.sub.2 layer; and forming a sidewall structure on sidewalls of the gate conductive layer.

Claims

1. A method of manufacturing a MOS device, comprising: providing a substrate, wherein a source region and a drain region are arranged in the substrate and spaced apart along a first direction parallel to the substrate ; forming a sandwich structure on the substrate, wherein the sandwich structure comprises a first SiO.sub.2 layer, a high-k dielectric layer over the first SiO.sub.2 layer, and a second SiO.sub.2 layer over the high-k dielectric layer; forming a groove in the sandwich structure between the source region and the drain region, wherein a width of the groove is arranged along the first direction, wherein a depth of the groove extends from an upper surface of the second SiO.sub.2 layer and ends inside the sandwich structure, and wherein depths at two sides of the groove are shallower than a depth at a center of the groove; forming a gate conductive layer, wherein the gate conductive layer fills the groove, wherein a top surface of the gate conductive layer is arranged to be higher than a top surface of the second SiO.sub.2 layer; and forming a sidewall structure on sidewalls of the gate conductive layer.

2. The method of manufacturing the MOS device according to claim 1, wherein a step of forming the groove comprises: forming a first photoresist layer on the second SiO.sub.2 layer; forming a photoresist layer opening in the first photoresist layer, wherein the photoresist layer opening is located between the source region and the drain region in the first direction, and wherein the photoresist layer opening partially exposes the second SiO.sub.2 layer; and etching the second SiO.sub.2 layer and the high-k dielectric layer using the first photoresist layer as a mask to pattern the groove.

3. The method of manufacturing the MOS device according to claim 1, wherein a bottom surface of the groove is in the shape of a concave arc.

4. The method of manufacturing the MOS device according to claim 1, wherein a bottom surface of the groove is not lower than the top surface of the first SiO.sub.2 layer.

5. The method of manufacturing the MOS device according to claim 1, wherein the step of forming the gate conductive layer comprises: forming a conductive material layer on the second SiO.sub.2 layer and in the groove respectively; forming a second photoresist layer on the conductive material layer; patterning the second photoresist layer to expose portions of the conductive material layer over the source region and the drain region, wherein a portion of the conductive material layer over the groove is still shielded by the second photoresist layer after patterning; and etching the conductive material layer using the second photoresist layer as a mask until the second SiO.sub.2 layer is partially exposed, wherein the portion of the conductive material layer shielded by the second photoresist layer is not etched and forms the gate conductive layer.

6. The method of manufacturing the MOS device according to claim 1, wherein a width of the gate conductive layer is larger than the width of the groove, and wherein two ends of the gate conductive layer are in contact with the top surface of the second SiO.sub.2 layer.

7. The method of manufacturing the MOS device according to claim 1, further comprising: removing regions of the sandwich structure that are not shielded by either the sidewall structure or by the gate conductive layer.

8. The method of manufacturing the MOS device according to claim 1, wherein the first SiO.sub.2 layer is formed by thermal oxidation.

9. A MOS device, comprising: a substrate, wherein a source region and a drain region are arranged in the substrate and are spaced apart in a first direction; a sandwich structure, wherein the sandwich structure is disposed on the substrate, wherein the sandwich structure comprises a first SiO.sub.2 layer, a high-k dielectric layer over the first SiO.sub.2 layer, and a second SiO.sub.2 layer over the high-k dielectric layer; a groove, wherein the groove is disposed in the sandwich structure between the source region and the drain region, wherein a width of the groove is arranged along the first direction; wherein the groove extends from a top surface of the second SiO.sub.2 layer and ends inside the sandwich structure, and wherein depths at two sides of the groove are shallower than a depth at a center of the groove; a gate conductive layer, which fills in the groove, wherein a top surface of the gate conductive layer is higher than the top surface of the second SiO.sub.2 layer; and a sidewall structure which is located on sidewalls of the gate conductive layer.

10. The MOS device according to claim 9, wherein a bottom surface of the groove is in a shape of a concave arc.

11. The MOS device according to claim 9, wherein a bottom surface of the groove is not lower than the top surface of the first SiO.sub.2 layer.

12. The MOS device according to claim 9, wherein a width of the gate conductive layer is larger than a width of the groove, and wherein two sides of the gate conductive layer are in contact with the top surface of the second SiO.sub.2 layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 is a diagram illustrating a cross-sectional view of a MOS device.

[0020] FIG. 2 is a flowchart illustrating a manufacturing method of a MOS device according to an example of the present disclosure.

[0021] FIG. 3 is a cross-sectional view of a substrate provided in a step of a manufacturing method of a MOS device of the present disclosure.

[0022] FIG. 4 is a cross-sectional view of illustrating a sandwich structure on a substrate post the step of forming it according to a manufacturing method of a MOS device of the present disclosure.

[0023] FIG. 5 is a cross-sectional view of illustrating a first photoresist layer on a second SiO.sub.2 layer post the step of patterning the first photoresist layer, according to a manufacturing method of a MOS device of the present disclosure.

[0024] FIG. 6 is a cross-sectional view of illustrating a groove acquired with a first photoresist layer as a mask post the step of etching a second SiO.sub.2 layer and a high-k dielectric layer to obtain it, according to a manufacturing method of a MOS device of the present disclosure.

[0025] FIG. 7 is a cross-sectional view of illustrating a conductive material layer on a second SiO.sub.2 layer and in a groove post the step of forming it, according to a manufacturing method of a MOS device of the present disclosure.

[0026] FIG. 8 is a cross-sectional view of illustrating a second photoresist layer on a conductive material layer post the step of patterning the second photoresist layer, according to a manufacturing method of a MOS device of the present disclosure.

[0027] FIG. 9 is a cross-sectional view of illustrating a conductive material layer with a second SiO.sub.2 layer exposed post the step of etching the layer, according to a manufacturing method of a MOS device of the present disclosure.

[0028] FIG. 10 is a cross-sectional view of illustrating a sidewall structure on sidewalls of a gate conductive layer post the step of forming it, according to a manufacturing method of a MOS device of the present disclosure.

[0029] FIG. 11 is a cross-sectional view of illustrating the sandwich structure post the step of removing regions of the sandwich structure which are not shielded by either a sidewall structure or a gate conductive layer, according to a manufacturing method of a MOS device of the present disclosure.

DETAILED DESCRIPTION

[0030] The following specific examples illustrate examples of the present disclosure, and those skilled in the art can easily understand other advantages and efficacy of the present disclosure from the disclosure of the present application. The present application can also be implemented or applied in other different examples. The details in the present application can be modified or changed based on different viewpoints and usages without departing from the spirit of the present application.

[0031] Refer to FIG. 1 to FIG. 11. It should be noted that the drawings provided are only to illustrate the basic concept of the present disclosure, and thus the components in the drawings are not necessarily drawn according to the actual quantity, shape or size in actual implementation. The type, quantity and proportion of each component in actual implementation can be modified as needed, and the layout of the components may be more complicated than that shown in the drawings. Herein, a horizontal direction refers to a direction parallel to the substrate of the device, and a vertical direction refers to a direction perpendicular to the substrate of the device.

Embodiment 1

[0032] Embodiment 1 provides a manufacturing method of a MOS device. FIG. 2 shows a flowchart illustrating the manufacturing method of the MOS device according to the present disclosure. The manufacturing method includes:

[0033] Step S1: providing a substrate, wherein the substrate includes a source region and a drain region, which are arranged spaced apart horizontally along the direction parallel to the substrate;

[0034] Step S2: forming a sandwich structure on the substrate, wherein the sandwich structure includes a first SiO.sub.2 layer, a high-k dielectric layer, and a second SiO.sub.2 layer sequentially stacked from bottom up;

[0035] Step S3: forming a groove in the sandwich structure, wherein the groove extends from an upper surface of the second SiO.sub.2 layer and ends inside the sandwich structure, wherein the groove is located between the source region and the drain region in the horizontal direction, wherein the depth at the two sides of the groove is shallower than the depth at the center part of the groove, wherein the direction from one side to the other end of the two sides is parallel to the direction pointing from the source region to the drain region;

[0036] Step S4: forming a gate conductive layer, wherein the groove is filled with the gate conductive layer, and a top surface of the gate conductive layer is higher than a top surface of the second SiO.sub.2 layer; and

[0037] Step S5: forming a sidewall structure on sidewalls of the gate conductive layer.

[0038] The details of Step S1 can be referred to FIG. 3. In FIG. 3, a substrate 201 is provided, in which a source region 202 and a drain region 203 are arranged spaced apart from each other horizontally along a direction parallel to the substrate.

[0039] For example, a material of the substrate 201 may include, but is not limited to, semiconductor materials such as silicon, germanium, silicon-germanium, silicon-on-insulator, and III-V compounds. The source region 202 and the drain region 203 can be formed by ion implantation into predetermined regions of the substrate 201. The source region 202 and the drain region 203 have the same dopant type. For example, the substrate 201 may be a P-type silicon substrate, and both the source region 202 and the drain region 203 may be N-type regions.

[0040] For more details of Step S2, refer to FIG. 4. In FIG. 4, formed on the substrate 201, the sandwich structure includes the first SiO.sub.2 layer 204, the high-k dielectric layer 205 and the second SiO.sub.2 layer 206 sequentially stacked up from the bottom layer.

[0041] For example, an ultra-thin SiO.sub.2 layer can be grown by thermal oxidation to form the first SiO.sub.2 layer 204 on the surface of the substrate 201. In this example, a thickness of the first SiO.sub.2 layer 204 may range from 10 to 50 angstroms (A).

[0042] For example, the high-k dielectric layer 205 and the second SiO.sub.2 layer 206 may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD) or other suitable methods. The dielectric constant of the high-k dielectric layer 205 is greater than 3.9, and its material includes, but is not limited to, at least one of nitrogen-doped silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, and zirconium oxide. In this example, a thickness of the high-k dielectric layer 205 may range from 50 A to 200 A.

[0043] Details of structures after Step S3 are shown in FIG. 5 and FIG. 6. As shown in FIG. 5 and FIG. 6, the groove 207 is formed in the sandwich structure, wherein the groove 207 extends from the upper surface of the second SiO.sub.2 layer 206 and ends inside the sandwich structure. The groove 207 is located between the source region 202 and the drain region 203 in the horizontal direction, and the two sides of the groove 207 are shallower than the center of the groove 207, wherein the direction from one sides to the other side of the two sides is parallel to the direction pointing from the source region 203 to the drain region 202.

[0044] For example, the step of forming the groove 207 may further include:

[0045] Step S3-1: forming a first photoresist layer 208 on the second SiO.sub.2 layer 206 using spin coating or other suitable methods;

[0046] Step S3-2: (as shown in FIG. 5) forming a photoresist layer opening 209 in the first photoresist layer 208 using photolithography processes including exposure, development, etc. The photoresist layer pattern opening 209 is located between the source region 202 and the drain region 203 in the horizontal direction, and the photoresist layer opening 209 partially exposes the second SiO.sub.2 layer 206;

[0047] Step S3-3: (as shown in FIG. 6) etching the second SiO.sub.2 layer 206 and the high-k dielectric layer 205 using the first photoresist layer 208 (with the photoresist layer opening 209) as a mask, to obtain the groove 207.

[0048] For example, in one particular example, the groove 207 can be formed by wet etching, wherein the wet etching may be isotropic etching, and a bottom surface of the groove 207 may be in the shape of a concave arc, with two shallower sides and a deeper center.

[0049] For example, in another example, the groove 207 can be obtained using wet etching combined with dry etching.

[0050] For example, the bottom surface of the groove 207 is not lower than the top surface of the first SiO.sub.2 layer 204, thus ensuring the integrity of the first SiO.sub.2 layer 204.

[0051] For example, the bottom surface of the groove 207 extends into the high-k dielectric layer 205.

[0052] More details of Step S4 are shown in FIGS. 7-9. As shown in FIGS. 7-9, the first photoresist layer 208 is removed, and a gate conductive layer 210 is formed. The gate conductive layer 210 is filled in the groove 207, and a top surface of the gate conductive layer 210 is higher than the top surface of the second SiO.sub.2 layer 206.

[0053] For example, a width of the gate conductive layer 210 may be smaller than, equal to, or larger than a width of the groove 207, with the widths extending in a direction parallel to the substrate. In one example, the width of the gate conductive layer 210 is preferably larger than the width of the groove 207. In the direction pointing from the source region 202 to the drain region 203, bottom surfaces of two ends of the gate conductive layer 210′ are in contact with the top surface of the second SiO.sub.2 layer 206, which helps to reduce the contact area between the two ends of the gate conductive layer 210 and a gate dielectric layer.

[0054] For example, the gate conductive layer 210 may be formed using following steps:

[0055] S4-1: (as shown in FIG. 7) forming a conductive material layer 210′ on the second SiO.sub.2 layer 206 and in the groove 207 using CVD, PVD or other suitable methods, and the material of the conductive material layer 210′ includes, but is not limited to, polysilicon;

[0056] S4-2: forming a second photoresist layer 211 on the conductive material layer 210′ using spin coating or other suitable methods;

[0057] S4-3: (as shown in FIG. 8) patterning the second photoresist layer 211 using photolithography processes including exposure, development, etc., to expose portions of the conductive material layer 210′ over the source region 202 and the drain region 203, while a portion of the conductive material layer 210′ over the groove 207 is still shielded by the second photoresist layer 211 after patterning.

[0058] S4-4: (as shown in FIG. 9) etching the conductive material layer 210′ using the second photoresist layer 211 as a mask until the second SiO.sub.2 layer 206 is partially exposed, while the region of the conductive material layer 210′ shielded by the patterned second photoresist layer 211 is not etched and forms the gate conductive layer 210.

[0059] Details of Step S5 are shown in FIG. 10 and FIG. 11. As shown in FIG. 10 and FIG. 11, the sidewall structure is formed on the sidewalls of the gate conductive layer 210.

[0060] For example, as shown in FIG. 10, surfaces of the gate conductive layer 210 are oxidized to obtain an oxide layer 212, and a silicon nitride layer 213 is deposited on surfaces of the oxide layer 212 to obtain the sidewall structure including the oxide layer 212 and the silicon nitride layer 213. Then, as shown in FIG. 11, wet etching and/or dry etching can be used to remove the region of the sandwich structure that is not covered by either the sidewall structure or the gate conductive layer 210, wherein the region of the sandwich structure covered by the sidewall structure and the gate conductive layer 210 remains, and serves as a gate dielectric layer.

[0061] In the manufacturing method of the MOS device, a relatively thick multi-material sandwich structure is first formed, and then etched to obtain a gate dielectric layer that is thin in the middle and thick at two ends. Such a design increases the breakdown voltage of the MOS device and mitigates the negative impact of the thickness of the gate dielectric layer on the turn-on voltage of the MOS device. The breakdown voltage is further increased by adding a high-k dielectric layer.

Embodiment 2

[0062] This embodiment provides a MOS device, which may be manufactured using the methods in Embodiment 1 or other suitable methods.

[0063] Referring to FIG. 11 which shows a MOS device. The MOS device comprises a substrate 201, a sandwich structure, a groove 207, a gate conductive layer 210, and a sidewall structure. A source region 202 and a drain region 203 are arranged in the substrate 201, and spaced apart in a direction parallel to the substrate. The sandwich structure is located on the substrate 201, and comprises a first SiO.sub.2 layer 201, a high-k dielectric layer 205, and a second SiO.sub.2 layer 206 stacked sequentially from bottom up. The groove 207 is located in the sandwich structure, and extends from an upper surface of the second SiO.sub.2 layer 206 and ends inside the sandwich structure. The groove 207 is located between the source region 202 and the drain region 203 in a horizontal direction, and two sides of the groove 207 are shallower than the center of the groove 207, wherein the direction from one end to the other end of the two ends is parallel to the direction pointing from the source region 202 to the drain region 203. The gate conductive layer 210 fills in the groove 207, and a top surface of the gate conductive layer 210 is higher than a top surface of the second SiO.sub.2 layer 206. The sidewall structure is located on sidewalls of the gate conductive layer 210.

[0064] For example, the sidewall structure comprises an oxide layer 212, and a silicon nitride layer 213 formed on surfaces of the oxide layer 212.

[0065] For example, a bottom surface of the groove 207 is in the shape of a concave arc.

[0066] For example, the bottom surface of the groove 207 is not lower than the top surface of the first SiO.sub.2 layer 206.

[0067] For example, a width of the gate conductive layer 210 may be smaller than, equal to or larger than a width of the groove 207. In an example, the width of the gate conductive layer 210 is preferably larger than the width of the groove 207. Bottoms surfaces of both ends of the gate conductive layer 210 are in contact with the top surface of the second SiO.sub.2 layer 206, which reduces potential defects in the contact regions between the two ends of the gate conductive layer 210 and the gate dielectric layer.

[0068] In summary, in the MOS device of the present disclosure, the gate dielectric layer is a sandwich structure composed of SiO.sub.2/high-k dielectric layer/SiO.sub.2; the high-k dielectric layer in the middle aids in preventing breakdown and increasing breakdown voltage of the MOS device; the upper and lower SiO.sub.2 layers reduce interface strains, and maintain high matching degrees between the gate oxide and substrate, and between the gate oxide and gate conductive layer. In the MOS device structure of the present disclosure, the gate dielectric layer is also designed to be thin in the middle and thick at two ends; the thicker ends mitigate the influence of source and drain voltages in edges of the source region and the drain region, thereby increasing the breakdown voltage, while the thinner middle can ensure that the conductive channel can still be turned on at a low voltage as usual, so that the turn-on voltage has no obvious difference from that of a traditional structure. That is, the present disclosure can increase the breakdown voltage of the MOS device without affecting its turn-on voltage. As a result, the present application effectively overcomes various shortcomings in the prior art, and is of high industrial utilization value.

[0069] The above examples only illustrate the principle and efficacy of the present disclosure, and are not meant to limit the present disclosure. Any skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideology of the present disclosure shall fall within the claimed scope of the present disclosure.