Electronic device with reduced process spread bandgap

Abstract

An electronic device is provided, including: a terminal configured for receiving a bandgap voltage reference, generated by incorporating a first base-emitter voltage subject to process variation; the electronic device including a first transistor with a base configured to be exposed to the bandgap voltage reference; the first transistor is biased with a constant collector current corresponding with the first base-emitter voltage, and is configured for providing a shifted voltage, VE, based on decreasing the bandgap voltage reference by a second base-emitter voltage subject to the process variation; and the electronic device including a second transistor, of the same type as the first transistor, including an emitter configured to be exposed to the shifted voltage; and the second transistor is biased with a constant base current and is configured for providing a restored bandgap voltage based on increasing the shifted voltage by a third base-emitter voltage.

Claims

1. An electronic device comprising: a terminal configured for receiving a bandgap voltage reference (VBG), generated by incorporating a first base-emitter voltage (VBE1), wherein the VBE1 is subject to process variation; a first transistor comprising a base configured to be exposed to the VBG, wherein the first transistor is biased with a constant collector current (IC) corresponding with the VBE1, and is configured for providing a shifted voltage (VE) based on decreasing the VBG by a second base-emitter voltage (VBE2), and wherein the VBE2 is subject to the process variation; and a second transistor of the same type as the first transistor, comprising an emitter configured to be exposed to the VE, wherein the second transistor is biased with a constant base current (IB), and is configured for providing a restored bandgap voltage (VBG2) based on increasing the VE by a third base-emitter voltage (VBE3), wherein the VBE3 is based on a proportional to absolute temperature (PTAT) current.

2. The electronic device of claim 1, further comprising a branch connected to the emitter of the first transistor and to the emitter of the second transistor, so that the branch is configured to carry a summed emitter current (IE).

3. The electronic device of claim 1, wherein the VBE1 is subject to process variation due to being generated by a bandgap core transistor, and wherein the first transistor and the second transistor are of the same type as the core transistor.

4. An electronic device comprising: a terminal configured for receiving a bandgap voltage reference (VBG) generated by incorporating a first base-emitter voltage (VBE1), wherein the VBE1 Is subject to process variation; a first transistor comprising a base configured to be exposed to the VBG, wherein the first transistor is biased with a constant collector current (IC) corresponding with the VBE1, and is configured for providing a shifted voltage (VE) based on decreasing the VBG by a second base-emitter voltage (VBE2), and wherein the VBE2 is subject to the process variation; a second transistor of the same type as the first transistor, comprising an emitter configured to be exposed to the VE, wherein the second transistor is biased with a constant base current (IB) and is configured for providing a restored bandgap voltage (VBG2) based on increasing the VE by a third base-emitter voltage (VBE3); a branch connected to the emitter of the first transistor and to the emitter of the second transistor, so that the branch is configured to carry a summed emitter current (IE); a first current mirror arranged to mirror the IE, wherein the first current mirror comprises: a first branch configured for carrying a scaled base current (*IB) and a core current (ICORE); a second branch configured for carrying the IE the first branch of the first current mirror comprising a second current mirror arranged to mirror the *IB supplied to the collector of the second transistor; a third transistor comprising a base configured to be exposed to the IB, wherein the third transistor is configured for providing the *IB in the first branch to be summed with the ICORE; and a terminal arranged to supply the ICORE, into the first branch to be summed with the *IB.

5. An electronic device comprising: a terminal configured for receiving a bandgap voltage reference (VBG) generated by incorporating a first base-emitter voltage (VBE1), wherein the VBE1 is subject to process variation; a first transistor comprising a base configured to be exposed to the VBG, wherein the first transistor is biased with a constant collector current (IC) corresponding with the VBE1, and is configured for providing a shifted voltage (VE) based on decreasing the VBG by a second base-emitter voltage (VBE2), and wherein the VBE2 is subject to the process variation; a second transistor of the same type as the first transistor, comprising an emitter configured to be exposed to the VE, wherein the second transistor is biased with a constant base current (IB) and is configured for providing a restored bandgap voltage (VBG2) based on increasing the VE by a third base-emitter voltage (VBE3); a branch connected to the emitter of the first transistor and to the emitter of the second transistor, so that the branch is configured to carry a summed emitter current (IE); a first current mirror arranged to mirror the IE, wherein the first current mirror comprises: a first branch configured for carrying a scaled base current (*IB), and a core current (ICORE); a second branch configured for carrying the IE: the first branch of the first current mirror comprising a second current mirror arranged to mirror the ICORE supplied to the collector of the first transistor; and a third transistor arranged in parallel to the second current mirror of the first branch, wherein the third transistor comprises a base configured to be exposed to the IB, and wherein the third transistor is configured for providing the *IB into the first branch to be summed with the ICORE.

6. An electronic device comprising: a terminal configured for receiving a bandgap voltage reference (VBG) generated by incorporating a first base-emitter voltage (VBE1), wherein the VBE1 is subject to process variation; a first transistor comprising a base configured to be exposed to the VBG, wherein the first transistor is biased with a constant collector current (IC) corresponding with the VBE1 and is configured for providing a shifted voltage (VE) based on decreasing the VBG by a second base-emitter voltage (VBE2), and wherein the VBE2 is subject to the process variation; a second transistor of the same type as the first transistor, comprising an emitter configured to be exposed to the VE, wherein the second transistor is biased with a constant base current (IB) and is configured for providing a restored bandgap voltage (VBG2) based on increasing the VE by a third base-emitter voltage (VBE3) wherein the VBE1 is subject to process variation due to being generated by a bandgap core transistor, and wherein the first transistor and the second transistor are of the same type as the core transistor.

7. The electronic device of claim 6, further comprising a branch connected to the emitter of the first transistor and to the emitter of the second transistor, so that the branch is configured to carry a summed emitter current (IE).

8. The electronic device of claim 6, further comprising a current mirror arranged to mirror the IE, wherein the current mirror comprises: a first branch configured for carrying a scaled base current (*IB), and a core current, (ICORE); and a second branch configured for carrying the IE.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) In the following description, a number of exemplary embodiments will be described in more detail, to help understanding, with reference to the appended drawings, in which:

(2) FIG. 1 schematically illustrates a first embodiment of the electronic device according to the present disclosure.

(3) FIG. 2 schematically illustrates a second embodiment of the electronic device according to the present disclosure.

(4) FIG. 3 schematically illustrates an example of a core circuit relating to the present disclosure.

DETAILED DESCRIPTION

(5) FIG. 1 schematically illustrates a first embodiment 100 of the electronic device according to the present disclosure.

(6) The electronic device 100 comprises: a terminal 103 configured for receiving a bandgap voltage reference, VBG, generated by incorporating a first base-emitter voltage, VBE1; the first base-emitter voltage, VBE1, being subject to process variation; a first transistor 101 comprising a base configured to be exposed to the bandgap voltage reference, VBG; wherein the first transistor is biased with a constant collector current, IC, corresponding with the first base-emitter voltage, VBE1, and is configured for providing a shifted voltage, VE, based on decreasing the bandgap voltage reference, VBG, by a second base-emitter voltage, VBE2; the second base-emitter voltage, VBE2, being subject to said process variation; and a second transistor 102, of the same type as the first transistor, comprising an emitter configured to be exposed to the shifted voltage, VE; wherein the second transistor is biased with a constant base current, IB, and is configured for providing a restored bandgap voltage, VBG2, based on increasing the shifted voltage, VE, by a third base-emitter voltage, VBE3.

(7) The third base-emitter voltage VBE3 does not introduce the process variation back into the signal, because its effective process variation is compensated by running the second transistor at the constant base current IB.

(8) The base current for the bipolar differential pair is injected into the VBG node. This node is likely either low-impedance or already compensated for the existing bandgap base current depending on the bandgap topology.

(9) Furthermore, the electronic device 100 may comprise a branch 104 connected to the emitter of the first transistor 101 and to the emitter of the second transistor 102, such that the branch 104 is configured to carry a summed emitter current, IE. This summed emitter current IE may be equal to *IB+ICORE, as shown in the figure.

(10) Furthermore, the electronic device 100 may comprise a current mirror 105 arranged to mirror the summed emitter current, IE. The current mirror 105 may comprise: a first branch 107 configured for carrying a scaled base current, *IB, and a core current, ICORE (which may be equal to the constant collector current IC); and a second branch 106 configured for carrying the summed emitter current, IE.

(11) The current mirror 105 may further comprise transistors 108 and 109.

(12) Furthermore, the first branch 107 may comprise: a current mirror 110 arranged to mirror the core current, ICORE, supplied to the collector of the first transistor 101. The current mirror 110 may comprise transistors 111 and 112.

(13) The first branch 107 may further comprise: a transistor 115 arranged in parallel to said current mirror 110 of the first branch 107. Said transistor 115 may comprise a base configured to be exposed to the constant base current, IB; and said transistor 115 may be configured for providing the scaled base current, *IB, into the first branch 107, to be summed with said mirrored core current, ICORE.

(14) Alternatively, one could tap off the old PTAT voltage and use a summer to add the PTAT to the constant base current VBE. However, this approach requires more transistors and has a greater opportunity for mismatch and other nonidealities.

(15) FIG. 2 schematically illustrates a second embodiment 200 of the electronic device according to the present disclosure. Here, as in the first embodiment described above, the electronic device 200 comprises: a terminal 103 configured for receiving a bandgap voltage reference, VBG, generated by incorporating a first base-emitter voltage, VBE1; the first base-emitter voltage, VBE1, being subject to process variation; a first transistor 101 comprising a base configured to be exposed to the bandgap voltage reference, VBG; wherein the first transistor is biased with a constant collector current, IC, corresponding with the first base-emitter voltage, VBE1, and is configured for providing a shifted voltage, VE, based on decreasing the bandgap voltage reference, VBG, by a second base-emitter voltage, VBE2; the second base-emitter voltage, VBE2, being subject to said process variation; and a second transistor 102, of the same type as the first transistor, comprising an emitter configured to be exposed to the shifted voltage, VE; wherein the second transistor is biased with a constant base current, IB, and is configured for providing a restored bandgap voltage, VBG2, based on increasing the shifted voltage, VE, by a third base-emitter voltage, VBE3.

(16) Furthermore, the electronic device 200 may comprise a branch 104 connected to the emitter of the first transistor 101 and to the emitter of the second transistor 102, such that the branch 104 is configured to carry a summed emitter current, IE. This summed emitter current IE may be equal to *IB+ICORE, as shown in the figure.

(17) Furthermore, the electronic device 200 may comprise a current mirror 105 arranged to mirror the summed emitter current, IE. The current mirror 105 may comprise: a first branch 107 configured for carrying a scaled base current, *IB, and a core current, ICORE (which may be equal to the constant collector current IC); and a second branch 106 configured for carrying the summed emitter current, IE.

(18) The current mirror 105 may further comprise transistors 108 and 109.

(19) Furthermore, the first branch 107 may comprise: a current mirror 201 arranged to mirror the scaled base current, *IB, supplied to the collector of the second transistor 102; a transistor 204 comprising a base configured to be exposed to the constant base current, IB; wherein said transistor is configured for providing the scaled base current, *IB, in the first branch; and a terminal 205 arranged to supply the core current, ICORE, into the first branch 107, to be summed with said scaled base current, *IB.

(20) It is noted that, in other words, the transistor 204 is thus arranged to generate the scaled base current, i.e. *IB. That current goes two places: out of the base to make part of the tail current and through the current mirror to force the second transistor 102 to conduct the same current (once the loop is closed).

(21) The second embodiment 200 mitigates the risk of mismatch (both random and systematic). Errors in the tail current are less likely to corrupt the current in the second transistor 102. The current through the second transistor 102 will likely be very low at cold and low to avoid throwing away current at hot and high .

(22) In practice, the second embodiment 200 allows more reasonable current levels to be chosen to achieve a given performance.

(23) The topology of the embodiments described in the present disclosure also helps to provide a low impedance bandgap reference.

(24) FIG. 3 schematically illustrates a core circuit arranged for supplying the described bandgap voltage reference and various other currents including IB and *IB.

(25) It is noted that other embodiments according to the present disclosure may be designed with PNPs as well as with NPNs. The MOSFETs shown in the exemplary first and second embodiments described above are primarily used as mirrors, so the circuit may also be seen as independent of MOSFET type or voltage rating, and the circuit could thus be designed without MOSFETs, using BJTs only.

(26) As used in this application and in the claims, the singular forms a, an, and the include the plural forms unless the context clearly dictates otherwise. The systems, apparatus, and methods described herein should not be construed as limiting in any way. Instead, the present disclosure is directed toward all novel and non-obvious features and aspects of the various disclosed embodiments, alone and in various combinations and sub-combinations with one another. The disclosed systems, methods, and apparatus are not limited to any specific aspect or feature or combinations thereof, nor do the disclosed systems, methods, and apparatus require that any one or more specific advantages be present or problems be solved. Any theories of operation are to facilitate explanation, but the disclosed systems, methods, and apparatus are not limited to such theories of operation.

(27) Although the operations of some of the disclosed methods are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed systems, methods, and apparatus can be used in conjunction with other systems, methods, and apparatus. Additionally, the description sometimes uses terms like obtaining and outputting to describe the disclosed methods. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by the skilled person.

(28) It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals may have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the examples described herein. However, it will be understood by the skilled person that the examples described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features. The description is not to be considered as limiting the scope of the examples described herein.

LIST OF REFERENCE NUMBERS

(29) 100 first embodiment 101 first transistor 102 second transistor 103 terminal 104 branch 105 current mirror 106 second branch 107 first branch 108 transistor 109 transistor 110 current mirror 111 transistor 112 transistor 113 transistor 114 transistor 115 transistor 200 second embodiment 201 current mirror 202 transistor 203 transistor 204 transistor 205 terminal 206 transistor 300 core circuit