CONFIGURABLE MICROPHONE USING INTERNAL CLOCK CHANGING

Abstract

A method of operating a microelectromechanical system (MEMS) includes, in a first operational mode, converting an analog output of the MEMS into a first internal data stream and a first external data stream having a first sampling rate; transitioning from the first operational mode to a second operation mode without restarting the MEMS; and in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream.

Claims

1. A circuit comprising: a clock divider having an input coupled to a clock signal input; a multiplexer having a first input coupled to an output of the clock divider, a second input coupled to the clock signal input, a third input coupled to a control signal input, and an output, wherein the multiplexer couples the first input to the output or couples the second input to the output according to a state of the control signal input; a signal processing circuit having an analog signal input, a clock signal input coupled to the output of the multiplexer, and a digital signal output comprising one or more output nodes; and a frequency converter coupled between the digital signal output of the signal processing circuit and a data stream output, wherein a conversion factor of the frequency converter is determined according to the state of the control signal input.

2. The circuit of claim 1, wherein the signal processing circuit comprises: an analog-to-digital converter (ADC) having an input coupled to the analog signal input; a digital filter having an input coupled to an output of the ADC; and a digital modulator having an input coupled to an output of the digital filter and an output coupled to the digital signal output.

3. The circuit of claim 1, wherein the signal processing circuit comprises: an analog-to-digital converter (ADC) having an input coupled to the analog signal input; and a digital filter having an input coupled to an output of the ADC and an output coupled to the digital signal output.

4. The circuit of claim 3, further comprising a digital modulator interposed between the frequency converter and the data stream output.

5. The circuit of claim 4, further comprising an additional frequency converter interposed between the digital modulator and the data stream output.

6. The circuit of claim 3, wherein the digital filter comprises an additional input for receiving a first set of coefficients or a second set of coefficients according to the state of the control signal input.

7. The circuit of claim 1, further comprising a microelectromechanical system (MEMS) having an output coupled to the analog signal input of the signal processing circuit.

8. The circuit of claim 7, wherein the MEMS comprises a microphone.

9. A microelectromechanical system (MEMS) circuit in a single package comprising: a control signal input, a clock signal input, and a data stream output for providing a constant rate single bit output stream at one or more output nodes; a MEMS device; and a signal processing circuit coupled to the MEMS device, to the control signal input, to the clock signal input, and the data stream output, wherein, in a first mode of operation determined by a first state of the control signal input, at least a portion of the signal processing circuit is directly coupled to the clock signal input, and wherein, in a second mode of operation determined by a second state of the control signal input, the at least a portion of the signal processing circuit is coupled to the clock signal input through a clock divider.

10. The MEMS circuit of claim 9, wherein the signal processing circuit comprises an analog-to-digital converter (ADC) having an input coupled to the MEMS device and a digital filter having an input coupled to an output of the ADC.

11. The MEMS circuit of claim 10, wherein the ADC comprises a sigma-delta ADC.

12. The MEMS circuit of claim 10, wherein the digital filter is configured to receive a first set of coefficients in the first mode of operation and a second set of coefficients in the second mode of operation.

13. The MEMS circuit of claim 9, wherein the MEMS device comprises a microphone.

14. The MEMS circuit of claim 9, further comprising a first frequency converter coupled between an output of the signal processing circuit and the data stream output, wherein a conversion factor of the first frequency converter is determined according to whether the state of the control signal input in in the first state or in the second state.

15. The MEMS circuit of claim 14, further comprising a digital modulator coupled to the data stream output and to the first frequency converter, wherein the digital modulator is clocked at a constant frequency regardless of whether the state of the control signal input in in the first state or in the second state.

16. The MEMS circuit of claim 15, further comprising a second frequency converter, wherein the first frequency converter is coupled between an output of the signal processing circuit and an input to the digital modulator, the second frequency converter is coupled between an output of the digital modulator and the data stream output, and a conversion factor of the second frequency converter is determined according to whether the state of the control signal input in in the first state or in the second state.

17. A method of operating a microelectromechanical system (MEMS) device, the method comprising: receiving a control signal at a control signal input; receiving a clock signal at a clock signal input; receiving an analog signal from the MEMS device at a signal processing circuit; in a first mode of operation determined by a first state of the control signal, directly coupling at least a portion of the signal processing circuit to the clock signal input; in a second mode of operation determined by a second state of the control signal, coupling the at least a portion of the signal processing circuit to the clock signal input through a clock divider; and providing a constant rate output stream at a data stream output of the signal processing circuit.

18. The method of claim 17, further comprising: converting the analog signal into a digital signal using an analog-to-digital converter (ADC) of the signal processing circuit; receiving by a digital filter having an input coupled to an output of the ADC, a first set of coefficients in the first mode of operation and a second set of coefficients in the second mode of operation; and filtering the digital signal using the digital filter.

19. The method of claim 17, further comprising: outputting a digital signal from the signal processing circuit; and determining a conversion factor of a frequency converter according to whether the control signal input in in the first state or in the second state; and converting a frequency of the digital signal using the frequency converter, wherein the frequency converter is coupled between an output of the signal processing circuit and the data stream output.

20. The method of claim 19, further comprising: modulating the digital signal using a digital modulator; and clocking the digital modulator at a constant frequency regardless of whether the control signal input in in the first state or in the second state.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0009] FIG. 1A shows a digital microphone with internal clock changing, according to an embodiment;

[0010] FIG. 1B shows a flow chart of a method of operating a digital microphone with internal clock changing, according to an embodiment;

[0011] FIG. 2 shows a modulator for the embodiment of FIG. 1A, according to an embodiment;

[0012] FIG. 3A shows a repeater for the embodiment of FIG. 1A, according to an embodiment;

[0013] FIG. 3B shows a corresponding diagram for the input and output functions with respect to frequency of the repeater of FIG. 3A;

[0014] FIG. 4 shows another embodiment of a digital microphone with internal clock changing, wherein the digital modulator clock rate is constant;

[0015] FIG. 5 shows another embodiment of a digital microphone having multiple repeaters;

[0016] FIG. 6 shows another embodiment of a digital microphone having adaptable filter coefficients;

[0017] FIG. 7A shows a simulated timing diagram associated with a digital microphone including a restart delay period; and

[0018] FIG. 7B shows a simulated timing diagram associated with any of the digital microphone embodiments shown in FIG. 1, 4, 5, or 6.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0019] In standard digital microphones the adjustment of or switching between microphone performance and microphone power consumption is handled by selecting different operating modes, which in turn is typically controlled by selecting different clock rates only. For example, a low power operating mode of the digital microphone may having a corresponding sampling frequency of f.sub.s=768 kHz, whereas a high performance operating mode of the digital microphone may have a corresponding sampling frequency of f.sub.s=3.072 MHz. Other frequencies for the high performance operating mode can be used such as 2.4 MHz or 1.536 MHz, in embodiments. If an operating mode change is required, for example a change from a low power mode to a high performance mode, the digital microphone clock is changed from 768 kHz to 3.072 MHz. To perform the mode change in the digital microphone the (changed) clock is detected (typically using a power mode detector (PMD)). In existing digital microphones the mode change is typically handled as a startup (or restart) of the digital microphone for safety reasons. During a mode change the acoustic signal is not available, which can also cause switching artefacts. Typically, the operating mode change can take between 1 ms and 10 ms, measured between the end of a first operating mode to the beginning of a second operating mode.

[0020] An advantage of some embodiments includes the ability to seamlessly adjust between operating modes without restart delay and with minimal switching artefacts (for example during seamless dynamic SNR adjustment or during seamless dynamic power saving strategies). Embodiments of a digital microphone and method of operating a digital microphone are therefore described below wherein an adjustment or switching between a low power mode and a high performance operating mode occurs seamlessly without any restart delay and with a minimum of switching artefacts. In an embodiment, only one additional external control signal input to the digital microphone is required, and the clock rate or sampling rate of an output signal at one or more output nodes of the digital microphone is configured to be constant between the two operating modes.

[0021] In an embodiment, when an external control signal (ctrl) is available, the performance (SNR) and/or power consumption of a digital microphone can be flexibly and seamlessly changed, by deriving different internal clock rates with a clock divider block responsive to the external control signal (ctrl) from a constant incoming clock (clk) as will be described in further detail below. According to an embodiment, a constant output signal clock rate can be provided by an adjustable interpolation stage that is also responsive to the external control signal (ctrl) that is also described in further detail below.

[0022] FIG. 1A shows a digital microphone 100 with internal clock changing, according to an embodiment. Digital microphone 100 is typically provided in a ported ceramic or plastic package and includes a MEMS microphone sensor 102 and an ASIC 104A coupled to MEMS microphone sensor 102. ASIC 104A receives an analog signal 103 from MEMS microphone sensor 102 and provides a digital output 114 corresponding to the analog signal 103 having N nodes or bits, wherein N is an integer between 1 and 8, in an embodiment. In another embodiment, N can be an integer greater than eight. In an embodiment, digital microphone 100 includes a control input 110 for receiving the control input signal (ctrl) and a clock input 112 for receiving the clock input signal (clk). In an embodiment, a multiplexer 106 is coupled between the control input 110 and the ASIC 104A, and a clock divider 108 is coupled between the clock input 112 and the multiplexer 106. The control input 110 is also coupled to the ASIC 104A. The operation of the ASIC 104A, multiplexer 106, and clock divider 108 with respect to the clk and ctrl signals is described in further detail below.

[0023] ASIC 104A includes a signal processing circuit 116A coupled to a repeater 124. The input signal of the signal processing circuit is the analog signal 103 of ASIC 104A, and the output of repeater 124 is the digital output 114 of ASIC 104A. In FIG. 1A, signal processing circuit 116A includes an ADC 118 that can comprise a sigma-delta ADC, in an embodiment. The ADC 118 converts the analog signal 103 received from the MEMS microphone sensor 102 into a data stream comprising one or more bit streams at one or more nodes. In an embodiment, a digital filter 120 can comprise a loop filter and is used for further processing the digital output of ADC 118. For example, digital filter 120 can be used for removing quantization noise outside of the pass band of the filter. A digital modulator 122 is used for noise-shaping of the filtered digital output from digital filter 120. The output of digital modulator 122 forms the output of signal processing circuit 116A in the example of FIG. 1A. Finally, the output of signal processing circuit 116A is coupled to repeater 124, which in the example of FIG. 1A is not part of the signal processing circuit 116A. In the example of FIG. 1A, the output of multiplexer 106 provides the clock signal for the signal processing circuit 116A, notably the ADC 118, and repeater 124 is coupled directly to control input 110 for directly receiving the control signal, ctrl.

[0024] Multiplexer 106 has three inputs, and an output. A first input receives the ctrl signal at control input 110. A second input receives a divided version of the clk signal through clock divider 108, and a third input received an undivided version of the clk signal directly from clock input 112. The logic state of the ctrl signal thus controls whether or not the divided or undivided clock signal is transferred through multiplexer 106 to the multiplexer output.

[0025] Clock divider 108 is a divider circuit that divides the input clock signal by a factor (D). For example, in the low power operating mode, clock divider 108 can divide the clock signal by two (D=2), by four (D=4) or other any other factor.

[0026] To obtain flexibility in terms of performance (SNR) and/or power consumption, different clock rates generated by the clock divider 108 and multiplexer 106 from the constant incoming clock rate (clk) can be used by signal processing circuit 116A. In the case of a reduced internal clock rate (clkred=clk/D). The clock rate of the output data stream at digital output 114 can be made constant by repeater 124. In the simplest implementation, repeater 124 can be a repeater interpolating (repeating values) at a factor D. In the high performance operating mode, the undivided clock signal is provided to signal processing circuit 116A. Thus, the sampling rate for the ADC is the same as the clock frequency of the input clock signal, clk at clock input 112. The state of the control signal configures repeater 124 to not add any additional zeroes to the output of the digital signal received from signal processing circuit 116A. In the low power operating mode, the divided clock signal is provided to signal processing circuit 116A. Thus, the sampling rate for the ADC is equal to the clock frequency of the input clock signal divided by D. The state of the control signal configures repeater 124 to add an appropriate number of zeroes to the output of the digital signal received from signal processing circuit 116A, such that the clock rate of the digital signals provided in the high performance operating mode and the low power operating mode are the same.

[0027] A further advantage of the digital microphone embodiment shown in FIG. 1A is that there is no interruption of the audio signal (compared to up to 10 ms in an existing solution). The solution provided by the embodiment of FIG. 1A enables the possibility to minimize switching artefacts (or transients) if the internal clock rate is changed (e.g. by selecting zero crossings of the audio signal, and adapting filter coefficients to new selected internal clock rate as is described in further detail below.)

[0028] In addition, the digital microphone embodiment of FIG. 1A allows an embodiment without an input clock related to power mode switching. In such a configuration, all power mode detection related blocks in the digital microphone can be removed, which minimizes design complexity, silicon die area and power dissipation.

[0029] FIG. 1A thus shows an embodiment wherein ASIC 104A is clocked at the derived clock rate defined by the control signal ctrl. At the digital output 114, the single bit or N bit digital output signal is again interpolated up to the input clock rate when required, for example in the low power mode.

[0030] FIG. 1B illustrates a method 160 of operating a microelectromechanical system (MEMS) that includes, in a first operational mode (for example a high performance operating mode), converting an analog signal 103 of the MEMS microphone sensor 102 into a first internal data stream (at output of ADC 118) and a first external data stream (at digital output 114) having a first sampling rate (derived from the undivided clock frequency), which is step 162. Transitioning from the first operational mode to a second operation mode (for example a low power mode) without restarting the MEMS, which is step 164. And, in the second operational mode, converting the analog signal 103 of the MEMS microphone sensor 102 into a second internal data stream (at output of ADC 118) having a second sampling rate (derived from the divided clock frequency) different from the first sampling rate, and performing a sampling rate conversion (using repeater 124 to add the appropriate number of zeroes) of the second internal data stream to generate a second external data stream (at digital output 114), which is step 166.

[0031] FIG. 2 shows a digital modulator 122 for the digital microphone embodiment of FIG. 1A. In an embodiment, digital modulator 122 includes an input 132 that is coupled to digital filter 120, shown in FIG. 1A. In an embodiment, input 132 receives a 22 bit data stream on a digital bus from digital filter 120. In other embodiments, other sized data streams can be received from digital filter 120. Input 132 is coupled to an input of summer 130, whose output is coupled to loop filter 126. Loop filter 126 has a transfer function labeled H(z), and in an embodiment can comprise a low-pass filter. The output of loop filter 126 is coupled to a quantizer 128 providing a stair-step function and providing an N bit digital output, which can comprise one or more digital bits. The digital output is fed back to a negative input of summer 130 through feedback path 134.

[0032] FIG. 3A shows an example of repeater 124 for the digital microphone embodiment of FIG. 1A. When the repeater function is desired, for example, in the low power mode operating mode, additional zeroes are added to the transfer function of the repeater, so that, in the case of the example of FIG. 1A, the original sampling rate of the digital output signal can be restored. Thus, the left-hand portion of FIG. 3A shows a repeater having an L transfer function 136 for converting an input sample frequency f.sub.s (and in the frequency domain the input function is written x(k)) and an output sample frequency of L*f.sub.s (and in the frequency domain the output function is written y(k)), wherein L can be an integer greater than one. The right-hand portion of FIG. 3A breaks the L transfer function 136 into two components, an L component coupled to the control input 110 for specifying the number of extra zeroes required, and an averaging filter 140, having the transfer function of 1+z.sup.1+ . . . +z.sup.(L-1).

[0033] FIG. 3A thus shows an equivalency. The left hand portion of FIG. 3A shows that the input signal on a low sampling rate is repeated (on the high sampling rate, the sampling rate is increased by a factor of L from low sampling rate). The right hand side shows the same signals obtained with a standard interpolation approach. In block 138 zeros are inserted (two zeros if L=3) followed by an averaging filter 140.

[0034] A corresponding time domain plot is shown in FIG. 3B. The left-hand portion of FIG. 3B corresponds to the input function x(k) versus the sample frequency f.sub.s, and the right-hand portion of FIG. 3B corresponds to the output function y(k) versus the sample frequency L*f.sub.s, wherein L=3 (each frequency sample is repeated 3 times). Numerous software and hardware digital implementations are possible for the repeater 124 shown in FIGS. 3A and 3B, and for other similar implementations such as frequency converters and frequency multipliers.

[0035] FIG. 4 shows another embodiment of a digital microphone 200 with internal clock changing, wherein the digital modulator 122 clock rate is constant by placing the digital modulator outside of the digital signal processing circuitry 116B, but inside of ASIC 104B. All other blocks in the digital microphone 200 of FIG. 4 are substantially the same as those previously described and shown in FIG. 1A.

[0036] For optimizing potential residual switching transients, the interpolation stage (repeater 124) can be shifted after the digital filter 120 so that also the digital modulator 122 is always running at a constant rate independent of the clock signal of ADC 118 and digital filter 120 as is shown in FIG. 4. Note that the clock signal for ADC 118 and digital filter 120 is provided by the output of multiplexer 106. Thus, the clock signal is switched between two different values the high performance mode and the low power mode. However, the clock signal for digital modulator 122 is provided directly by the undivided clk signal from clock input 112.

[0037] FIG. 5 shows another embodiment of a digital microphone 300 having multiple repeaters 124A and 124B. Clock divider 108 is set to divide the input clock frequency by a factor of D1. In an example D1=4, and D2=2, while the clock rate at the interface is maintained. In this example the ADC 118 is clocked D1-times lower (4) and the interpolation (upsampling) is done in two steps. The first repeater 124A is upsampling by D1/D2 (by a factor of two) and the second repeater 124B is upsampling by a factor of D2 (also by a factor of two in this example).

[0038] All other blocks in the digital microphone 300 of FIG. 5 are substantially the same as those previously described and shown in FIG. 4. In the embodiment of FIG. 5 the interpolation of the digital output signal at digital output 114 is done in two steps. For example, if D1 is set to four and D2 is set to two, a first repeater 124A performs a first interpolation step, wherein an extra zero is inserted, and the output of first repeater 124A doubles the sample rate (D1/D2=4/2=2). The output of first repeater 124A is coupled to the input of digital modulator 122. A second repeater 124B performs a second interpolation steps, wherein an extra zero is also inserted, and the output of second repeater 124B doubles the sample rate (D2=2). Numerous other examples can be constructed, using different values for D1 and D2. Note that repeaters 124A and 124B are controlled directly by the ctrl control signal from control input 110. In a first mode of operation, determined by the state of the ctrl control signal, repeaters 124A and 124B do not add the additional zeroes and the sample rate is the same at the input and output of the repeaters. In a second mode of operation, determined by the state of the ctrl control signal, repeaters 124A and 124B add additional zeroes by a factor of D1/D2, and D2 respectively. The output sample rate is interpolated by these factors and is not equal to the input sample rate at the input of the repeater. The split repeater embodiment of the digital microphone 300 shown in FIG. 5 is used to further minimize switching artefacts between the low power operating mode and the high performance operating mode.

[0039] FIG. 6 shows another embodiment of a digital microphone 400 having adaptable filter coefficients. FIG. 6 is similar to the previous embodiment of digital microphone 200 shown in FIG. 4, but further details of the digital filter 120 are shown to provide the adaptable filter coefficient function. FIG. 6 thus shows an implementation where the digital filter 120 coefficients are adjusted based on the required performance/clock mode to even further improve the switching transient behavior for a seamless transition. All required filters are designed in a configurable manner so that their properties stay constant under changing clock rate conditions.

[0040] Digital filter 120 is shown in further detail in FIG. 6 including a filter transfer function 152 defined as H(z)=num(z)/den(z), wherein num(z) is the numerator of the filter transfer function 152, and den(z) is the denominator of the filter transfer function 152. A lookup table or memory 154 includes two different numerators num0 and num1, and two different denominators den0 and den1. Since digital filter 120 is under control of the ctrl control signal, num0 and den0 are used in the transfer function in a first mode of operation determined by a first state of the ctrl control signal, and num1 and den1 are used in the transfer function in a second mode of operation determined by a second state of the ctrl control signal.

[0041] FIG. 7A shows a simulated timing diagram of a digital microphone embodiment including a restart delay and 7B shows a simulated timing diagram associated with any of the digital microphone embodiments shown in FIG. 1, 4, 5, or 6. Simulations show that is possible to enable seamless audio switching and reduce audible switching effects as well as transients that are potentially harmful for the following signal chain to a minimum. The transient signal comparison of an embodiment having a restart delay is depicted in FIG. 7A, and an embodiment as shown in FIG. 1, 4, 5, or 6 is shown in FIG. 7B. The digital microphone output signal changes from the low power mode to the high performance mode.

[0042] FIG. 7A thus shows a low power mode output signal 702 followed by a restart delay 704, which is followed by a high performance mode output signal 706. FIG. 7B thus shows the low power mode output signal 702 directly followed by the high performance mode output signal 706. The transition between the two modes is accomplished with a seamless transition and a minimization of switching transients. The output signals of FIGS. 7A and 7B are obtained at output node 114.

[0043] Example embodiments of the present invention are summarized here. Other embodiments can also be understood from the entirety of the specification and the claims filed herein.

[0044] Example 1. According to an embodiment, a method of operating a microelectromechanical system (MEMS) includes, in a first operational mode, converting an analog output of the MEMS into a first internal data stream and a first external data stream having a first sampling rate; transitioning from the first operational mode to a second operation mode without restarting the MEMS; and in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream.

[0045] Example 2. The method of Example 1, wherein the first external data stream and the second external data stream are provided at a one or more output nodes.

[0046] Example 3. The method of any of the previous examples, wherein a sampling rate of the first external data stream and a sampling rate of the second external data stream are equal.

[0047] Example 4. The method of any of the previous examples, wherein performing a sampling rate conversion of the second internal data stream to generate a second external data stream comprises repeating samples in the second internal data stream.

[0048] Example 5. The method of any of the previous examples, wherein converting the analog output of the MEMS comprises performing a sigma-delta analog-to-digital conversion on the analog output of the MEMS.

[0049] Example 6. The method of any of the previous examples, wherein converting the analog output of the MEMS into the first internal data stream is performed by a signal processing circuit clocked at the first sampling rate, and wherein converting the analog output of the MEMS into the second internal data stream is performed by the signal processing circuit clocked at the second sampling rate.

[0050] Example 7. The method of any of the previous examples, wherein the signal processing circuit comprises an analog-to-digital converter (ADC) and a digital filter.

[0051] Example 8. The method of any of the previous examples, further comprising providing a first set of coefficients to the digital filter in the first operational mode and providing a second set of coefficients to the digital filter in the second operational mode.

[0052] Example 9. The method of any of the previous examples, wherein the signal processing circuit further comprises a digital modulator.

[0053] Example 10. The method of any of the previous examples, wherein the signal processing circuit receives an undivided clock signal in the first operational mode and a divided clock signal in the second operational mode.

[0054] Example 11. The method of any of the previous examples, wherein the MEMS comprises a microphone.

[0055] Example 12. According to an embodiment, a circuit includes a clock divider having an input coupled to a clock signal input; a multiplexer having a first input coupled to an output of the clock divider, a second input coupled to the clock signal input, a third input coupled to a control signal input, and an output, wherein the multiplexer couples the first input to the output or couples the second input to the output according to a state of the control signal input; a signal processing circuit having an analog signal input, a clock signal input coupled to the output of the multiplexer, and a digital signal output comprising one or more output nodes; and a frequency converter coupled between the digital signal output of the signal processing circuit and a data stream output, wherein a conversion factor of the frequency converter is determined according to the state of the control signal input.

[0056] Example 13. The circuit of Example 12, wherein the signal processing circuit includes an analog-to-digital converter (ADC) having an input coupled to the analog signal input; a digital filter having an input coupled to an output of the ADC; and a digital modulator having an input coupled to an output of the digital filter and an output coupled to the digital signal output.

[0057] Example 14. The circuit of any of the previous examples, wherein the signal processing circuit comprises: an analog-to-digital converter (ADC) having an input coupled to the analog signal input; and a digital filter having an input coupled to an output of the ADC and an output coupled to the digital signal output.

[0058] Example 15. The circuit of any of the previous examples, further comprising a digital modulator interposed between the frequency converter and the data stream output.

[0059] Example 16. The circuit of any of the previous examples, further comprising an additional frequency converter interposed between the digital modulator and the data stream output.

[0060] Example 17. The circuit of any of the previous examples, wherein the digital filter comprises an additional input for receiving a first set of coefficients or a second set of coefficients according to the state of the control signal input.

[0061] Example 18. The circuit of any of the previous examples, further comprising a microelectromechanical system (MEMS) having an output coupled to the analog signal input of the signal processing circuit.

[0062] Example 19. The circuit of any of the previous examples, wherein the MEMS comprises a microphone.

[0063] Example 20. According to an embodiment, a microelectromechanical (MEMS) circuit in a single package includes a control signal input, a clock signal input, and a data stream output for providing a constant rate single bit output stream at one or more output nodes; a MEMS device; and a signal processing circuit coupled to the MEMS device, to the control signal input, to the clock signal input, and the data stream output, wherein, in a first mode of operation determined by a first state of the control signal input, at least a portion of the signal processing circuit is directly coupled to the clock signal input, and wherein, in a second mode of operation determined by a second state of the control signal input, the at least a portion of the signal processing circuit is coupled to the clock signal input through a clock divider.

[0064] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.