PARTIAL FRAME REPLACEMENT ENABLING MULTIPLE VERSIONS IN AN INTEGRATED VIDEO PACKAGE
20250227326 ยท 2025-07-10
Inventors
Cpc classification
H04N21/8543
ELECTRICITY
H04N21/26258
ELECTRICITY
H04N21/45452
ELECTRICITY
H04N21/440245
ELECTRICITY
H04N21/2353
ELECTRICITY
International classification
H04N21/4402
ELECTRICITY
Abstract
Multiple different versions of media content are contained in a single package of audio-video media content, using compression algorithms that reduce storage and bandwidth required for storing multiple full-resolution versions of the media. Portions of individual frames are replaced during playback so that only the pixels that differ between versions need to be stored.
Claims
1. A computer-implemented method for substituting frame image data, the computer-implemented method comprising: encoding, by one or more processors, an image of a video stream to produce an encoded video frame; defining, by the one or more processors, metadata for the encoded video frame; correlating, by the one or more processors, the metadata to the encoded video frame; and placing, by the one or more processors, the encoded video frame correlated to the metadata in a frame queue.
2. The computer-implemented method of claim 1, wherein encoding the image of the video stream to produce the encoded video frame includes: adding, by the one or more processors, an identifier to the encoded video frame.
3. The computer-implemented method of claim 1, wherein the metadata includes one or more instructions for altering the encoded video frame.
4. The computer-implemented method of claim 1, wherein the metadata includes a substitution image for a region less than an entirety of the encoded video frame.
5. The computer-implemented method of claim 4, wherein the region includes one or more discontinuous sub-regions.
6. The computer-implemented method of claim 4, the computer-implemented method further comprising: decompressing, by the one or more processors, the substitution image; and substituting, by the one or more processors, the region with the decompressed substitution image.
7. The computer-implemented method of claim 6, wherein substituting the decompressed substitution image includes: overwriting, by the one or more processors, at least one pixel of the region with a pixel corresponding to the decompressed substitution image.
8. A computer system for substituting frame image data, the computer system comprising: at least one memory storing instructions; and at least one processor configured to execute the instructions to perform operations comprising: encoding, by the at least one processor, an image of a video stream to produce an encoded video frame; defining, by the at least one processor, metadata for the encoded video frame; correlating, by the at least one processor, the metadata to the encoded video frame; and placing, by the at least one processor, the encoded video frame correlated to the metadata in a frame queue.
9. The computer system of claim 8, wherein encoding the image of the video stream to produce the encoded video frame includes: adding, by the at least one processor, an identifier to the encoded video frame.
10. The computer system of claim 8, wherein the metadata includes one or more instructions for altering the encoded video frame.
11. The computer system of claim 8, wherein the metadata includes a substitution image for a region less than an entirety of the encoded video frame.
12. The computer system of claim 11, wherein the region includes one or more discontinuous sub-regions.
13. The computer system of claim 11, the operations further comprising: decompressing, by the at least one processor, the substitution image; and substituting, by the at least one processor, the region with the decompressed substitution image.
14. The computer system of claim 13, wherein substituting the decompressed substitution image includes: overwriting, by the at least one processor, at least one pixel of the region with a pixel corresponding to the decompressed substitution image.
15. A non-transitory computer-readable medium containing instructions that, when executed by a processor, cause the processor to perform operations for substituting frame image data, the operations comprising: encoding an image of a video stream to produce an encoded video frame; defining metadata for the encoded video frame; correlating the metadata to the encoded video frame; and placing the encoded video frame correlated to the metadata in a frame queue.
16. The non-transitory computer-readable medium of claim 15, wherein encoding the image of the video stream to produce the encoded video frame includes: adding an identifier to the encoded video frame.
17. The non-transitory computer-readable medium of claim 15, wherein the metadata includes one or more instructions for altering the encoded video frame.
18. The non-transitory computer-readable medium of claim 15, wherein the metadata includes a substitution image for a region less than an entirety of the encoded video frame.
19. The non-transitory computer-readable medium of claim 18, wherein the region includes one or more discontinuous sub-regions.
20. The non-transitory computer-readable medium of claim 18, the operations further comprising: decompressing the substitution image; and substituting the region with the decompressed substitution image.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The features, nature, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify like elements correspondingly throughout the specification and drawings.
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DETAILED DESCRIPTION
[0026] Various aspects are now described with reference to the drawings. In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding of one or more aspects. It may be evident, however, that the various aspects may be practiced without these specific details. In other instances, well-known structures and devices are represented in block diagram form to facilitate focus on novel aspects of the present disclosure.
[0027] Referring to
[0028] A metadata document 125, 225 (e.g., in XML or similar format) including the unique metadata and that describes the content versions that can be created may accompany the package, 135, 125. The document may include instructions for processing that describe the original content and the sections of that content where changes need to be made. The document 125, 135 may further contain a map to the files that represent changed portions, information about where and when to place them into the content. The playback software may read the metadata document and overlay the replacement portions into the correct frame and position. The result is that multiple different versions of the main content can be created from the source 115, 215.
[0029] Using the SMTPE Interoperable Mastering Format (IMF) enables replacement of frames in content and create play list style edits for alternate version. The present technology extends the IMF functionality to enable replacement of only a portion of each frame, not an entire frame replacement. In an alternative, a producer may make a video with the pieces to be replaced and then render the rest of the frame as a transparent video (alpha layer). However, the alternative approach requires a player capable of using both video tracks simultaneously lowers bit rate efficiency, besides lacking the essential benefit of reducing the size of the entire package. Thus, an approach like IMF should be advantageous as described in more detail below.
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[0034] The at least one processor may perform additional operations 450 shown in
[0035]
[0036] As illustrated in
[0037] The apparatus or system 500 may further comprise an electrical component 503 for correlating the frame of video data to unique metadata for the frame, wherein the unique metadata defines a substitution image for a region less than an entirety of the frame. The component 503 may be, or may include, a means for said correlating. Said means may include the processor 510 coupled to the memory 516, and to the input device 514, the processor executing an algorithm based on program instructions stored in the memory. Such algorithm may include a sequence of more detailed operations, for example, determining a frame sequence number, and looking up the unique metadata based on an index organized by frame sequence number.
[0038] The apparatus or system 500 may further comprise an electrical component 504 for preparing an altered frame at least in part by substituting the region of the frame with the substitution image. The component 504 may be, or may include, a means for said preparing. Said means may include the processor 510 coupled to the memory 516, the processor executing an algorithm based on program instructions stored in the memory. Such algorithm may include a sequence of more detailed operations, for example, determining a position and size of one or more regions or subregions in the source image loaded into a memory cache, loading a portion of the substitution image corresponding to each of the one or more subregions into a computer memory, overwriting the cached source with the substitution image, and outputting the resulting altered image.
[0039] The apparatus or system 500 may further comprise an electrical component 506 for placing the altered frame in a frame queue of a computer memory instead of the frame, for at least one of play-out or storage. The component 506 may be, or may include, a means for said placing. Said means may include the processor 510 coupled to the memory 516, and to the input device 514, the processor executing an algorithm based on program instructions stored in the memory. Such algorithm may include a sequence of more detailed operations, for example, writing the altered frame in a memory cache, and associating the written frame with a status identifier (implicit or explicit).
[0040] The apparatus 500 may optionally include a processor module 510 having at least one processor, in the case of the apparatus 500 configured as a digital signal processor. The processor 510, in such case, may be in operative communication with the modules 502-506 via a bus 512 or other communication coupling, for example, a network. The processor 510 may initiate and schedule the functions performed by electrical components 502-506.
[0041] In related aspects, the apparatus 500 may include a decoder 514 for decoding a video stream to obtain image data therefrom. The apparatus 500 may further include a network interface module (not shown) operable for communicating with a storage device over a computer network. In further related aspects, the apparatus 500 may optionally include a module for storing information, such as, for example, a memory device/module 516. The computer readable medium or the memory module 516 may be operatively coupled to the other components of the apparatus 500 via the bus 512 or the like. The memory module 516 may be adapted to store computer readable instructions and data for effecting the processes and behavior of the modules 502-506, and subcomponents thereof, or the processor 510, or one or more of the additional operations 450 described in connection with the method 400 or
[0042]
[0043] The at least one processor may perform additional operations 650 shown in
[0044]
[0045] As illustrated in
[0046] Such algorithm may include a sequence of more detailed operations, for example, receiving image data, determining an encoding based an intended output medium, executing the determined encoding algorithm on the input data, and outputting a resulting encoded image as part of (e.g., a frame) of a video file or video data.
[0047] The apparatus or system 700 may further comprise an electrical component 703 for defining unique metadata for the encoded frame comprising a substitution image for a region less than an entirety of the encoded frame. The component 703 may be, or may include, a means for said defining. Said means may include the processor 710 coupled to the memory 716, and to the input device 714, the processor executing an algorithm based on program instructions stored in the memory. Such algorithm may include a sequence of more detailed operations, for example, reading an alteration database for the source video content that defines a position and geometry of the substation image and luminance/color values for each of its pixels, and automatically generating metadata relating the substitution image to the frame and replacement region (including if present discontinuous subregions).
[0048] The apparatus or system 700 may further comprise an electrical component 704 for correlating the unique metadata to the encoded frame. The component 704 may be, or may include, a means for said correlating. Said means may include the processor 710 coupled to the memory 716, the processor executing an algorithm based on program instructions stored in the memory. Such algorithm may include a sequence of more detailed operations, for example, determining a frame identifier for the current frame of the source video and generating a document, file, or other data structure containing the metadata indexed to a frame identifier for the current frame (repeating these operations for each frame).
[0049] The apparatus or system 700 may further comprise an electrical component 706 for placing the frame of video data correlated to the unique metadata in frame queue of a computer memory for later decoding and play-out. The component 706 may be, or may include, a means for said placing. Said means may include the processor 710 coupled to the memory 716, and to the input device 714, the processor executing an algorithm based on program instructions stored in the memory. Such algorithm may include a sequence of more detailed operations, for example, compiling the sequence of frames from a frame queue into a document or file, verifying that each frame to be altered in the version has a unique metadata in the metadata structure indexed to a relevant frame of the source video, and including the source video and metadata structure in a package according to a predetermined order or arrangement of data elements.
[0050] The apparatus 700 may optionally include a processor module 710 having at least one processor, in the case of the apparatus 700 configured as a digital signal processor. The processor 710, in such case, may be in operative communication with the modules 702-706 via a bus 712 or other communication coupling, for example, a network. The processor 710 may initiate and schedule the functions performed by electrical components 702-706.
[0051] In related aspects, the apparatus 700 may include an encoder 714 for encoding a succession of images as video data. The apparatus may include a network interface device (not shown) operable for communicating with a storage device over a computer network. In further related aspects, the apparatus 700 may optionally include a module for storing information, such as, for example, a memory device/module 716. The computer readable medium or the memory module 716 may be operatively coupled to the other components of the apparatus 700 via the bus 712 or the like. The memory module 716 may be adapted to store computer readable instructions and data for effecting the processes and behavior of the modules 702-706, and subcomponents thereof, or the processor 710, or one or more of the additional operations 650 described in connection with the method 600 or
[0052] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. For example both apparatus 500, 700 may be combined in a single apparatus 300 depicted above.
[0053] As used in this application, the terms component, module, system, and the like are intended to refer to a computer-related entity, either hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer or system of cooperating computers. By way of illustration, both an application running on a server and the server can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers.
[0054] Various aspects will be presented in terms of systems that may include several components, modules, and the like. It is to be understood and appreciated that the various systems may include additional components, modules, etc. and/or may not include all the components, modules, etc. discussed in connection with the figures. A combination of these approaches may also be used. The various aspects disclosed herein can be performed on electrical devices including devices that utilize touch screen display technologies and/or mouse-and-keyboard type interfaces. Examples of such devices include computers (desktop and mobile), smart phones, personal digital assistants (PDAs), virtual reality or augmented reality headgear, and other electronic devices both wired and wireless.
[0055] In addition, the various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
[0056] Furthermore, the one or more versions may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques to produce software, firmware, hardware, or any combination thereof to control a computer to implement the disclosed aspects. Non-transitory computer readable media can include but are not limited to magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips . . . ), optical disks (e.g., compact disk (CD), digital versatile disk (DVD), BluRay . . . ), smart cards, solid-state devices (SSDs), and flash memory devices (e.g., card, stick). Of course, those skilled in the art will recognize many modifications may be made to this configuration without departing from the scope of the disclosed aspects.
[0057] The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be clear to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
[0058] In view of the exemplary systems described supra, methodologies that may be implemented in accordance with the disclosed subject matter have been described with reference to several flow diagrams. While for purposes of simplicity of explanation, the methodologies are shown and described as a series of blocks, it is to be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in different orders and/or concurrently with other blocks from what is depicted and described herein. Moreover, not all illustrated blocks may be required to implement the methodologies described herein. Additionally, it should be further appreciated that the methodologies disclosed herein are capable of being stored on an article of manufacture to facilitate transporting and transferring such methodologies to computers.