Passivation for a semiconductor light emitting device

Abstract

In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.

Claims

1. A method comprising: providing a semiconductor structure comprising an active region between an n-type region and a p-type region, the semiconductor structure being divided into a plurality of light-emitting devices (LEDs) separated by a gap between adjacent LEDs of the plurality of LEDs; removing a portion of the p-type region and the active region in the gap to form a first exposed surface region of the n-type region and in a region adjacent the gap to form a second exposed surface region; disposing a dielectric layer at least directly on the first exposed surface region; disposing an underfill in areas between the semiconductor structure and a mount at least directly on a portion of the dielectric layer and the second exposed surface region; and attaching the semiconductor structure to the mount.

2. The method of claim 1, wherein the dielectric layer improves adhesion of the underfill to the first exposed surface region in the gap.

3. The method of claim 1, wherein the dielectric layer comprises at least one of AlN, TiN, SiO.sub.2, SiN.sub.xO.sub.y, SiN.sub.x, and Si.sub.3N.sub.4.

4. The method of claim 1, further comprising: forming a p-contact on the p-type region; and forming a guard layer on the p-contact.

5. The method of claim 1, wherein the disposing the underfill material is performed one of before, during or after the attaching the semiconductor structure to the mount.

6. The method of claim 1, wherein the attaching the semiconductor structure to the mount comprises at least one of ultrasonic bonding, thermosonic bonding or thermocompression bonding of a bond layer on the semiconductor structure to a bond layer on the mount.

7. The method of claim 1, wherein the gap is between 1 and 10microns wide.

8. The method of claim 1, wherein the disposing the underfill material comprises: depositing a solid layer of a dielectric material on at least one of the semiconductor structure or the mount; and patterning the solid layer.

9. The method of claim 1, wherein the disposing the underfill material comprises injecting the underfill material between the semiconductor structure and the mount.

10. The method of claim 9, wherein the underfill material is one of silicone or epoxy.

11. A method comprising: providing a semiconductor structure comprising an active region between an n-type region and a p-type region, the semiconductor structure being divided into a plurality of light-emitting devices (LEDs) separated by a gap between adjacent LEDs of the plurality of LEDs and comprising an n-contact on an exposed portion of the n-type region; removing a portion of the p-type region and the active region in the gap to form an exposed surface region of the n-type region; disposing a passivation layer on the semiconductor structure, including over an outer side of the n-contact and on top of the exposed portion of the n-type region in the gap; and attaching the semiconductor structure to a mount.

12. The method of claim 11, further comprising: forming a p-contact on the p-type region; and forming a guard layer on the p-contact.

13. The method of claim 11, further comprising forming a metal bonding layer coupled to the exposed portion of the n-type region.

14. The method of claim 13, wherein the disposing the passivation layer on the semiconductor structure further comprises disposing the passivation layer on a bottom surface of the metal bonding layer.

15. The method of claim 14, forming one or more openings in the passivation layer.

16. The method of claim 15, wherein the disposing the passivation layer comprises patterning the passivation layer to form the one or more openings.

17. The method of claim 15, wherein the attaching the semiconductor structure to the mount comprises at least one of ultrasonic bonding, thermosonic bonding or thermocompression bonding of the metal bonding layer in the one or more openings to a bond layer on the mount.

18. The method of claim 11, wherein the passivation layer comprises at least one of AlN, TiN, SiO.sub.2, SiN.sub.xO.sub.y, SiN.sub.x, or Si.sub.3N.sub.4.

19. The method of claim 11, wherein the disposing the passivation layer comprises at least one of sputtering, e-beam evaporation, CVD, or PECVD.

20. The method of claim 1, wherein the disposing the passivation layer comprises: at least one of spin-coating or dip-coating the semiconductor structure with precursor materials; and curing the precursor materials to form a high density insulating dielectric.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a portion of a wafer of flip chip light emitting devices with a dielectric layer disposed in a street between adjacent devices (adjacent devices are not shown).

(2) FIG. 2 illustrates a portion of a wafer of flip chip light emitting devices with a dielectric layer disposed over a bonding metal and in a street between adjacent devices (adjacent devices are not shown).

(3) FIG. 3 illustrates portion of a wafer of flip chip light emitting devices with a reflective dielectric stack disposed in a street between adjacent devices (adjacent devices are not shown).

DETAILED DESCRIPTION

(4) Though in the examples below the semiconductor light emitting device is a III-nitride LED that emits blue or UV light, semiconductor devices besides LEDs such as laser diodes and semiconductor devices made from other materials systems such as other III-V materials, III-phosphide, III-arsenide, II-VI materials, or Si-based materials may be used.

(5) FIG. 1 illustrates a portion of a wafer of thin film flip chip light emitting devices. To form the structure illustrated in FIG. 1, first a semiconductor structure 20 is grown over a growth substrate. The semiconductor structure 20 includes a light emitting or active region 24 sandwiched between n- and p-type regions 22 and 26. An n-type region 22 is typically grown first over the growth substrate and may include multiple layers of different compositions and dopant concentration including, for example, preparation layers such as buffer layers or nucleation layers, which may be n-type or not intentionally doped, and n- or even p-type device layers designed for particular optical or electrical properties desirable for the light emitting region to efficiently emit light. A light emitting or active region 24 is grown over the n-type region 22. Examples of suitable light emitting regions include a single thick or thin light emitting layer, or a multiple quantum well light emitting region including multiple thin or thick light emitting layers separated by barrier layers. A p-type region 26 is grown over the light emitting region 24. Like the n-type region 22, the p-type region 26 may include multiple layers of different composition, thickness, and dopant concentration, including layers that are not intentionally doped, or n-type layers.

(6) One or more p-contact metals 28, such as, for example, silver, is deposited on the p-type region 26, then portions of the p-type region and active region are etched away to expose a portion 35 of an n-type layer on which an n-contact 40 is later formed. The p-contact 28 may be sealed by one or more guard layers 30 and 32 disposed beside and over p-contact 28. Guard layers 30 and 32 may be, for example, a dielectric layer with openings that expose p-contact 28 or, as illustrated in FIG. 1, one or more metal layers such as TiW. One or more dielectric layers 34, such as, for example, Si.sub.3N.sub.4 formed by, for example, plasma enhanced chemical vapor deposition (PECVD) is disposed over guard layer 30 to electrically isolate the conductive structure connected to the p-type region (including p-contact 28 and guard layers 30 and 32) and the n-contact 40. Openings are formed in dielectric layer 34 in the regions 35 where n-contact 40 electrically contacts n-type region 22, then the n-contact metal 40, such as, for example, aluminum, is formed. A bonding metal 42, such as, for example, gold, is formed over n-contact 40 to facilitate bonding each device to a mount 56 and electrical contact with the mount.

(7) The p-contact 28 and n-contact 40 are formed on the same side of the semiconductor structure. In some embodiments either or both the n-contact 40 and the p-contact 28 are reflective and the device is mounted such that light is extracted through the top of the device in the orientation illustrated in FIG. 1. In some embodiments, the contacts may be limited in extent or made transparent, and the device may be mounted such that light is extracted through the surface on which the contacts are formed.

(8) The wafer of devices is attached to a mount 56, for example by ultrasonic bonding, thermosonic bonding, or thermocompression bonding of bonding layer 42 to a bonding layer (not shown in FIG. 1) formed on mount 56. Before, during, or after attaching wafer 10 to mount 56, an underfill 58 is disposed in any areas between the semiconductor device wafer 10 and mount 56 where the semiconductor device wafer 10 is not supported by the bonding layers. The underfill 58 may be, for example, a dielectric layer or other solid layer that is deposited on wafer 10 or mount 56 and patterned, or a material such as silicone, epoxy, or any other suitable material that is injected between wafer 10 and mount 56 after bonding then cured into a solid. Underfill 58 supports wafer 10 during processing and operation of the semiconductor devices, in particular during removal of the growth substrate. For example, a sapphire substrate may be removed by shining a laser through the substrate to melt a layer of semiconductor material in direct contact with the substrate, a process that may create stress in the semiconductor structure. In some embodiments, the semiconductor layer exposed by removing the growth substrate is patterned or roughened, which may improve light extraction from the device. In some embodiments, the growth substrate may remain part of the device.

(9) As illustrated in FIG. 1, in an area 36 between two devices, known as a “street,” a portion 38 of dielectric layer 34 described above is left. As illustrated in FIG. 1, the portion 38 of dielectric layer 34 in the street is disposed over an etched surface of the semiconductor structure 20; i.e., the surface of n-type region 22 exposed by etching a mesa. The street may be, for example, between 1 and 10 microns wide and is often about five microns wide. The street is cut, for example by sawing, by laser scribing, or by laser scribing and breaking, to singulate the wafer into individual dice. The wafer may be diced, for example, after a wafer of devices is attached to a wafer of mounts, or before attaching to the mount. Dielectric portion 38 may improve adhesion of underfill 58 to wafer 10, particularly at the interface between semiconductor material (n-type region 22) and underfill 58. Improving the adhesion of the underfill to the wafer may improve the reliability of the semiconductor devices by forming a seal that prevents contaminants from reaching the device, and may reduce damage or avoid failure caused by insufficient support of wafer 10.

(10) FIG. 2 illustrates a portion of a wafer of thin film flip chip light emitting devices. The structure illustrated in FIG. 2 includes a passivation layer 44. Semiconductor structure 20 is grown, then p-contact 28, guard layers 30 and 32, dielectric 34, n-contact 40, and bonding layer 42 are formed and patterned as described above in reference to FIG. 1. Passivation layer 44 is deposited over bonding layer 42. Passivation layer 44 may be any suitable material such as, for example, an insulating or dielectric layer, AlN, TiN, SiO.sub.2, SiN.sub.xO.sub.y, SiN.sub.x, or Si.sub.3N.sub.4, formed by, for example, any suitable method including sputtering, e-beam evaporation, CVD, PECVD, or spin-coating or dip-coating the structure with appropriate precursor materials, then curing the precursor materials to form a high density insulating dielectric. Passivation layer 44 may be a single layer or a multi-layer structure. Passivation layer 44 is patterned by conventional photolithography techniques to form one or more openings 46 which allow the structure to be connected to a mount (not shown in FIG. 2) by, for example, attaching bonding layer 42 to a bonding layer formed on a mount, as described above in reference to FIG. 1. Passivation layer 44 may be left in streets 36 between adjacent devices.

(11) Passivation layer 44 covers the device, except in areas where conductive paths are required for attaching to electrodes on the mount. Passivation layer 44 seals the side of the device by coating the side of bonding layer 42 and n-contact 40. In the areas where it is formed, passivation layer 44 passivates the structure by protecting the device from corrosion, etching, oxidation, and other processes that may damage the device during operation or processing. For example, passivation layer 44 may reduce or prevent the intrusion of corrosive species such as water vapor, which may improve the performance of the device and/or reduce failure rates. In some embodiments, the thickness of passivation layer 44 is selected to reflect any light emitted by active region 24 that may be incident on passivation layer 44. Passivation layer 44 may improve the adhesion of an underfill to the wafer, as described above in reference to FIG. 1.

(12) In FIG. 3, the passivation layer 44 of FIG. 2 is replaced by a multilayer dielectric stack 48. Multilayer dielectric stack 48 may include several pairs of alternating layers of two materials 50 and 52 with different refractive indices. Examples of suitable materials include, for example, SiN.sub.x, Si.sub.3N.sub.4 and SiO.sub.2 formed by, for example, the techniques described above for forming passivation layer 44 of FIG. 2, or any other suitable technique. Materials 50 and 52 are selected to form a stack 48 that reflects any light from active region 24 that is incident on stack 48. Openings 54 are formed in stack 48 where necessary for electrical and/or physical contact to bonding layer 42. Multilayer stack 48 may improve the adhesion of an underfill to the wafer, as described above in reference to FIG. 1.

(13) In some embodiments, as illustrated in FIG. 3, in or adjacent to street 36, all or a portion 35 of the semiconductor structure remaining after the mesa etch may be removed to expose the growth substrate (not shown in FIG. 3). The passivation layer (underfill 58 in FIG. 1, passivation layer 44 in FIG. 2, and stack 48 in FIG. 3) may extend over the side of the semiconductor structure where the entire thickness of the semiconductor structure 20 is removed, as illustrated in FIG. 3. Extending the passivation layer over the edge of semiconductor structure 20 may further improve passivation of the structure and extraction from the device, by reflecting light incident on the interface between n-type region 22 and stack 48.

(14) Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.