Semiconductor apparatus for image transmission

Abstract

A video input interface receives input video data in a normal state. A control input interface receives character data for On Screen Display (OSD) in a setup state. An encoder encodes the character data and stores encoded compressed data in a memory in the setup state. A decoder receives an instruction signal designating the character data to be displayed, reads and decodes one piece of compressed data corresponding to the instruction signal from the memory, and reproduces the original character data in the normal state. A multiplexer superimposes character data on frame data and outputs the data.

Claims

1. A timing controller comprising: a video input interface structured to receive input video data via a differential serial interface; a memory structured to store reference character data describing a predetermined character that can be contained in the input video data; an image processing circuit structured to generate output video data to be displayed on a display panel based on the input video data; an abnormality detector structured to determine whether or not there is an abnormality based on the input video data and the reference character data; and an output interface to be coupled to a gate driver and a source drive in the display panel and structured to control the gate driver and the source driver based on the output video data, wherein the semiconductor apparatus is monolithically integrated on a single semiconductor substrate.

2. The timing controller according to claim 1, further comprising: a control input interface provided separately from the video input interface to enable communication with an outside processor.

3. The timing controller according to claim 2, wherein a display position of the predetermined character is variable, and wherein a control signal that the control input interface receives from the processor contains positional information indicating the display position of the predetermined character.

4. The timing controller according to claim 1, wherein the predetermined character is arranged in a fixed manner at a predetermined position in a user-unrecognizable state.

5. The timing controller according to claim 2, wherein a control signal that the control input interface receives from the processor contains at least either information indicating whether or not the predetermined character is targeted for determination by the abnormality detector or information indicating whether or not a current frame is targeted for determination by the abnormality detector.

6. The timing controller according to claim 1, wherein the semiconductor apparatus is structured to support an OSD function, and wherein the memory has stored therein character data for the OSD, and wherein the image processing circuit superimposes the character data for the OSD on the input video data in an OSD mode.

7. The timing controller according to claim 6, wherein the reference character data and the character data for the OSD are used in common.

8. The timing controller according to claim 6, wherein the OSD mode and a determination mode in which determination is given by the abnormality detector are selectable.

9. The timing controller according to claim 1, wherein the memory is a non-volatile memory.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which:

(2) FIG. 1 is a block diagram of an image display system;

(3) FIG. 2 is a block diagram of a timing controller according to a first embodiment;

(4) FIG. 3 describes run-length compression of character data;

(5) FIG. 4 illustrates a state in which compressed data is stored in a memory;

(6) FIG. 5A to FIG. 5C illustrate data structures of same-color segments;

(7) FIG. 6 illustrates compression ratios of the same-color segments when a second data structure in FIG. 5B is employed;

(8) FIG. 7 illustrates a display panel on which two pieces of character data are displayed;

(9) FIG. 8A to FIG. 8C illustrate an in-vehicle display device using the timing controller;

(10) FIG. 9 is a perspective view illustrating an electronic device;

(11) FIG. 10 is a block diagram of an image display system including a timing controller according to a second embodiment;

(12) FIG. 11 illustrates an example of a predetermined character;

(13) FIG. 12A and FIG. 12B illustrate abnormality detection by means of the timing controller;

(14) FIG. 13 is a block diagram of an image display system including a timing controller according to an embodiment;

(15) FIG. 14 is a block diagram of the image display system including a timing controller according to an embodiment; and

(16) FIG. 15 illustrates the display panel on which two pieces of character data are displayed.

DETAILED DESCRIPTION OF THE INVENTION

(17) The invention will now be described based on preferred embodiments which do not intend to limit the scope of the present invention but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention.

(18) In the present description, “a state in which a member A is connected to a member B” includes a case in which the member A and the member B are connected physically directly and a case in which the member A and the member B are connected indirectly via another member which has no substantial effect on the electric connection state between the members or which does not impair a function and an effect obtained by the connection between the members.

(19) Similarly, “a state in which a member C is provided between a member A and a member B” includes a case in which the member A and the member C, or the member B and the member C, are connected directly and a case in which the member A and the member C, or the member B and the member C, are connected indirectly via another member which has no substantial effect on the electric connection state between the members or which does not impair a function and an effect obtained by the connection between the members.

First Embodiment

(20) FIG. 2 is a block diagram of a timing controller 300 according to a first embodiment. In a similar manner to that in the image display system 100R in FIG. 1, the timing controller 300 receives input video data S.sub.1 from a graphic controller 110, supplies output video data S.sub.2 to one or a plurality of source driver(s) 106, and outputs a control/synchronous signal S.sub.3 to a gate driver 104 and one or the plurality of source driver(s) 106. The timing controller 300 may be a functional integrated circuit (IC) integrated on one semiconductor substrate.

(21) The timing controller 300 includes a video input interface 302, a memory 304, a main logic 306, an output interface 308, a control input interface 310, and an OSD processor 320.

(22) The video input interface 302, the main logic 306, and the output interface 308 are circuit blocks related to display of image data from the graphic controller 110 and may be the same as those included in the conventional timing controller 200R. The video input interface 302 is connected to the graphic controller 110 via a first line 112 and receives the input video data S.sub.1. As an interface between the video input interface 302 and the graphic controller 110, a differential high-speed serial interface such as a low voltage differential signaling (LVDS) can be employed. The input video data S.sub.1 received by the video input interface 302 is stored as frame data S.sub.4 in the memory 304. The memory 304 may be a static random access memory (SRAM) without limitation.

(23) The main logic 306 performs various kinds of signal processing to the frame data S.sub.4. The signal processing of the main logic 306 is not particularly limited, and a known technique may be used such as γ (gamma) correction, frame rate control (FRC) processing, and RGB mapping. The output interface 308 outputs the output video data S.sub.2 processed by the main logic 306 to the source driver 106. The main logic 306 also generates the control/synchronous signal S.sub.3 that is to be supplied to the gate driver 104 and the source driver 106.

(24) The control input interface 310, the OSD processor 320, and a multiplexer 330 are provided in relation to an OSD function.

(25) The timing controller 300 is in a setup state immediately after turning on the power. For example, the timing controller 300 has a period for setting parameters and the like of the γ correction and the RGB mapping (initializing period) at the time of the power-on as a previous stage to reception and output of the video input data to a panel. A part of the initializing period may be regarded as the setup state.

(26) Alternatively, giving a command from an outside to the timing controller 300 may enable the setup state to be set. For example, a register associated with the setup state may be provided inside a timing controller 300a, and 1 may be written in the register from the outside (for example, a processor 114) to shift a state to the setup state. In this case, the state can be shifted to the setup state not only immediately after turning on the timing controller 300 but also at an arbitrary time.

(27) The control input interface 310 receives character data S.sub.5 for On Screen Display (OSD) from the processor 114 in the setup state. The character data S.sub.5 is stored in a non-volatile memory 118 and is transmitted via the processor 114 to the control input interface 310. The character data S.sub.5 may be monochrome or colored bitmap data without limitation. Also, the representation form of the character data S.sub.5 is an arbitrary form such as icons, graphics, and characters. As the control input interface 310, a register-access-type interface can be used. Favorable examples thereof include, but are not limited to, a serial peripheral interface (SPI) and an inter-integrated circuit (I.sup.2C) interface. Although FIG. 2 illustrates a configuration in which the processor 114 is provided separately from the graphic controller 110, the function of the processor 114 may be incorporated into the graphic controller 110.

(28) The OSD processor 320 includes an encoder 322 and a decoder 324. In the setup state, the encoder 322 encodes the character data S.sub.5 and stores encoded compressed data S.sub.6 in the memory 304. Also, address information S.sub.7 representing an address at which the compressed data S.sub.6 has been stored is stored to correspond to the character data S.sub.5.

(29) In the setup state, a plurality of pieces of character data S.sub.5 may be input. In this case, an ID may be given to each piece of character data S.sub.5, correspond to the compressed data S.sub.6 and the address information S.sub.7, and be stored in the memory 304.

(30) In a normal state, the control input interface 310 receives an instruction signal S.sub.8 containing an ID designating character data to be displayed. The decoder 324 refers to the address information S.sub.7 corresponding to the ID and reads from the memory 304 and decodes a piece of compressed data S.sub.6 corresponding to the ID information to reproduce original character data S.sub.9.

(31) The multiplexer 330 superimposes the character data S.sub.9 on frame data S.sub.10 output from the main logic 306 and outputs the data to the output interface 308.

(32) A position at which the character data S.sub.9 is to be displayed is preferably controllable. The instruction signal S.sub.8 may contain positional information POS designating the position at which the character data S.sub.9 is to be displayed. The multiplexer 330 displays the character data S.sub.9 at the position corresponding to the positional information POS.

(33) The entire configuration of the timing controller 300 has been described above. Next, compression of the character data S.sub.5 will be described. For compression of the character data S.sub.5, run-length compression can be used.

(34) FIG. 3 describes run-length compression of the character data S.sub.5. Although the character data of 7×6 pixels is illustrated in FIG. 3 to simplify the description, actual character data may contain 50×50 pixels, 100×100 pixels, or as many pixels as another number. Also, the number of pixels in the vertical direction and the number of pixels in the horizontal direction may differ.

(35) In the run-length compression, consecutive pixels having the same color (referred to as a same-color segment) are converted into color data CD and a run-length value RL representing a value for the consecutive number. In the run-length compression, pixels are processed from the upper line to the lower line, and in each line, from the left end to the right end. Each of the arrows in FIG. 3 represents a same-color segment SEG.

(36) The color data CD can be represented by 24 bits consisting of 8 bits of each of R, G, and B.

(37) The character data S.sub.5 in FIG. 3 is divided into five same-color segments SEG.sub.1 to SEG.sub.5. The run-length values RL of the respective same-color segments SEG.sub.1 to SEG.sub.5 are 17, 2, 5, 2, and 16. The same-color segments SEG.sub.1, SEG.sub.3, and SEG.sub.5 have a first color while the same-color segments SEG.sub.2 and SEG.sub.4 have a second color. Accordingly, the compressed data S.sub.6 corresponding to one piece of character data S.sub.5 can be represented by one piece of segment data SEG or a combination of a plurality of pieces of segment data SEG.

(38) FIG. 4 illustrates a state in which compressed data COMP (S.sub.6) is stored in the memory 304. First compressed data COMP.sub.1 contains M pieces of segment data representing M same-color segments, second compressed data COMP.sub.2 contains N pieces of segment data, and third compressed data COMPS contains K pieces of segment data. An initial address of each piece of compressed data COMP is stored as address information ADR in the memory 304.

(39) A size (the number of pixels) of the character data S.sub.5 may be fixed to 50 pixels×50 pixels, for example. However, to provide additional flexibility, the size may be selectable from a plurality of options by a user. For example, the timing controller 300 may be configured to support two sizes of 50×50 pixels and 100×100 pixels. In this case, in the setup state, size data SIZE designating the size may be input as well as the character data S.sub.5. The size data SIZE is stored in the memory 304 to correspond to the ID of the character data S.sub.5.

(40) To provide additional flexibility, the user may be able to designate the size of the character data S.sub.5 freely. For example, in the setup state, the size data SIZE may be input to designate the number of vertical pixels and the number of horizontal pixels, as well as the character data S.sub.5. The size data is stored in the memory 304 to correspond to the ID of the character data S.sub.5.

(41) FIG. 5A to FIG. 5C illustrate data structures of the same-color segments SEG. FIG. 5A illustrates a first data structure. Data of each same-color segment SEG (segment data) contains one or a plurality of set(s) SET of a color word CW and a run-length word RLW.

(42) In a case in which the number of bits of the run-length word RLW is 3, and in which the consecutive number (run-length value) is never zero, run-length words RLW <000> to <111> can represent run-length values 1 to 8.

(43) In a case in which the run-length value RL is 8 or less as in the case of the same-color segment SEG.sub.2 (SEG.sub.3 or SEG.sub.4), the compressed data thereof is represented by one set SET.sub.1 containing one color word CW and one run-length word RLW as illustrated in FIG. 5A.

(44) In a case in which the run-length value RL of a same-color segment SEG is 9 or more, the same-color segment SEG contains a plurality of sets each having the same color data CD. For example, in a case of the same-color segment SEG′ whose run-length value RL is 17, the consecutive number is divided into 16 and 1. That is, the same-color segment SEG.sub.1 is represented by two sets SET.sub.1 and SET.sub.2. In the two sets SET.sub.1 and SET.sub.2, the color words CW are the same, and the run-length word RLW of the first set is <111> while the run-length word RLW of the second set is <011>.

(45) In a case in which the run-length value RL is 17 to 24, the consecutive number can be divided into 8+8+a (where 1≤a≤8), and the same-color segment SEG can contain three sets SET.

(46) Meanwhile, although the number of bits for each word is 3 here to facilitate understanding, the number is not limited to this and may be 4 to 6 bits or so. The optimal number of bits for each word may be determined to have a high compression ratio in consideration of the shape and the size of the character data.

(47) FIG. 5B illustrates a second data structure. In the second data structure, the format length of the run-length value RL is variable.

(48) At the top of each of the color word CW and the run-length word RLW, a separator bit representing a boundary of the same-color segment SEG is provided. In the example in FIG. 5B, the separator bit is a termination bit TB representing a termination of the same-color segment, and the value 1 represents the termination. The separator bit may represent a start point instead of the termination.

(49) The same-color segment whose run-length value RL is 1 may contain only the color word CW whose termination bit TB is 1 and no run-length word RLW. This enables the compression ratio to be further raised. In this case, the 4-bit run-length words RLW <0000> to <1111> can represent run-length values 2 to 17.

(50) For example, in a case in which the character data represents characters, anti-aliasing may be provided to display a smooth font, and the same-color segment whose run-length value RL is 1 tends to be generated. By dispensing with the run-length word RLW to represent “run-length value RL=1,” the compression ratio especially in the case of the characters can be raised.

(51) In a case in which “termination bit TB=1” is added to the second run-length word RLW, the run-length value is represented by 2 words and 8 bits. For example, the first run-length word RLW may be allocated to the low 4 bits while the second run-length word RLW may be allocated to the high 4 bits, and vice versa. The 8-bit run-length values RL <00000000> to <11111111> obtained by combining the two run-length words RLW represent run-length values 2 to 257.

(52) Meanwhile, by allocating the precedent run-length word RLW to the low bits of the run-length value, at the time of decoding, a pixel group corresponding to the run-length value RL represented by the precedent run-length word RLW can be marked (or rasterized) before the subsequent run-length word RLW is read out.

(53) In a case in which “termination bit TB=1” is added to the third run-length word RLW, the run-length value RL is represented by 3 words and 12 bits.

(54) In the first data structure in FIG. 5A, since each set SET contains the color word CW of the same value, this is redundant, and the compression ratio may be lowered. Conversely, in the second data structure, since there is no redundancy of the color word CW, the compression ratio can be raised.

(55) FIG. 5C illustrates a third data structure. In the third data structure, as well as in the second data structure, the format length of the run-length value RL is variable. In the third data structure, the segment data does not contain the termination bit TB for each word but contains a bit WB designating the number of words of the run-length value RL (word number designation bit). Although the number of bits of the word number designation bit WB is not particularly limited, the number of bits is 2 in this example. In a case in which the run-length value RL is 2 to 17, the word number designation bit WB is 1 (<01> in a case of a binary number), and the segment data contains one run-length word RLW. In a case in which the run-length value RL is 2 to 257, the word number designation bit WB is 2 (<10> in a case of a binary number), and the segment data contains two run-length words RLW. The initial run-length word RLW may represent the low 4 bits of the run-length value RL while the second run-length word RLW may represent the high 4 bits of the run-length value RL.

(56) In the second data structure in FIG. 5B, since the total number of termination bits TB increases as the number of words of the run-length value increases, the compression ratio tends to be lowered. Conversely, in the third data structure, even when the number of words of the run-length value increases, the bit number of the word number designation bit WB is constant, and the compression ratio can thus be restricted from being lowered. Meanwhile, the second data structure or the third data structure may be selected to have a high compression ratio in consideration of the shape and the size of the character data.

(57) As another data structure, the following structure is considered. For example, in the second or third data structure, the sum of the plurality of run-length words RLW may be the run-length value RL in a similar manner to that of the first data structure. For example, in a case in which the segment data contains two run-length words RLW whose values are <0001> and <1111>, the run-length value RL may be 3+17=20.

(58) The configuration of the timing controller 300 has been described above. Next, an operation thereof will be described.

1. Setup State

(59) When a device or a system including the timing controller 300 is activated, the timing controller 300 is in a setup state. The processor 114 transmits the character data S.sub.5 as well as the size data SIZE to the control input interface 310. The encoder 322 compresses the received character data S.sub.5 and stores the compressed data S.sub.6 in the memory 304. In a case in which there are a plurality of pieces of character data S.sub.5, the plurality of pieces of character data are compressed sequentially.

2. Normal State

(60) The graphic controller 110 transmits the input video data S.sub.1 via the first line 112 to the video input interface 302. The timing controller 300 processes the input video data S.sub.1 and controls the gate driver 104 and the source drivers 106 to display an image on the display panel.

(61) In a case in which a character is to be displayed on the display panel with use of the OSD function, the processor 114 transmits the instruction signal S.sub.8 separately from the input video data S.sub.1. The instruction signal S.sub.8 contains the ID information designating one of the plurality of pieces of character data S.sub.5 transmitted to the timing controller 300 in the setup state and the positional information POS designating a display position.

(62) The decoder 324 refers to the address information S.sub.7 corresponding to the ID information and accesses the corresponding compressed data S.sub.6. The decoder 324 then decodes the compressed data S.sub.6 based on the size data SIZE to extract the character data S.sub.9 in a bitmap format. The multiplexer 330 displays the character data S.sub.9 at a position designated by the positional information POS. FIG. 7 illustrates the display panel 102 on which two pieces of character data S.sub.91 and S.sub.92 are displayed.

(63) The multiplexer 330 may substitute the luminance value of the frame data S.sub.10 at a region at which the character data S.sub.9 is arranged with the luminance value of the character data S.sub.9.

(64) The operation of the timing controller 300 has been described above. Next, advantages thereof will be described.

(65) Since the encoder and the decoder for the character data for the OSD are incorporated in the timing controller 300, and the character data S.sub.5 is given each time the timing controller 300 is in the setup state, various kinds of character data can be displayed.

(66) Also, since the character data is stored in the memory 304 in a compressed form, the capacity of the memory 304 can be reduced, which leads to cost reduction. FIG. 6 illustrates the compression ratios of the same-color segments when the second data structure in FIG. 5B is employed. Here, the bit wide of the run-length word RLW is 4 bits. As the run-length value RL is higher, the higher compression ratio is obtained. In a case in which the run-length value is 1 or 2, the segment data is larger than the data volume of the original pixel data. However, in most of characters, icons, and graphics, the run-length value is 1 or 2 only in a case of anti-aliasing or the like, and the probability of occurrence thereof is extremely low. Accordingly, the compression ratio of the entire character data can sufficiently be raised.

(67) Also, while the ROM 111 storing the character data for the OSD is required to be provided on the side of the timing controller 200R in FIG. 1, the character data is not required to be stored in the ROM in the timing controller 300 in FIG. 2. Since the memory 304 such as an SRAM is more reasonable than the ROM, the cost can be reduced.

(68) In the system in FIG. 1, an OTP (one time programmable) ROM is used for the ROM 111. Hence, in a case in which the character data for the OSD is to be changed or added, the ROM 111 is required to be replaced. However, in many cases, it is impossible to replace the ROM, or even when it is possible, the cost will be extremely high.

(69) In many systems, to the processor 114 is connected not the one time ROM but the rewritable non-volatile memory 118 such as a hard disk, a solid state drive (SSD), an electrically erasable programmable read-only memory (EEPROM), and a flash memory. Accordingly, in the timing controller 300 in FIG. 2, the character for the OSD can be changed or added by changing or adding the character data stored in the non-volatile memory 118.

(70) Next, use of the timing controller 300 will be described. FIG. 8A illustrates an in-vehicle display device 600 using the timing controller 300. The in-vehicle display device 600 is buried in a console 602 on the cockpit front face. The in-vehicle display device 600 receives from the vehicle processor and displays the input video data S.sub.1 including a speed meter 604, a tachometer 606 indicating the number of revolutions of the engine, a fuel remaining amount 608, and, in a case of a hybrid car or an electric car, a remaining amount of a battery (FIG. 8A).

(71) Conventionally, an indicator lamp or a warning lamp (hereinbelow referred to simply as a warning lamp) indicating a certain abnormality or a dead battery as illustrated in FIG. 8B is displayed outside the display panel with use of an independent LED. The reason for not displaying the warning lamp on the display panel is as follows. That is, the timing controller 300 and the graphic controller 110 are connected by means of a differential serial interface. During a period from start of activation of the system to establishment of a link between the timing controller 300 and the graphic controller 110 by means of the serial interface, no image data can be transmitted, and no image can thus be displayed on the display panel 102. Also, in a case in which the link is once established, and in which the link is then disconnected due to a noise or the like, no image can be displayed on the display panel 102 until the link is established again. A similar problem occurs in a case in which the cable is pulled or disconnected, or in which the serial interface or the graphic controller 110 is partially failed. Such a state in which no image can be displayed as each of the above states is referred to as “an undisplayable state.”

(72) Since the warning lamp has important information that should be given to the driver, the warning lamp is required to be lit even in the undisplayable state. Under such circumstances, the warning lamp is required to be provided outside the display panel.

(73) Conversely, with use of the timing controller 300 according to the embodiment, the warning lamp can be displayed on the display panel as the character data S.sub.5 for the OSD. The reason for this is that communication by means of the differential serial interface is not required for the OSD display. Since this can dispense with the LED and the driving circuit thereof, the cost can be reduced. Also, since a standard function of the ECU such as I.sup.2C can be used, the cost can further be reduced.

(74) Also, in a case in which the in-vehicle display device 600 is in a state in which no input video data S.sub.1 can be displayed (undisplayable state), the display panel 102 will black out, which poses a problem for driving. To solve the problem, numbers, alphabets, and the like may be prepared as the character data S.sub.5 for the OSD. As illustrated in FIG. 8C, in a case in which a certain abnormality occurs during driving, and in which the speed meter 604 and the tachometer 606 cannot be displayed, car speed information 610 and information 612 about the number of revolutions of the engine can be displayed in real time with use of the OSD function, and the safety can be improved.

(75) Also, during a period until the input video data S.sub.1 can be displayed after the car is ignited to cause the in-vehicle display device 600 to be activated, a character string such as “PLEASE WAIT . . . ” and current time can be displayed with use of the OSD function.

(76) The timing controller 300 can be used for a medical display device. The medical display device displays information required for doctors and nurses during an examination, treatment, or operation. In the medical display device, important information (such as a heart rate and blood pressure of a patient) can be displayed with use of the OSD function even in a state in which no input video data S.sub.1 can be displayed.

(77) FIG. 9 is a perspective view illustrating an electronic device 500. The electronic device 500 in FIG. 9 can be a laptop computer, a tablet terminal, a smartphone, a portable game machine, an audio player, or the like. The electronic device 500 includes the graphic controller 110, the display panel 102, the gate driver 104, and the source drivers 106 incorporated in a chassis 502. Between the timing controller 300 and the graphic controller 110, a transmission device 120 including a differential transmitter, a transmission path, and a differential receiver may be provided.

(78) Modification examples of the first embodiment will be described.

First Modification Example

(79) Although the character data S.sub.9 for the OSD is displayed to be superimposed on the frame data S.sub.10 in the embodiment, the present invention is not limited to this, and the character for the OSD may be displayed to be transparent or translucent by means of alpha blending. In this case, the color data CD may be an a value representing the transparency. Consequently, the character data S.sub.9 can be transparent or translucent and be displayed to be superimposed on the frame data S.sub.10.

Second Modification Example

(80) The encoder 322 may further compress the 24-bit color data CD with use of a color palette. For example, when the compressed data S.sub.6 is constituted by sixteen or less colors, a 4-bit color palette is generated. Each time a segment of a new color appears, the encoder 322 adds the color to the palette and holds an identifier thereof in the color palette as the color data CD. In a case in which a same-color segment of a color included in the color palette appears, the encoder 322 holds an identifier of the color as the color data CD. Accordingly, the segment data can further be compressed.

Third Modification Example

(81) The type of the control input interface 310 is not limited to the register access type. For example, differential serial transmission may be used in a similar manner to that in the first line 112, or the control input interface 310 can be designed as an arbitrary interface.

Fourth Modification Example

(82) Although the character data S.sub.5 in the setup state and the instruction signal S.sub.8 in the normal state are received by the common control input interface 310 in the embodiment, these may be received by separate interfaces.

Fifth Modification Example

(83) Although the run-length compression, which is easily implemented, has been described in the embodiment, other image compression may be used. Also, error detection such as cyclic redundancy check (CRC) may be added to the character data S.sub.5, the instruction signal S.sub.8, and the like. Instead of the CRC, error detection such as parity and checksum may be added.

Second Embodiment

(84) FIG. 10 is a block diagram of an image display system 100 including a timing controller 400 according to a second embodiment. In a similar manner to that in the image display system 100R in FIG. 1, the timing controller 400 receives the input video data S.sub.1 from the graphic controller 110, supplies the output video data S.sub.2 to one or the plurality of source driver(s) 106, and outputs the control/synchronous signal S.sub.3 to the gate driver 104 and one or the plurality of source driver(s) 106. The timing controller 400 may be a functional integrated circuit (IC) integrated on one semiconductor substrate.

(85) The timing controller 400 includes the video input interface 302, a frame memory 303, an image processing circuit 306, the output interface 308, the control input interface 310, an abnormality detector 340, and a memory 342.

(86) The video input interface 302, the frame memory 303, the image processing circuit 306, and the output interface 308 are circuit blocks related to display of image data from the graphic controller 110 and may be the same as those included in the conventional timing controller 200R. The video input interface 302 is connected to the graphic controller 110 via a signal line 112 and receives the input video data S.sub.1. As an interface between the video input interface 302 and the graphic controller 110, a differential high-speed serial interface such as a low voltage differential signaling (LVDS) can be employed. The input video data S.sub.1 received by the video input interface 302 is stored as the frame data S.sub.4 in the frame memory 303. The frame memory 303 may be a static random access memory (SRAM) without limitation. Meanwhile, the frame memory 303 may be a frame buffer holding one-frame image data or a line buffer holding data for one or a plurality of line(s), and the frame data S.sub.4 may referred to as line data.

(87) The image processing circuit 306 performs various kinds of signal processing to the frame data S.sub.4. The signal processing of the image processing circuit 306 is not particularly limited, and a known technique may be used such as γ (gamma) correction, frame rate control (FRC) processing, and RGB mapping. The output interface 308 outputs the output video data S.sub.2 processed by the image processing circuit 306 to the source driver 106. The image processing circuit 306 also generates the control/synchronous signal S.sub.3 that is to be supplied to the gate driver 104 and the source driver 106.

(88) The abnormality detector 340 and the memory 342 are provided in relation to a function of detecting an abnormal state, especially the undisplayable state.

(89) The memory 342 stores reference character data S.sub.REF describing predetermined characters that can be contained in the input video data S.sub.1. The memory 342 may be a read-only memory (ROM) or a rewritable non-volatile memory such as a flash memory. Alternatively, the memory 342 may be a volatile memory as described in relation to an embodiment in FIG. 13.

(90) The abnormality detector 340 determines whether or not an abnormality (or the undisplayable state) exists based on the input video data S.sub.1 and the reference character data S.sub.REF when a predetermined character should be contained in a frame represented by the input video data S.sub.1. Specifically, the abnormality detector 340 determines whether or not a predetermined character represented by the reference character data S.sub.REF is correctly contained in the input video data S.sub.1. The abnormality detector 340 determines that the state is normal in a case in which the predetermined character is contained and that the state is abnormal in a case in which the predetermined character is not contained.

(91) The processor 114 is a central processing unit (CPU) or a microcomputer comprehensively controlling the image display system 100. Although FIG. 10 illustrates a configuration in which the processor 114 is provided separately from the graphic controller 110, the function of the processor 114 may be incorporated into the graphic controller 110.

(92) The control input interface 310 is provided separately from the video input interface 302, and the timing controller 400 is configured to enable communication with the processor 114 and can receive various control signals S.sub.11 from the processor 114. As the control input interface 310, a register-access-type interface can be used. Favorable examples thereof include, but are not limited to, a serial peripheral interface (SPI) and an inter-integrated circuit (I.sup.2C) interface.

(93) When an abnormality is detected by the abnormality detector 340, the timing controller 400 may interrupt the processor 114. This enables notification of generation of the abnormality (generation of the undisplayable state) to be given to the processor 114. The way to interrupt the processor 114 is not particularly limited, and an interrupt request (IRQ) may be used, for example.

(94) The configuration of the timing controller 400 has been described above. Next, an operation thereof will be described.

(95) FIG. 11 illustrates an example of the predetermined character. The example of the predetermined character is, but is not limited to, an icon representing the battery. The memory 342 has stored therein the reference character data S.sub.REF representing such a predetermined character.

(96) FIG. 12A and FIG. 12B illustrate abnormality detection by means of the timing controller 400. Each of FIG. 12A and FIG. 12B illustrates the frame data S.sub.4 based on the input video data S.sub.1 received by the video input interface 302. Here, to facilitate understanding, predetermined characters are contained at predetermined positions in all frames.

(97) FIG. 12A illustrates frame data S.sub.4a in a case in which the video input interface 302 has received the input video data S.sub.1 normally. The frame data S.sub.4a can contain various characters such as a speed meter and a tachometer. Since the frame data S.sub.4a in FIG. 12A contains the predetermined character in FIG. 11 correctly at a predetermined position, the abnormality detector 340 determines that the state is normal.

(98) FIG. 12B illustrates frame data S.sub.4b in a case in which the video input interface 302 has not received the input video data S.sub.1 correctly. In this example, information about the lower half of the frame data S.sub.4b is lost due to a communication error, and the frame data S.sub.4b does not contain the lower half of the predetermined character in FIG. 11 correctly. Accordingly, the abnormality detector 340 determines that the state is abnormal.

(99) In this manner, according to the timing controller 400 in FIG. 10, whether or not the input video data S.sub.1 is received correctly can be determined, and an abnormal state can be detected.

(100) Additional functions and characteristics of the timing controller 400 will be described below.

(101) Preferably, the control signal S.sub.11 that the control input interface 310 receives from the processor 114 may contain information S.sub.11A indicating whether or not a current frame is targeted for determination by the abnormality detector 340. Accordingly, in a case in which the predetermined character is contained in all frames, the frequency of abnormality determination (for example, once per sixty frames and once per second) can be controlled.

(102) By using this information S.sub.11A, a character(s) to be displayed only when a predetermined condition is satisfied can be the predetermined character. For example, each of various warning lamps to be displayed on the cluster panel corresponds to such a character.

(103) The display position of the predetermined character can be variable. In this case, the control signal S.sub.11 that the control input interface 310 receives from the processor 114 may contain positional information Sim indicating a display position of the predetermined character. Accordingly, the abnormality detector 340 may determine if the predetermined character is correctly displayed at a position indicated by the positional information SUB of the frame data S.sub.4.

(104) The predetermined character may be arranged in a fixed manner at a predetermined position at the end portion on the display panel that cannot be seen by the user. Accordingly, all frames can be targeted for determination by the abnormality detector 340.

(105) The number of the predetermined characters is not limited to one but may be plural. In this case, the reference character data S.sub.REF may be prepared for each predetermined character.

(106) The configuration of the present invention is comprehended as the block diagram or the circuit diagram in FIG. 10, is applied to various devices and circuits led from the above description, and is not limited to a specific configuration. Hereinbelow, more specific configuration examples and modification examples will be described to facilitate understanding of the nature of the invention and the circuit operation and clarify these, not to narrow the scope of the present invention.

(107) FIG. 13 is a block diagram of an image display system 100A including a timing controller 400A according to an embodiment.

(108) The timing controller 400A is in a setup state immediately after turning on the power. For example, the timing controller 400A has a period for setting parameters and the like of the γ correction and the RGB mapping (initializing period) at the time of the power-on as a previous stage to reception and output of the video input data to a panel. A part of the initializing period may be regarded as the setup state.

(109) Alternatively, giving a command from an outside to the timing controller 400A may enable the setup state to be set. For example, a register associated with the setup state may be provided inside the timing controller 400A, and 1 may be written in the register from the outside (for example, the processor 114) to shift a state to the setup state. In this case, the state can be shifted to the setup state not only immediately after turning on the timing controller 400A but also at an arbitrary time.

(110) In the present embodiment, the memory 342 may be a static random access memory (SRAM). The control input interface 310 can receive the character data S.sub.5 representing the predetermined character from the processor 114 in the setup state. The character data S.sub.5 is stored in the non-volatile memory 118 and is transmitted via the processor 114 to the control input interface 310. The character data S.sub.5 may be monochrome or colored bitmap data without limitation. Also, the representation form of the character data S.sub.5 is an arbitrary form such as icons, graphics, and characters. There may be the plurality of pieces of the character data S.sub.5.

(111) The timing controller 400A further includes the encoder 322 and the decoder 324. In the setup state, the encoder 322 encodes the character data S.sub.5 received by the control input interface 310, generates the reference character data S.sub.REF, and stores the data in the memory 342. In the normal state, the decoder 324 decodes the reference character data S.sub.REF read from the memory 342 and reproduces an original predetermined character.

(112) The configuration of the timing controller 400A has been described above. Next, compression of the character data S.sub.5 will be described. For compression of the character data S.sub.5, run-length compression can be used. The run-length compression has been described with reference to FIG. 3 to FIG. 5A to FIG. 5C.

(113) The configuration of the timing controller 400A has been described above. Next, an operation thereof will be described.

1. Setup State

(114) When a device or a system including the timing controller 400A is activated, the timing controller 400A is in a setup state. The processor 114 transmits the character data S.sub.5 as well as the size data SIZE to the control input interface 310. The encoder 322 compresses the received character data S.sub.5 and stores the compressed data S.sub.6 in the memory 342 as the reference character data S.sub.REF. In a case in which there are a plurality of pieces of character data S.sub.5, the plurality of pieces of character data are compressed sequentially.

2. Normal State

(115) The graphic controller 110 transmits the input video data S.sub.1 via the signal line 112 to the video input interface 302. The timing controller 400A processes the input video data S and controls the gate driver 104 and the source drivers 106 to display an image on the display panel. The abnormality detector 340 determines whether or not the predetermined character reproduced by the decoder 324 is correctly contained in the frame data S.sub.4.

(116) The operation of the timing controller 400A has been described above. Next, advantages thereof will be described.

(117) Since the encoder and the decoder for the character data for the abnormality determination are incorporated in the timing controller 400A, and the character data S.sub.5 is given each time the timing controller 400A is in the setup state, the abnormality determination can be performed with use of various kinds of character data.

(118) Also, since the character data is stored in the memory 342 in a compressed form, the capacity of the memory 342 can be reduced, which leads to cost reduction. FIG. 6 illustrates the compression ratios of the same-color segments when the second data structure in FIG. 5B is employed. Here, the bit wide of the run-length word RLW is 4 bits. As the run-length value RL is higher, the higher compression ratio is obtained. In a case in which the run-length value is 1 or 2, the segment data is larger than the data volume of the original pixel data. However, in most of characters, icons, and graphics, the run-length value is 1 or 2 only in a case of anti-aliasing or the like, and the probability of occurrence thereof is extremely low. Accordingly, the compression ratio of the entire character data can sufficiently be raised.

(119) In a case in which the memory 342 storing the reference character data S.sub.REF is a ROM, the cost is raised. However, in the timing controller 400A in FIG. 13, since a volatile memory such as an SRAM can be used as the memory 342, the cost can be reduced.

(120) In a case in which, as the non-volatile memory 118 to be connected to the processor 114, not the one time ROM but the rewritable non-volatile memory 118 such as a hard disk, a solid state drive (SSD), an electrically erasable programmable read-only memory (EEPROM), and a flash memory is used, the following advantages can be obtained. That is, in a case in which the one time ROM is used as the memory 342, and in which the reference character data S.sub.REF is stored in the one time ROM, the predetermined character cannot be added or changed. Conversely, in a case in which the volatile memory is used as the memory 342, and in which the rewritable non-volatile memory is used as the processor 114, the character data stored in the non-volatile memory 118 can be changed or added. Accordingly, the character for the abnormality detection can easily be changed or added.

(121) FIG. 14 is a block diagram of the image display system 100A including a timing controller 400B according to an embodiment. The timing controller 400B includes the OSD function. The memory 342 has stored therein the character data for the OSD. Preferably, the reference character data S.sub.REF for the abnormality detection and the character data for the OSD are used in common. This enables the capacity of the memory 342 to be saved.

(122) In the timing controller 400B, an OSD mode and an abnormality detection mode are switchable. The OSD mode and the abnormality detection mode may be selectable in accordance with the control signal S.sub.11 from the processor 114.

(123) The OSD mode and the determination mode in which determination is given by the abnormality detector may be selectable. In the determination mode, the abnormality detector 340 is activated and gives abnormality determination based on the character data reproduced by the decoder 324. The abnormality determination has been described above.

(124) In the OSD mode, the abnormality detector 340 is deactivated, and the OSD processor 320 of the image processing circuit 306 is activated. The OSD processor 320 superimposes the character data reproduced by the decoder 324 on the frame data S.sub.4 to generate the output video data S.sub.2.

(125) In a case in which a character is to be displayed on the display panel with use of the OSD function, the processor 114 sets the timing controller 400B to the OSD mode by means of the control signal S.sub.11.

(126) The processor 114 transmits the instruction signal S.sub.8 separately from the input video data S.sub.1. The instruction signal S.sub.8 contains the ID information designating one of the plurality of pieces of character data S.sub.5 transmitted to the timing controller 400B in the setup state and the positional information POS designating a display position.

(127) The decoder 324 refers to the address information S.sub.7 corresponding to the ID information and accesses the corresponding compressed data S.sub.6. The decoder 324 then decodes the compressed data S.sub.6 based on the size data SIZE to extract the character data S.sub.9 in a bitmap format. The OSD processor 320 displays the character data S.sub.9 at a position designated by the positional information POS. FIG. 15 illustrates the display panel 102 on which two pieces of character data S.sub.91 and S.sub.92 are displayed.

(128) According to the timing controller 400B, both the OSD function and the abnormality detection function can be provided. By using the character data for the OSD and the character data for the abnormality detection in common, the capacity of the memory 342 can be reduced.

(129) According to the timing controller 400B, while the OSD function can be provided on one platform, the abnormality detection function can be provided on another platform.

(130) Alternatively, in one platform, freedom to appropriately select the OSD function or the abnormality detection function can be provided. For example, the abnormality detection function may be active by default, and in a case in which an abnormality is detected by the abnormality detector 340, the OSD function may be used. When an abnormality is generated in transmission of image data via the signal line 112, the processor 114 is interrupted by the timing controller 400B. The interruption triggers the processor 114 to set the timing controller 400B to the OSD mode. By appropriately generating the instruction signal S.sub.8, the processor 114 can display an image on the display.

(131) More preferably, in the OSD mode and the abnormality detection mode, the instruction signal S.sub.8 for the OSD and the control signal S.sub.11 for the abnormality detection may be used in common. In other words, the register for control of the OSD and the register for the abnormality detection may be used in common. For example, an address at which the positional information POS for the OSD is written and an address at which the positional information Sim of the predetermined character is written in the abnormality detection mode may be equal. Accordingly, the capacity of the register can be reduced.

(132) Next, use of the timing controller 400 according to the second embodiment will be described. The timing controller 400 can be used in the in-vehicle display device 600 in FIG. 8A. The in-vehicle display device 600 is buried in the console 602 on the cockpit front face. The in-vehicle display device 600 receives from the vehicle processor and displays the input video data S.sub.1 including the speed meter 604, the tachometer 606 indicating the number of revolutions of the engine, the fuel remaining amount 608, and, in a case of a hybrid car or an electric car, the remaining amount of a battery (FIG. 8A).

(133) Conventionally, an indicator lamp or a warning lamp (hereinbelow referred to simply as a warning lamp) indicating a certain abnormality or a dead battery as illustrated in FIG. 8B is displayed outside the display panel with use of an independent LED. The reason for not displaying the warning lamp on the display panel is as follows. That is, the timing controller 400 and the graphic controller 110 are connected by means of a differential serial interface. During a period from start of activation of the system to establishment of a link between the timing controller 400 and the graphic controller 110 by means of the serial interface, no image data can be transmitted, and no image can thus be displayed on the display panel 102. Also, in a case in which the link is established, and in which the link is then disconnected due to a noise or the like, no image can be displayed on the display panel 102 until the link is established again. A similar problem occurs in a case in which the cable is pulled or disconnected, or in which the serial interface or the graphic controller 110 is partially failed. Such a state in which no image can be displayed as each of the above states is referred to as “an undisplayable state.”

(134) Since the warning lamp has important information that should be given to the driver, the warning lamp is required to be lit even in the undisplayable state. Under such circumstances, the warning lamp is required to be provided outside the display panel.

(135) Conversely, with use of the timing controller 400 according to the embodiment, the warning lamp can be displayed on the display panel as the character data S.sub.5 for the OSD. The reason for this is that communication by means of the differential serial interface is not required for the OSD display. Since this can dispense with the LED and the driving circuit thereof, the cost can be reduced. Also, since a standard function of the ECU such as I.sup.2C can be used, the cost can further be reduced.

(136) Also, in a case in which the in-vehicle display device 600 is in a state in which no input video data S.sub.1 can be displayed (undisplayable state), the display panel 102 will black out, which poses a problem for driving. To solve the problem, numbers, alphabets, and the like may be prepared as the character data S.sub.5 for the OSD. As illustrated in FIG. 8C, in a case in which a certain abnormality occurs during driving, and in which the speed meter 604 and the tachometer 606 cannot be displayed, the car speed information 610 and the information 612 about the number of revolutions of the engine can be displayed in real time with use of the OSD function, and the safety can be improved.

(137) Also, during a period until the input video data S.sub.1 can be displayed after the car is ignited to cause the in-vehicle display device 600 to be activated, a character string such as “PLEASE WAIT . . . ” and current time can be displayed with use of the OSD function.

(138) The timing controller 400 can be used for a medical display device. The medical display device displays information required for doctors and nurses during an examination, treatment, or operation. In the medical display device, important information (such as a heart rate and blood pressure of a patient) can be displayed with use of the OSD function even in a state in which no input video data S.sub.1 can be displayed.

(139) FIG. 9 is a perspective view illustrating the electronic device 500. The electronic device 500 in FIG. 9 can be a laptop computer, a tablet terminal, a smartphone, a portable game machine, an audio player, or the like. The electronic device 500 includes the graphic controller 110, the display panel 102, the gate driver 104, and the source drivers 106 incorporated in the chassis 502. Between the timing controller 400 and the graphic controller 110, the transmission device 120 including a differential transmitter, a transmission path, and a differential receiver may be provided.

(140) While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the appended claims.