Abstract
A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a semiconductor chip having an active region for radiation emission, applying a seed layer on the semiconductor chip, wherein the seed layer includes a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal, applying a structured photoresist layer directly to the seed layer, applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer and wherein a proportion of the second metal in the seed layer is between 0.5 wt % and 10 wt %.
Claims
1. A method for producing an optoelectronic component, the method comprising: providing a semiconductor chip having an active region for radiation emission; applying a seed layer on the semiconductor chip, wherein the seed layer comprises a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal; applying a structured photoresist layer directly to the seed layer; and applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer, wherein a proportion of the second metal in the seed layer is between 0.5 wt % and 10 wt %.
2. The method according to claim 1, further comprising tempering the seed layer.
3. The method according to claim 1, further comprising removing the photoresist layer with a lift-off method.
4. The method according to claim 1, further comprising removing the regions of the seed layer not covered by the photoresist layer by wet chemical etching.
5. The method according to claim 1, wherein a region between the photoresist layer and the seed layer is free of a nitride layer for adhesion promotion.
6. The method according to claim 1, wherein the seed layer is free of titanium.
7. The method according to claim 1, wherein the first metal is gold, silver, platinum or copper.
8. The method according to claim 1, wherein the second metal is zinc, tin or aluminum.
9. The method according to claim 1, wherein the first metal is gold and the second metal is zinc.
10. The method according to claim 1, wherein the seed layer has a layer thickness between 50 nm and 5000 nm.
11. The method according to claim 1, wherein the solder layer comprises a metal which is electrodeposited and corresponds to the first metal of the seed layer.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) Further advantages, advantageous embodiments and further developments result from the exemplary embodiments described in the following in connection with the figures.
(2) They show:
(3) FIGS. 1A to 1E show methods for producing an optoelectronic component;
(4) FIGS. 2A and 2B show schematic side views of an optoelectronic component according to an embodiment;
(5) FIGS. 3A to 3D show schematic top views or side views of an optoelectronic component according to an embodiment;
(6) FIGS. 4A to 4C show schematic top views or side views of an optoelectronic component according to an embodiment or according to an example of comparison; and
(7) FIGS. 5A and 5B show semiconductor chips according to an embodiment.
(8) In the exemplary embodiments and figures, same or similar and similar acting elements can each be labeled with the same reference signs. The elements shown and their size ratio are not to be regarded as true to scale. Rather, individual elements, such as layers, components, devices and regions, can be displayed exaggeratedly large for better representability and/or better understanding.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
(9) FIGS. 1A to 1E show a method for producing an optoelectronic component according to an embodiment.
(10) As shown in FIG. 1A, a semiconductor chip 1 is provided. For example, the semiconductor chip 1 is a gallium nitride semiconductor chip. A seed layer 4 can be applied to this semiconductor chip 1, in particular over the entire surface (FIG. 1B). As shown in FIG. 1B, a photoresist layer 9 can be applied to this seed layer 4 in a structured manner. The photoresist layer 9 is preferably applied directly to the seed layer 4. The photoresist can be a positive, negative or reverse resist. For example, AZ 15 nXT can be used as a photoresist. The seed layer 4 has a first metal, for example gold, and a second metal being different from the first metal, for example, zinc. The proportion of the first metal to the second metal is preferably 97:3.
(11) Subsequently, as shown in FIG. 1C, the solder layer to can be applied at least to regions of the seed layer 4 that are not covered by photoresist layer 9. In other words, the photoresist layer 9 here serves as a mask, wherein the solder layer 10 is applied between the regions not covered by the mask. The solder layer 10 is arranged laterally to the structured photoresist layer 9.
(12) Subsequently, as shown in FIG. 1D, the photoresist layer 9 can be removed again. The photoresist layers 9 can be removed using a lift-off method. Subsequently, regions of the seed layer 4 can be removed, which were covered by the photoresist layer 9. The removal of the seed layer 4, in particular in the regions between the structured regions of the solder layer 10, can be removed by wet chemical etching (FIG. 1E). Preferably the seed layer 4 is completely removed in these regions in order to avoid a short circuit.
(13) FIGS. 2A and 2B each show a schematic side view of an optoelectronic component according to an embodiment. The component has a semiconductor chip 1. A preferably structured seed layer 4 is arranged on the semiconductor chip. The seed layer 4 is followed directly by the solder layer 10. The solder layer 10 is preferably formed from a layer sequence, for example, gold and tin (not shown here).
(14) The component of FIG. 2B differs from the component of FIG. 2A in that here the contacts 5, 6 of the semiconductor chip 1, in particular the n-contact 5 and p-contact 6 of the semiconductor chip are shown. Both contacts 5, 6 are electrically separated from one another by a dielectric layer 6, for example, of silicon dioxide, in order to avoid a short circuit. The component in FIG. 2B also has deepenings or recesses 81. The deepenings were created as a result of the removal of the photoresist layer 9 during production.
(15) The FIGS. 3A to 3D show a schematic top view or side view of an optoelectronic component too according to an embodiment.
(16) FIG. 3A shows the component with a large number of light generation regions 7. Here, the light generation regions 7 are arranged in a matrix. FIG. 3A also shows the semiconductor layer sequence or the front side of the semiconductor chip 1, i.e., the side through which the radiation is emitted.
(17) FIG. 3B shows the back side of the semiconductor chip 1. The solder layer 10 can be applied galvanically to this back side of the semiconductor chip 1.
(18) FIG. 3C shows a cutout of the backside of the semiconductor chip 1. The n-contact 5 and the p-contact 6 are shown. These two contacts are spatially and electrically separated from one another. The photoresist layer 9 is also shown. This photoresist layer 9 is removed again in a subsequent method step.
(19) The FIG. 3D shows the schematic side view of an optoelectronic component according to an embodiment. In comparison to the component of FIG. 2B, the component of FIG. 3D also shows an adhesion layer 31. The adhesion layer 31, for example, can be made of titanium. The adhesion layer 31 can also be missing.
(20) FIGS. 4A to 4C show a schematic top view or side views of a component according to examples of comparison. FIGS. 4B and 4C each show a sectional view of AA′, as shown in FIG. 4A. Here a second dielectric layer 8, in particular of silicon nitride, is used to enable the photoresist layers 9 to adhere to the seed layer 4. The inventors have now found out that such a second dielectric layer 8 can be completely dispensed with if the seed layer 4 described here, in particular of gold and zinc, is used.
(21) FIGS. 5A and 5B each show a schematic side view of a semiconductor chip 1 according to an embodiment.
(22) The semiconductor chip 1 of FIG. 5A has a carrier 16 on which an n-contact 5 is arranged. A p-contact 6 is arranged above the n-contact 5. The semiconductor chip 1 further comprises a semiconductor layer sequence comprising at least one p-doped semiconductor layer, at least one n-doped semiconductor layer, and an active region. The n-contact 5 extends up to the n-doped semiconductor layer and thus electrically contacts it. The p-contact 6 electrically contacts the p-doped semiconductor layer 12.
(23) FIG. 5B shows a schematic side view of a so-called flip chip. This means that the contacts 5, 6 are arranged on the same side of the semiconductor chip 1. The semiconductor chip 1 can be arranged on a carrier 16. The arrangements described in FIGS. 5A and 5B can also have the solder layer 10 and the seed layer 4 according to the above embodiments and are applicable accordingly.
(24) The exemplary embodiments described in connection with the Figures and their features can also be combined with one another according to further exemplary embodiments, even if such combinations are not explicitly shown in the Figures. Furthermore, the exemplary embodiments described in connection with the Figures can have additional or alternative features as described in the general part.
(25) The invention is not limited by the description using the exemplary embodiments of these. Rather, the invention includes any new feature, as well as any combination of features, which in particular includes any combination of features in the claims, even if that feature or combination itself is not explicitly stated in the claims and exemplary embodiments.
