MILLIMETER-WAVE POWER AMPLIFIER

Abstract

In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.

Claims

1. A method for operating a millimeter-wave power amplifier comprising an input transistor having an output node coupled to a load path of a cascode transistor, the method comprising: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.

2. The method of claim 1, further comprising: generating a bias reference voltage; and comparing a voltage of a reference node of the cascode transistor to the bias reference voltage, wherein adjusting the first DC bias current comprises adjusting the first DC bias current until the bias reference voltage and the voltage of the reference node of the cascode transistor are substantially at a same DC voltage.

3. The method of claim 2, wherein: comparing the voltage of the reference node of the cascode transistor to the bias reference voltage comprises using a transconductance amplifier; and adjusting the first DC bias current further comprises providing a bias voltage for the input transistor using a diode connected transistor coupled to an output of the transconductance amplifier and to the control node of the input transistor.

4. The method of claim 2, wherein generating the bias reference voltage comprises: applying a reference current to a cascode reference transistor; and applying a same cascode bias voltage to a control node of the cascode transistor and a control node of the cascode reference transistor.

5. The method of claim 1, wherein; the input transistor comprises a first input transistor and a second input transistor; the cascode transistor comprises a first cascode transistor and a second cascode transistor, wherein the first input transistor has an output node coupled to a load path of the first cascode transistor, and the second input transistor has an output node coupled to a load path of the second cascode transistor; and providing the output signal to the load comprises providing a first phase of the output signal to the load from the first cascode transistor, and providing a second phase of the output signal to the load from the second cascode transistor.

6. The method of claim 5, wherein: receiving the millimeter-wave transmit signal comprises receiving the millimeter-wave transmit signal via a first transformer coupled between a control node of the first input transistor and a control node of the second input transistor; and providing the output signal to the load comprises providing the output signal to the load via a second transformer coupled between an output node of the first cascode transistor and an output node of the second cascode transistor.

7. The method of claim 1, further comprising limiting the first DC bias current.

8. The method of claim 1, further comprising, using an interstage matching network coupled between the output node of the input transistor and a reference node of the cascode transistor, modifying an impedance seen by the output node of the input transistor, wherein the interstage matching network at least partially compensates for an increased impedance caused by a parasitic inductance coupled between the output node of the input transistor and the reference node of the cascode transistor.

9. A millimeter-wave power amplifier comprising: a cascode transistor having an output node configured to be coupled to a load; an input transistor having an output node coupled to a load path of the cascode transistor; and a bias circuit coupled to the input transistor and the cascode transistor, the bias circuit configured to adjust a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.

10. The millimeter-wave power amplifier of claim 9, wherein the bias circuit comprises: a bias reference voltage generator configured to produce a bias reference voltage; and a feedback circuit configured to adjust the first DC bias current until the bias reference voltage and a voltage of a reference node of the cascode transistor have substantially a same DC voltage.

11. The millimeter-wave power amplifier of claim 10, wherein: the feedback circuit comprises a transconductance amplifier having a first input coupled to the bias reference voltage generator and a second input coupled to the reference node of the cascode transistor; and a diode connected transistor coupled to an output of the transconductance amplifier and a control node of the input transistor.

12. The millimeter-wave power amplifier of claim 10, wherein the bias reference voltage generator comprises a cascode reference transistor having a load path coupled to reference current source, and a control node coupled to a cascode bias node configured to provide a cascode reference voltage, wherein a control node of the cascode transistor is configured to receive a same cascode reference voltage.

13. The millimeter-wave power amplifier of claim 9, wherein: the input transistor comprises a first input transistor and a second input transistor; and the cascode transistor comprises a first cascode transistor and a second cascode transistor, wherein the first input transistor has an output node coupled to a load path of the first cascode transistor, and the second input transistor has an output node coupled to a load path of the second cascode transistor.

14. The millimeter-wave power amplifier of claim 13, further comprising: a first transformer having a first winding coupled between a control node of the first input transistor and a control node of the second input transistor, and a second winding configured to receive an RF input signal; and a second transformer coupled between the output node of the first cascode transistor and an output node of the second cascode transistor.

15. The millimeter-wave power amplifier of claim 9, further comprising a current limiting circuit configured to limit the first DC bias current to a first predetermined limit current.

16. The millimeter-wave power amplifier of claim 9, wherein the input transistor and the cascode transistor each comprise a bipolar junction transistor.

17. A millimeter-wave power amplifier comprising: a first signal path comprising a first input transistor, and a first cascode transistor having a first reference node coupled to a first output node of the first input transistor; a second signal path comprising a second input transistor, and a second cascode transistor having a second reference node coupled to a second output node of the second input transistor; a further cascode transistor configured to receive a reference current at a bias reference node; a first amplifier having a first input coupled to the bias reference node and a second input coupled to the first reference node of the first cascode transistor and to the second reference node of the second cascode transistor; and a first diode connected transistor coupled to an output of the first amplifier and coupled to a first control node of the first input transistor and a second control node of the second input transistor.

18. The millimeter-wave power amplifier of claim 17, further comprising a current limiting circuit coupled between the output of the first amplifier and the first diode connected transistor.

19. The millimeter-wave power amplifier of claim 17, further comprising an input transformer comprising: a first winding having a first end coupled to the first control node of the first input transistor, a second end coupled to the second control node of the input second transistor, and a center tap coupled to the first diode connected transistor; and a second winding configured to receive an RF input signal.

20. The millimeter-wave power amplifier of claim 17, wherein the first input transistor, the second input transistor, the first cascode transistor, the second cascode transistor and the first diode connected transistor each comprise a bipolar junction transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0009] FIG. 1A illustrates a schematic of an exemplary power amplifier; FIG. 1B illustrates a Smith chart representation of internal impedances of the power amplifier of FIG. 1A; and FIGS. 1C and 1D illustrate waveform diagrams associated with the performance of the power amplifier of FIG. 1A;

[0010] FIG. 2A illustrates a schematic a power amplifier according to an embodiment; FIGS. 2B and 2C illustrate waveform diagrams associated with the power amplifier of FIG. 2A; FIG. 2D illustrates a plot of gain with respect to output power for different power amplifier configurations; and FIG. 2E illustrates a schematic of a power amplifier according to another embodiment;

[0011] FIGS. 3A and 3B illustrate schematics of power amplifiers according to further embodiments;

[0012] FIG. 4A illustrates a power amplifier according to a further embodiment; FIG. 4B illustrates a Smith chart representation of internal impedances of the power amplifier of FIG. 4A; and FIG. 4C illustrates a plot of gain with respect to output power for different power amplifier configurations;

[0013] FIG. 5 illustrates a block diagram of a method according to an embodiment; and

[0014] FIG. 6A illustrates a radar transceiver according to an embodiment; and FIG. 6B illustrates an RF transceiver according to an embodiment.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0015] The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0016] In an embodiment, a millimeter-wave power amplifier includes a cascode transistor having an output node configured to be coupled to a load; an input transistor having an output node coupled to a load path of the cascode transistor; and a bias circuit coupled to the input transistor and the cascode transistor. The bias circuit is configured to adjust a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor. By biasing the input transistor in this manner, sufficient DC current can be supplied to the cascode transistor to allow for class AB operation at high signal levels.

[0017] FIG. 1 illustrates a schematic of an exemplary millimeter-wave power amplifier that includes an input stage having input transistors T.sub.1P and T.sub.1N and a cascode stage operating as a common base amplifier having cascode transistors T.sub.2P and T.sub.2N. In the depicted power amplifier, the input stage operates as a common emitter stage, and the cascode stage operates as a common base stage. An RF input signal RF.sub.IN is introduced at the bases of input transistors T.sub.1P and T.sub.1N via input transformer 106, and the output of the cascode stage is coupled to a load represented as resistor R.sub.L via output transformer 104. Input transistors T.sub.1P and T.sub.1N are biased by diode connected transistor T.sub.3 that is DC coupled to the bases of input transistors T.sub.1P and T.sub.1N via the center tap V.sub.B1 of the secondary winding of input transformer 106. Diode connected transistor T.sub.3 and input transistors T.sub.1P and T.sub.1N form a current mirror that mirrors bias current I.sub.BIAS (or a scaled version of bias current I.sub.BIAS) from diode connected transistor T.sub.3 to input transistors T.sub.1P and T.sub.1N. The collectors of cascode transistors T.sub.2P and T.sub.2N are biased with supply voltage V.sub.DD via the center-tap of the primary winding of output transformer 104.

[0018] Inductors L.sub.S represent the parasitic inductance of the signal routing between the respective collectors of input transistors T.sub.1P and T.sub.1N and the respective emitters of cascode transistors T.sub.2P and T.sub.2N. Capacitors C.sub.CE represent the respective parasitic collector-emitter capacitances of input transistors T.sub.1 and T.sub.1N and cascode transistors T.sub.2P and T.sub.2N, and capacitors C.sub.BE represent the respective parasitic collector-emitter capacitances of cascode transistors T.sub.2P and T.sub.2N.

[0019] During operation, input transformer 106 converts single ended RF input signal RF.sub.IN to a differential signal at the bases of input transistors T.sub.1P and T.sub.1N via input transformer 106. This differential signal is amplified by input transistors T.sub.1P and T.sub.1N to provide output currents I.sub.C1P and I.sub.C1N, which is passed to the emitters of cascode transistors T.sub.2P and T.sub.2N. Output currents I.sub.C2P and I.sub.C2N are input to the primary winding of output transformer 104 to provide an amplified output signal to a load represented as resistor R.sub.L coupled to the secondary winding of output transformer 104. However, because of the effects of parasitic inductances L.sub.S and parasitic capacitances C.sub.CE and C.sub.BE, AC currents I.sub.E2P and I.sub.E2N at the emitters of cascode transistors T.sub.2P and T.sub.2N are higher than AC currents I.sub.C1P and I.sub.C2N at the collectors of input transistors input transistors T.sub.1P and T.sub.1N.

[0020] Parasitic inductances L.sub.S and parasitic capacitances C.sub.CE and C.sub.BE effectively cause an impedance transformation between the emitters of cascode transistors T.sub.2P and T.sub.2N and the collectors of input transistors T.sub.1P and T.sub.1N as illustrated in the Smith chart of FIG. 1B. Point 122 represents the impedance seen at the emitters of cascode transistors T.sub.2P and T.sub.2N, in which each transistor has a resistive impedance of 1/gm, where gm is the transconductance of cascode transistors T.sub.2P and T.sub.2N. Point 124 represents the impedance seen at the collectors of input transistors T.sub.1P and T.sub.1N after the impedance is transformed by parasitic capacitances C.sub.BE, parasitic inductances L.sub.S and parasitic capacitances C.sub.CE. As is apparent from the Smith chart, the transformed impedance at point 124 is higher than then the impedance at initial point 122.

[0021] FIGS. 1C and 1D are waveform diagrams that illustrate the effect of the impedance transformation on the operation of power amplifier 100. FIG. 1C illustrates a graph of normalized RF current 131, DC current 132, and quiescent current 133 at the collector of input transistor T.sub.1P with respect to normalized input voltage. RF current 131 is a time domain representation of the AC and DC components of the output current, DC current 132 represents the DC component of the output current, and quiescent current 133 represents the portion of the DC current attributable to the DC bias voltage applied between the base and emitter of input transistor T.sub.1P. As is apparent from FIG. 1C, DC current 132 is the same as quiescent current 133 up to normalized input voltages of 0.5 when the input stage of power amplifier experiences class A operation. However, at normalized input voltages above 0.5, input transistor T.sub.1P, the RF current 131 is zero for a portion of its operation, which indicates that input transistor T.sub.1P experiences class AB operation. The increase of DC current 132 at normalized input voltages above 0.5 is indicative of additional DC current supplied by input transistor T.sub.1P as its base voltage increases in response to higher input signal levels.

[0022] FIG. 1D illustrates a graph of normalized RF current 134, DC current 135, and quiescent current 136 at the collector of cascode transistor T.sub.2P with respect to normalized input voltage at the input stage. RF current 134 represents the AC and DC component of the output current, DC current 135 represents the DC component of the output current, and quiescent current 136 represents the portion of the DC current attributable to the DC bias voltage applied between the base and emitter of input transistor T.sub.2P. This DC bias voltage is the difference between applied bias voltage V.sub.B2 and the average voltage seen at the emitter of cascode transistor T.sub.2P.

[0023] As is apparent from FIG. 1D, DC current 135 is the same as quiescent current 136 up to normalized input voltages of about 0.25 when the cascode stage of power amplifier experiences class A operation. However, at normalized input voltages above 0.25, cascode transistor T.sub.2P, the RF current 134 is zero for a portion of its operation, which indicates that cascode transistor T.sub.CP experiences class AB operation. A comparison of FIGS. 1C and 1D reveal that the cascode stage enters class AB operation lower normalized input voltages (e.g. 0.25 V) than the input stage (0.50 V). This reduction in the normalized input voltage at which the cascode stage enters class AB operation is due to the effect of the above-mentioned impedance transformation of the RF current in the amplifier that causes the AC emitter currents of cascode transistors T.sub.2P and T.sub.2N to be larger than the collector currents of input transistors T.sub.1P and T.sub.1N. Since cascode transistors T.sub.2P and T.sub.2N operate at higher AC currents than input transistors T.sub.1P and T.sub.1N, cascode transistors T.sub.2P and T.sub.2N transition to class AB operation at lower normalized input voltages than input transistors T.sub.1P and T.sub.1N.

[0024] Additionally, it can be seen that quiescent current 136 decreases as the normalized input voltage increases when the cascode stage is in class AB operation, and RF current 134 shows signs of compression at higher normalized input voltages. As the cascode stage enters class AB operation, cascode transistors T.sub.2P and T.sub.2N effectively become “self-pinched” being effectively in class-C above a normalized input voltage of e.g. 0.9. The emitters of cascode transistors T.sub.2P and T.sub.2N are coupled to the relatively high impedances at the collectors of input transistors T.sub.1P and T.sub.1N. As such, input transistors T.sub.1P and T.sub.1N function as current sources that limit the ability of cascode transistors T.sub.2P and T.sub.2N to draw additional current. This results in a reduction of gain and a decreased 1 dB compression point for amplifier 100.

[0025] FIG. 2A illustrates a schematic of power amplifier 200 in which input transistors T.sub.1P and T.sub.1N are biased in a manner that advantageously maintain a substantially constant bias current in cascode transistors T.sub.2P and T.sub.2N even when power amplifier 200 operates as a class AB amplifier. The topology of power amplifier 200 is similar to the topology of power amplifier 100 shown in FIG. 1A with the exception that a feedback circuit forming a bias feedback loop is added to control the bias current of input transistors T.sub.1P and T.sub.1N. As shown, the common mode voltage V.sub.E2,DC of the emitters of cascode transistors T.sub.2P and T.sub.2N is monitored via resistors R.sub.SENSE that provide access to the AC ground node separating the DC content from the AC swing of the emitter node. Alternatively, this monitoring could also be achieved using inductors. Bias reference voltage V.sub.REF at a bias reference node is generated by applying bias current I.sub.BIAS generated by reference current source 204 to the emitter of bias transistor T.sub.4 (also referred to as a “cascode reference transistor” or “further cascode transistor”), and by applying bias voltage V.sub.B2 (also referred to as a “cascode reference voltage”) to the base of bias transistor T.sub.4 at a cascode bias node. Current source 204 and transistor T.sub.4 may be collectively referred to as a “bias reference voltage generator.” Transconductance amplifier 202 provides an amplified current having a magnitude proportional to the difference between common mode voltage V.sub.E2,DC and bias reference voltage V.sub.REF. This current is mirrored by diode connected transistor T.sub.3 to input transistors T.sub.1P and T.sub.1N. The bias feedback loop formed by transconductance amplifier 202, transistor T.sub.3, input transistors T.sub.1P and T.sub.1N, and cascode transistors T.sub.2P and T.sub.2N adjusts the bias current of input transistors T.sub.1P and T.sub.1N such that the common mode voltage V.sub.E2,DC of the emitters of cascode transistors T.sub.2P and T.sub.2N is very close to the bias reference voltage V.sub.REF. While the emitters of input transistors T.sub.1P and T.sub.1N are shown coupled directed to ground, it should be understood that in some embodiments, the emitters of input transistors T.sub.1P and T.sub.1N may be coupled to ground (or to another reference voltage node) via a degeneration resistor or other component.

[0026] Because the bases of cascode transistors T.sub.2P and T.sub.2N are biased to the same voltage V.sub.B2 as the base of bias transistor T.sub.4, the DC component of the base-emitter voltage of cascode transistors T.sub.2P and T.sub.2N is the substantially the same as the base-emitter voltage of bias transistor T.sub.4. Accordingly, the DC quiescent current of cascode transistors T.sub.2P and T.sub.2N is proportional to bias current I.sub.BIAS flowing through transistor T.sub.4. In various embodiments, the ratio of the DC quiescent current of cascode transistors T.sub.2P and T.sub.2N to bias current I.sub.BIAS is related to the emitter area ratio between each of cascode transistors T.sub.2P and T.sub.2N and bias transistor T.sub.4. For example, if the emitter areas of cascode transistors T.sub.2P and T.sub.2N are each equal to the emitter area of bias transistor T.sub.4, the DC quiescent current of each of cascode transistors T.sub.2P and T.sub.2N is substantially I.sub.BIAS. On the other hand, if the emitter areas of cascode transistors T.sub.2P and T.sub.2N are each k times larger than the emitter area of bias transistor T.sub.4, the DC quiescent current of each of cascode transistors T.sub.2P and T.sub.2N is substantially k I.sub.BIAS. The accuracy of DC quiescent current of each of cascode transistors T.sub.2P and T.sub.2N and I.sub.BIAS depends on how well cascode transistors T.sub.2P and T.sub.2N are matched and depends on the loop gain of the bias feedback loop.

[0027] FIGS. 2B and 2C are waveform diagrams that illustrate the effect of the bias feedback loop on the operation of power amplifier 200. FIG. 2B illustrates a graph of normalized RF current 231 and quiescent current 233 at the collector of input transistor T.sub.1P with respect to normalized input voltage. As shown, quiescent current 133 is constant up to normalized input voltages of 0.3. At this point, cascode transistors T.sub.2P and T.sub.2N undergoes class AB operation, which causes the bias control loop to increase its bias current.

[0028] FIG. 2C illustrates a graph of normalized RF current 234, DC current 235, and quiescent current 236 at the collector of cascode transistor T.sub.2P with respect to normalized input voltage at the input stage. As is apparent from FIG. 2C, DC current 232 is the same as quiescent current 233 up to normalized input voltages of about 0.3 as the cascode stage of power amplifier experiences class A operation. However, at normalized input voltages above 0.3, cascode transistor T.sub.2P, the RF current 234 is zero for a portion of its operation, which indicates that cascode transistor T.sub.CP experiences class AB operation. However, unlike the operation of power amplifier 100 shown in the waveform diagram of FIG. 1D described above, the quiescent current 136 stays substantially constant due to the operation of the bias feedback loop as the normalized input voltage increases. It can also be seen that the normalized output current reaches 1 for power amplifier 200, while the normalized output current of power amplifier 100 only reaches about 0.78 under similar operation conditions. Thus, the use of an embodiment bias feedback loop advantageously increases the 1 dB compression point of power amplifier 200.

[0029] FIG. 2D illustrates a plot of gain with respect to output power for a variety of different power amplifier configurations operating at 100 GHz. Trace 242 represents the gain of a class-A power amplifier, trace 244 represents the gain of embodiment power amplifier 200 shown in FIG. 2A, and trace 245 illustrates the gain of exemplary power amplifier 100 shown in FIG. 1A. As apparent from FIG. 2D, both the class-A power amplifier and embodiment power amplifier 200 (with the bias feedback loop) have a 1 dB compression point of between 11 dB and 12 dB. Exemplary power amplifier 100, on the other hand, has a lower 1 dB compression point of about 8 dB.

[0030] FIG. 2E illustrates power amplifier 250 according to an alternative embodiment of the present invention. Power amplifier 250 is similar to power amplifier 200 shown in FIG. 2A, with the exception that transconductance amplifier 202 and diode connected transistor T.sub.3 is replaced with operational amplifier 252. During operation, operational amplifier 252 amplifies the difference between common mode voltage V.sub.E2,DC and bias reference voltage V.sub.REF and applies an amplified voltage difference V.sub.B1 to the bases of input transistors T.sub.1P and T.sub.1N via input transformer 106. The quiescent current through cascode transistors T.sub.2P and T.sub.2N is proportional to bias current I.sub.BIAS as described above with respect to the embodiment of FIG. 2A.

[0031] It should be understood that the embodiments of FIGS. 2A and 2E illustrate two specific examples of power amplifier that utilize bias feedback loops to maintain a substantially constant quiescent current in cascode transistors T.sub.2P and T.sub.2N. It should be understood that other bias feedback topologies may be used in alternative embodiments, and that embodiments of the present invention are not limited to power amplifiers of a cascode configuration. Embodiment concepts may also be applied to amplifiers having other topologies, such as amplifiers having a stacked configuration.

[0032] It should be further appreciated that while the power amplifiers disclosed herein are implemented using bipolar junction transistors, other transistor types could be used including, but not limited to metal oxide semiconductor field effect transistors (MOSFETs), heterojunction field effect transistors (HFETs), implemented high electron mobility transistors (HEMTs) implemented on a variety of semiconductor processes technologies including, but not limited to SiGe, GaN, CMOS, and GaAs.

[0033] In some embodiments, the bias current or peak power output of a power amplifier can be controlled by limiting the current in the bias feedback loop. Power amplifier 300 shown in FIG. 3A is similar to power amplifier 200 shown in FIG. 2A, with the exception that a current limiter 302 is coupled between the output of transconductance amplifier 202 and diode connected transistor T.sub.3. During operation, current limiter 302 limits the amount of current provided by transconductance amplifier to diode connected transistor T.sub.3. Limiting the current through transistor T.sub.3 limits the quiescent current of cascode transistors T.sub.2P and T.sub.2N to a value proportional to the current limit of current limiter 302. Current limiter 302 may be implemented using current limiting circuits known in the art. In some embodiments, the current limit of current limiter 302 is a predefined or predetermined limit current, which may be adjustable and/or programmable. By controlling the limiting current, the bias current, maximum output power and/or the 1 dB compression point of an embodiment amplifier can be adjusted and/or controlled.

[0034] FIG. 3B illustrates a power amplifier 320 according to a further embodiment of the invention that includes current limiter 322 having an adjustable current limit. As shown, current limiter 322 includes a transconductance amplifier 324 having a first input coupled to diode connected transistor T.sub.3 and a second input coupled to diode connected transistor T.sub.5 configured to receive a limiting current I.sub.MAX,REF. In some embodiments, limiting current I.sub.MAX,REF is programmable. The output of transconductance amplifier 324 is coupled to the input of transconductance amplifier 202 via diode D.sub.1. Diode D.sub.2 is coupled between the output of transconductance amplifier 324 and ground. During operation, transconductance amplifier 324 compares the base-emitter voltage of transistor T.sub.4 with the base-emitter voltage of transistor T.sub.5. When the base-emitter voltage of transistor T.sub.3 exceeds the base-emitter voltage of transistor T.sub.5, which indicates that the current supplied by transconductance amplifier to transistor T.sub.3 exceeds limit current I.sub.MAX,REF, transconductance amplifier 324 supplies current I.sub.L to node V.sub.REF. The application of current I.sub.L to node V.sub.REF reduces the current flowing through bias transistor T.sub.4, thereby reducing the bias current of power amplifier 320. It should be understood that the current limiting circuits depicted in FIGS. 3A and 3B are just two examples of many possible current limiting configurations that can be applied to power amplifiers according to embodiments of the present invention.

[0035] In some embodiments, the effect of the impedance transformation between input transistors T.sub.1P and T.sub.1N and cascode transistors T.sub.2P and T.sub.2N on the operation of a cascode RF power amplifier described above can also be mitigated by coupling a matching network between input transistors T.sub.1P and T.sub.1N and cascode transistors T.sub.2P and T.sub.2N, as shown in FIG. 4A. Inductors L.sub.S1 represent the parasitic inductance of the signal routing between the respective emitters of cascode transistors T.sub.2P and T.sub.2N and interstage matching network 402, Inductors L.sub.S2 represent the parasitic inductance of the signal routing between interstage matching network 402 and the respective collectors of input transistors T.sub.1P and T.sub.1N, capacitors C.sub.CE represent the respective parasitic collector-emitter capacitances of input transistors T.sub.1P and T.sub.1N and cascode transistors T.sub.2P and T.sub.2N, and capacitors C.sub.BE represent the respective parasitic collector-emitter capacitances of cascode transistors T.sub.2P and T.sub.2N. In various embodiments, capacitor C.sub.ISMN compensates for the impedance transformation caused by the above-mentioned parasitic inductances and capacitances such that the impedance seen by the collectors of input transistors T.sub.1P and T.sub.1N is close to the impedance of the emitters of cascode transistors T.sub.2P and T.sub.2N. Thus, interstage matching network 402 at least partially compensates for an increased impedance caused by a parasitic inductance coupled between the output nodes of the input transistors T.sub.1P and T.sub.1N and the emitters (also referred to as “reference nodes”) of cascode transistors T.sub.2P and T.sub.2N.

[0036] FIG. 4B shows a Smith chart that illustrates how matching network compensates for the impedance transformation. Point 422 represents in which each transistor has a resistive impedance of 1/gm. Point 424 represents the impedance seen at the port of interstage matching network 402 after the impedance is transformed by parasitic inductances L.sub.S and parasitic capacitances C.sub.CE and C.sub.BE. Capacitor C.sub.ISMIN transforms the inductive impedance at point 424 to a capacitive impedance at point 426, and parasitic inductance L.sub.s2 transforms the capacitive impedance at point 426 to a substantially real impedance at point 428, which represents the impedance seen at the collectors of input transistors T.sub.1P and T.sub.1N.

[0037] It should be understood that the illustrated implementation of interstage matching network 402 using capacitor C.sub.ISMIN is just one specific example of many possible matching networks. In alternative embodiments of the present invention, other impedance matching networks known in the art may be used to match the impedance of the emitters of cascode transistors cascode transistors T.sub.2P and T.sub.2N to the impedance of the collectors of input transistors T.sub.1P and T.sub.1N. It should also be understood that in some embodiments, interstage matching network 402 may be used to transform the impedance of the emitters of cascode transistors cascode transistors T.sub.2P and T.sub.2N to a different impedance depending on specification and requirements of the particular system. In yet further embodiments, interstage matching network 402 may also be combined with the embodiments described above in FIGS. 2A, 2E, 3A and 3B.

[0038] FIG. 4C illustrates a plot of gain with respect to output power for a variety of different power amplifier configurations operating at 100 GHz. Trace 442 represents the gain of a class-A power amplifier, trace 444 represents the gain of embodiment power amplifier 400 with interstage the matching network shown in FIG. 4A, and trace 445 illustrates the gain of exemplary power amplifier 100 shown in FIG. 1A. As apparent from FIG. 2D, both the class-A power amplifier and embodiment power amplifier 200 (with the bias feedback loop) have a 1 dB compression point of between 11 dB and 13 dB. Exemplary power amplifier 100, on the other hand, has a lower 1 dB compression point of about 9 dB. Thus, the inclusion of interstage matching advantageously increases the 1 dB compression point of a cascode power amplifier.

[0039] FIG. 5 illustrates a block diagram of an embodiment method 500 of operating a cascode power amplifier. In step 502, a millimeter-wave transmit signal is received at a control node of an input transistor. This input transistor may be implemented by input transistor T1.sub.P or T.sub.1N, as shown in the embodiment of FIG. 2A, where the control node corresponds to the base of these transistors. In embodiments that utilize MOSFETs, the control node would correspond to the gate of the MOSFET. In step 504, the millimeter-wave transmit signal is amplified to form an output signal using the input transistor and a cascode transistor. This output signal is provided to a load coupled to an output node of the cascode transistor in step 506. In some embodiments, such as the embodiment of FIG. 2A, the output node of the cascode transistor may be a collector. However, in embodiments that utilize MOSFETS, the output node would be a drain of the MOSFET. In step 508, a first DC bias current of the input transistor is adjusted to form a substantially constant second DC bias current of the cascode transistor. In various embodiments, the DC bias current may be adjusted using a feedback loop as described above with respect to the embodiments of FIGS. 2A, 2E, 3A and 3B.

[0040] FIG. 6A illustrates an embodiment radar transceiver 602 that utilizes an embodiment power amplifier as described according to the various embodiments above. As shown, radar transceiver 602 includes PLL 604 that generates an RF signal s.sub.LO(t), which may be frequency-modulated using frequency modulation techniques know in the art. For example, in a frequency modulated continuous wave (FMCW) radar system, RF signal s.sub.LO(t) may be frequency modulated to have a frequency ramp of increasing and/or decreasing frequency. Alternatively, RF signal s.sub.LO(t) may be frequency modulated according to other shapes and patterns, such as rectangular and sinusoidal. In radar applications, the LO signal may be in the Super High Frequency (SHF) or the Extremely High Frequency (EHF) band (e.g., between 76 GHz and 81 GHz in automotive applications).

[0041] The LO signal s.sub.LO(t) is processed in the transmit signal path as well as in the receive signal path. The transmit signal s.sub.RF(t), which is radiated by the TX antenna 612, is generated by amplifying the LO signal s.sub.LO(t), for example, using an RF power amplifier 620 according to embodiments of the present invention described above. The output of power amplifier 620 is coupled to the TX antenna 612. The received signal y.sub.RF(t), which is provided by the RX antenna 614, is provided to a mixer 624. In the present example, the received signal y.sub.RF(t) (i.e., the antenna signal) is pre-amplified by RF amplifier 623 (gain g), so that the mixer receives the amplified signal g.Math.y.sub.RF(t) at its RF input. The mixer 624 further receives the LO signal s.sub.LO(t) at its reference input and is configured to down-convert the amplified signal g.Math.y.sub.RF(t) into the base band. The resulting base-band signal at the mixer output is denoted as y.sub.BB(t). The base-band signal y.sub.BB(t) is further processed by the analog base band signal processing chain 630, which basically includes one or more filters (e.g., a band-pass filter 631) to remove undesired side bands and image frequencies as well as one or more amplifiers such as amplifier 632. The analog output signal, which may be supplied to an analog-to-digital converter is denoted as y(t). radar transceiver 602.

[0042] In the present example, the mixer 624 down-converts the RF signal g.Math.y.sub.RF(t) (amplified antenna signal) into the base band. The respective base band signal (mixer output signal) is denoted by y.sub.BB(t). The down-conversion may be accomplished in a single stage (i.e., from the RF band into the base band) or via one or more intermediate stages (from the RF band into an IF band and subsequently into the base band). It should be understood that radar transceiver 602 is just one of many possible systems that may utilize power amplifiers according to embodiments of the present invention. Embodiment power amplifiers may be used in other types of systems, such as RF transmitters and transceivers used in communication systems.

[0043] FIG. 6B illustrates an embodiment RF transceiver 662 that utilizes an embodiment power amplifier as described according to the various embodiments above. RF transceiver 602 may be used, for example, in an RF communication system. As shown, RF transceiver 652 includes a baseband processor 654 that is coupled to a transmit signal path and a receive signal path. The transmit signal path includes a digital-to-analog converter (DAC) 656, upconverter 658, power amplifier 660 transmit filter 662 that may be coupled to transmit antenna 664. In various embodiments, power amplifier 660 may be implemented using a power amplifier described in embodiments above. During operation, baseband processor 654 generates a baseband signal in the digital domain, which is converted to the analog domain using DAC 656 to form an analog baseband signal. DAC 656 may be implemented using DAC circuits known in the art. The analog baseband signal is upconverted to an RF frequency using upconverter 658, which may be implemented, for example, using one or more RF mixing circuits. The output of the upconverter is amplified using embodiment power amplifier 660, and the resulting amplified RF signal is filtered using transmit filter 662 and provided to transmit antenna 664. Transmit filter 662 may be implemented using RF filter circuits and systems known in the art including, but not limited to passive LC filters, surface acoustic wave (SAW) filters.

[0044] The receive signal path includes an analog-to-to digital converter (ADC) 674, downconverter 672, low noise amplifier (LNA) 670 and receive filter 668 that may be coupled to a receive antenna 666. During operation, receive filter 668 filters an RF signal received by receive antenna 666. The filtered received signal is filtered by LNA 670, the output of which downconverted by downconverter 672. The downconverted analog signal is digitized by ADC 647, and the digitized output is processed by baseband processor 654. Receive filter 668 may be implemented RF filter circuits and systems known in the art including, but not limited to passive LC filters, surface acoustic wave (SAW) filters; downconverter 672 may by implemented using downconverter circuits and systems known in the art, such as one or more RF mixer circuits, and ADC 674 may be implemented using ADC circuits known in the art.

[0045] In some embodiments, all of the circuitry of RF transceiver 662 may be implemented on a single monolithic semiconductor integrated circuit. Alternatively, the components of RF transceiver 662 may be partitioned using multiple components. It should be understood that radar RF transceiver 662 is just one of many systems that may utilize power amplifiers according to embodiments of the present invention.

[0046] Embodiments of the present invention are summarized here. Other embodiments can also be understood from the entirety of the specification and the claims filed herein.

[0047] Example 1. A method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor, the method including: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.

[0048] Example 2. The method of example 1, further including: generating a bias reference voltage; and comparing a voltage of a reference node of the cascode transistor to the bias reference voltage, where adjusting the first DC bias current includes adjusting the first DC bias current until the bias reference voltage and the voltage of the reference node of the cascode transistor are substantially at a same DC voltage.

[0049] Example 3. The method of example 2, where: comparing the voltage of the reference node of the cascode transistor to the bias reference voltage includes using a transconductance amplifier; and adjusting the first DC bias current further includes providing a bias voltage for the input transistor using a diode connected transistor coupled to an output of the transconductance amplifier and to the control node of the input transistor.

[0050] Example 4. The method of one of examples 2 or 3, where generating the bias reference voltage includes: applying a reference current to a cascode reference transistor; and applying a same cascode bias voltage to a control node of the cascode transistor and a control node of the cascode reference transistor.

[0051] Example 5. The method of one of examples 1 to 4, where; the input transistor includes a first input transistor and a second input transistor; the cascode transistor includes a first cascode transistor and a second cascode transistor, where the first input transistor has an output node coupled to a load path of the first cascode transistor, and the second input transistor has an output node coupled to a load path of the second cascode transistor; and providing the output signal to the load includes providing a first phase of the output signal to the load from the first cascode transistor, and providing a second phase of the output signal to the load from the second cascode transistor.

[0052] Example 6. The method of example 5, where: receiving the millimeter-wave transmit signal includes receiving the millimeter-wave transmit signal via a first transformer coupled between a control node of the first input transistor and a control node of the second input transistor; and providing the output signal to the load includes providing the output signal to the load via a second transformer coupled between an output node of the first cascode transistor and an output node of the second cascode transistor.

[0053] Example 7. The method of one of examples 1 to 6, further including limiting the first DC bias current.

[0054] Example 8. The method of one of examples 1 to 7, further including, using an interstage matching network coupled between the output node of the input transistor and a reference node of the cascode transistor, modifying an impedance seen by the output node of the input transistor, where the interstage matching network at least partially compensates for an increased impedance caused by a parasitic inductance coupled between the output node of the input transistor and the reference node of the cascode transistor.

[0055] Example 9. A millimeter-wave power amplifier including: a cascode transistor having an output node configured to be coupled to a load; an input transistor having an output node coupled to a load path of the cascode transistor; and a bias circuit coupled to the input transistor and the cascode transistor, the bias circuit configured to adjust a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.

[0056] Example 10. The millimeter-wave power amplifier of example 9, where the bias circuit includes: a bias reference voltage generator configured to produce a bias reference voltage; and a feedback circuit configured to adjust the first DC bias current until the bias reference voltage and a voltage of a reference node of the cascode transistor have substantially a same DC voltage.

[0057] Example 11. The millimeter-wave power amplifier of example 10, where: the feedback circuit includes a transconductance amplifier having a first input coupled to the bias reference voltage generator and a second input coupled to the reference node of the cascode transistor; and a diode connected transistor coupled to an output of the transconductance amplifier and a control node of the input transistor.

[0058] Example 12. The millimeter-wave power amplifier of example 10 or 11, where the bias reference voltage generator includes a cascode reference transistor having a load path coupled to reference current source, and a control node coupled to a cascode bias node configured to provide a cascode reference voltage, where a control node of the cascode transistor is configured to receive a same cascode reference voltage.

[0059] Example 13. The millimeter-wave power amplifier of one of examples 9 to 12, where: the input transistor includes a first input transistor and a second input transistor; and the cascode transistor includes a first cascode transistor and a second cascode transistor, where the first input transistor has an output node coupled to a load path of the first cascode transistor, and the second input transistor has an output node coupled to a load path of the second cascode transistor.

[0060] Example 14. The millimeter-wave power amplifier of example 13, further including: a first transformer having a first winding coupled between a control node of the first input transistor and a control node of the second input transistor, and a second winding configured to receive an RF input signal; and a second transformer coupled between the output node of the first cascode transistor and an output node of the second cascode transistor.

[0061] Example 15. The millimeter-wave power amplifier of one of examples 9 to 14, further including a current limiting circuit configured to limit the first DC bias current to a first predetermined limit current.

[0062] Example 16. The millimeter-wave power amplifier of one of examples 9 to 15, where the input transistor and the cascode transistor each include a bipolar junction transistor.

[0063] Example 17. A millimeter-wave power amplifier including: a first signal path including a first input transistor, and a first cascode transistor having a first reference node coupled to a first output node of the first input transistor; a second signal path including a second input transistor, and a second cascode transistor having a second reference node coupled to a second output node of the second input transistor; a further cascode transistor configured to receive a reference current at a bias reference node; a first amplifier having a first input coupled to the bias reference node and a second input coupled to the first reference node of the first cascode transistor and to the second reference node of the second cascode transistor; and a first diode connected transistor coupled to an output of the first amplifier and coupled to a first control node of the first input transistor and a second control node of the second input transistor.

[0064] Example 18. The millimeter-wave power amplifier of example 17, further including a current limiting circuit coupled between the output of the first amplifier and the first diode connected transistor.

[0065] Example 19. The millimeter-wave power amplifier of one of examples 17 or 18, further including an input transformer including: a first winding having a first end coupled to the first control node of the first input transistor, a second end coupled to the second control node of the input second transistor, and a center tap coupled to the first diode connected transistor; and a second winding configured to receive an RF input signal.

[0066] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.