FAST-SWITCHING POWER MANAGEMENT INTEGRATED CIRCUIT

Abstract

A fast-switching power management integrated circuit (PMIC) is provided. The PMIC is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying a radio frequency (RF) signal modulated in multiple time intervals. Herein, the PMIC is configured to increase or decrease the APT voltage from a present voltage level in a present one of the time intervals to a future voltage level in an upcoming one of the time intervals with very short switching interval (e.g., <20 nanoseconds). When the APT voltage transitions from the present voltage level to the future voltage level, the PMIC opportunistically activates a voltage amplifier to help ensure proper operation of the power amplifier circuit (e.g., maintain the APT voltage at the present level and reduce ripple in the APT voltage). As a result, the PMIC can switch the APT voltage frequently and rapidly with reduced inrush current.

Claims

1. A power management integrated circuit (PMIC) comprising: a voltage output that outputs an average power tracking (APT) voltage to a power amplifier circuit for amplifying a radio frequency (RF) signal modulated in a plurality of modulation units each comprising a plurality of time intervals; an offset circuit coupled to the voltage output and configured to change the APT voltage from a present voltage level in a present time interval among the plurality of time intervals to a future voltage level in an upcoming time interval among the plurality of time intervals during a transition interval that falls within one of the present time interval and the upcoming time interval; and a voltage amplifier coupled to an input of the offset circuit, the voltage amplifier is activated at a start of the transition interval and deactivated at an end of the transition interval to generate a modulated voltage at the input of the offset circuit based on an amplifier target voltage determined to cause the modulated voltage to be higher than or equal to a headroom voltage at the end of the transition interval.

2. The PMIC of claim 1, further comprising a control circuit configured to: determine the start and the end of the transition interval based on the present voltage level and the future voltage level of the APT voltage; determine the amplifier target voltage to be equal to a sum of the future voltage level and a markup voltage; activate the voltage amplifier at the start of the transition interval; and deactivate the voltage amplifier at the end of the transition interval.

3. The PMIC of claim 2, wherein the control circuit is further configured to: determine that the future voltage level of the APT voltage is higher than the present voltage level of the APT voltage; determine the start of the transition interval to be at a boundary between the present time interval and the upcoming time interval; determine the end of the transition interval to be later than the boundary between the present time interval and the upcoming time interval; determine the markup voltage to be equal to the headroom voltage; and cause the offset circuit to increase the APT voltage from the present voltage level to the future voltage level by the end of the transition interval.

4. The PMIC of claim 2, wherein the control circuit is further configured to: determine that the future voltage level of the APT voltage is lower than the present voltage level of the APT voltage and the headroom voltage is lower than a differential between the present voltage level and the future voltage level; determine the start of the transition interval to be earlier than a boundary between the present time interval and the upcoming time interval; determine the end of the transition interval to be at the boundary between the present time interval and the upcoming time interval; determine the markup voltage to be equal to zero; and cause the offset circuit to decrease the APT voltage from the present voltage level to the future voltage level by the end of the transition interval.

5. The PMIC of claim 2, wherein the control circuit is further configured to: determine that the future voltage level of the APT voltage is lower than the present voltage level of the APT voltage and the headroom voltage is higher than or equal to a differential between the present voltage level and the future voltage level; determine the start of the transition interval to be earlier than a boundary between the present time interval and the upcoming time interval; determine the end of the transition interval to be at the boundary between the present time interval and the upcoming time interval; determine the markup voltage to be equal to the headroom voltage subtracted by the differential between the present voltage level and the future voltage level; and cause the offset circuit to decrease the APT voltage from the present voltage level to the future voltage level by the end of the transition interval.

6. The PMIC of claim 2, wherein the control circuit is further configured to receive, during the present time interval, an indication that indicates the future voltage level of the APT voltage in the upcoming time interval.

7. The PMIC of claim 2, wherein the control circuit is further configured to receive, during a present one of the plurality of modulation units, a profile indication that indicates a selected power profile for an upcoming one of the plurality of modulation units, the selected power profile comprises a plurality of future voltage levels each corresponding to a respective one of the plurality of time intervals in the upcoming one of the plurality of modulation units.

8. The PMIC of claim 7, further comprising a memory circuit configured to store a profile lookup table (LUT) comprising a plurality of predetermined power profiles, wherein the control circuit is further configured to retrieve the selected power profile from the profile LUT based on the received indication.

9. The PMIC of claim 1, wherein: the plurality of modulation units each corresponds to a time division duplex, TDD, time slot; and the plurality of time intervals in each of the plurality of modulation units corresponds to an orthogonal frequency division multiplexing, OFDM, symbol.

10. A wireless communication circuit comprising a power management integrated circuit (PMIC) comprising: a voltage output that outputs an average power tracking (APT) voltage for amplifying a radio frequency, RF, signal modulated in a plurality of modulation units each comprising a plurality of time intervals; an offset circuit coupled to the voltage output and configured to change the APT voltage from a present voltage level in a present time interval among the plurality of time intervals to a future voltage level in an upcoming time interval among the plurality of time intervals during a transition interval that falls within one of the present time interval and the upcoming time interval; and a voltage amplifier coupled to an input of the offset circuit, the voltage amplifier is activated at a start of the transition interval and deactivated at an end of the transition interval to generate a modulated voltage at the input of the offset circuit based on an amplifier target voltage determined to cause the modulated voltage to be higher than or equal to a headroom voltage at the end of the transition interval.

11. The wireless communication circuit of claim 10, wherein the PMIC further comprises a control circuit configured to: determine the start and the end of the transition interval based on the present voltage level and the future voltage level of the APT voltage; determine the amplifier target voltage to be equal to a sum of the future voltage level and a markup voltage; activate the voltage amplifier at the start of the transition interval; and deactivate the voltage amplifier at the end of the transition interval.

12. The wireless communication circuit of claim 11, wherein the control circuit is further configured to: determine that the future voltage level of the APT voltage is higher than the present voltage level of the APT voltage; determine the start of the transition interval to be at a boundary between the present time interval and the upcoming time interval; determine the end of the transition interval to be later than the boundary between the present time interval and the upcoming time interval; determine the markup voltage to be equal to the headroom voltage; and cause the offset circuit to increase the APT voltage from the present voltage level to the future voltage level by the end of the transition interval.

13. The wireless communication circuit of claim 11, wherein the control circuit is further configured to: determine that the future voltage level of the APT voltage is lower than the present voltage level of the APT voltage and the headroom voltage is lower than a differential between the present voltage level and the future voltage level; determine the start of the transition interval to be earlier than a boundary between the present time interval and the upcoming time interval; determine the end of the transition interval to be at the boundary between the present time interval and the upcoming time interval; determine the markup voltage to be equal to zero; and cause the offset circuit to decrease the APT voltage from the present voltage level to the future voltage level by the end of the transition interval.

14. The wireless communication circuit of claim 11, wherein the control circuit is further configured to: determine that the future voltage level of the APT voltage is lower than the present voltage level of the APT voltage and the headroom voltage is higher than or equal to a differential between the present voltage level and the future voltage level; determine the start of the transition interval to be earlier than a boundary between the present time interval and the upcoming time interval; determine the end of the transition interval to be at the boundary between the present time interval and the upcoming time interval; determine the markup voltage to be equal to the headroom voltage subtracted by the differential between the present voltage level and the future voltage level; and cause the offset circuit to decrease the APT voltage from the present voltage level to the future voltage level by the end of the transition interval.

15. The wireless communication circuit of claim 11, wherein the control circuit is further configured to receive, during the present time interval, an indication that indicates the future voltage level of the APT voltage in the upcoming time interval.

16. The wireless communication circuit of claim 11, wherein the control circuit is further configured to receive, during a present one of the plurality of modulation units, a profile indication that indicates a selected power profile for an upcoming one of the plurality of modulation units, the selected power profile comprises a plurality of future voltage levels each corresponding to a respective one of the plurality of time intervals in the upcoming one of the plurality of modulation units.

17. The wireless communication circuit of claim 16, wherein the PMIC further comprises a memory circuit configured to store a profile lookup table, LUT, comprising a plurality of predetermined power profiles, wherein the control circuit is further configured to retrieve the selected power profile from the profile LUT based on the received indication.

18. The wireless communication circuit of claim 10, wherein: the plurality of modulation units each corresponds to a time division duplex (TDD) time slot; and the plurality of time intervals in each of the plurality of modulation units corresponds to an orthogonal frequency division multiplexing (OFDM) symbol.

19. The wireless communication circuit of claim 10, further comprising a transceiver circuit configured to: generate the RF signal and modulate the RF signal in the plurality of modulation units each comprising the plurality of time intervals; and provide a modulated target voltage to the PMIC to indicate the future voltage level in the upcoming time interval among the plurality of time intervals.

20. The wireless communication circuit of claim 10, further comprising a power amplifier circuit configured to amplify the RF signal in each of the plurality of time intervals based on the APT voltage.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0013] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0014] FIG. 1 is a schematic diagram of an exemplary orthogonal frequency division multiplexing (OFDM) time-frequency grid illustrating at least one resource block (RB) for physical resource allocation;

[0015] FIG. 2 is a schematic diagram of an exemplary power management integrated circuit (PMIC) configured according to embodiments of the present disclosure to support fast average power tracking (APT) voltage switching;

[0016] FIG. 3 is a timing diagram providing an exemplary illustration of the PMIC of FIG. 2 configured according to an embodiment of the present disclosure to increase the APT voltage from a present voltage level to a future voltage level;

[0017] FIG. 4 is a timing diagram providing an exemplary illustration of the PMIC of FIG. 2 configured according to an embodiment of the present disclosure to decrease the APT voltage from a present voltage level to a future voltage level;

[0018] FIG. 5 is a timing diagram providing an exemplary illustration of the PMIC of FIG. 2 configured according to another embodiment of the present disclosure to decrease the APT voltage from a present voltage level to a future voltage level;

[0019] FIGS. 6A and 6B are block diagrams providing exemplary illustrations of some power profiles that may be used by the PMIC of FIG. 2 for enabling fast APT voltage switching; and

[0020] FIG. 7 is a schematic diagram of an exemplary user element wherein the PMIC of FIG. 2 can be provided.

DETAILED DESCRIPTION

[0021] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0022] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0023] It will be understood that when an element such as a layer, region, or substrate is referred to as being on or extending onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly on or extending directly onto another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being over or extending over another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being directly over or extending directly over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being directly connected or directly coupled to another element, there are no intervening elements present.

[0024] Relative terms such as below or above or upper or lower or horizontal or vertical may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms a, an, and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0027] Embodiments of the disclosure relate to a fast-switching power management integrated circuit (PMIC). The PMIC is configured to provide an average power tracking (APT) voltage to a power amplifier circuit for amplifying a radio frequency (RF) signal modulated in multiple time intervals. Herein, the PMIC is configured to increase or decrease the APT voltage from a present voltage level in a present one of the time intervals to a future voltage level in an upcoming one of the time intervals with a very short switching interval (e.g., <20 nanoseconds). When the APT voltage transitions from the present voltage level to the future voltage level, the PMIC opportunistically activates a voltage amplifier to help ensure proper operation of the power amplifier circuit (e.g., maintain the APT voltage at the present level and reduce ripple in the APT voltage). As a result, the PMIC can switch the APT voltage frequently and rapidly with reduced inrush current.

[0028] In this regard, FIG. 2 is a schematic diagram of an exemplary PMIC 24, which is provided in a wireless communication circuit 25 and configured according to embodiments of the present disclosure to support fast APT voltage switching. The PMIC 24 includes a voltage output 26 that outputs an APT voltage V.sub.CC to a power amplifier circuit 28 in the wireless communication circuit 25. The power amplifier circuit 28 is configured to amplify an RF signal 30 based on the APT voltage V.sub.CC. The RF signal 30, which may be generated by a transceiver circuit 31 in the wireless communication circuit 25, is modulated in multiple modulation units, each of which is further divided into multiple time intervals. In the context of the present disclosure, the modulation units are equivalent to time-division duplex (TDD) time slots or mini time slots, and the time intervals inside each of the modulation units are equivalent to orthogonal frequency division multiplexing (OFDM) symbols, such as the OFDM symbols 20(1)-20(N) in FIG. 1. In this regard, each of the time intervals can be modulated to carry a data payload (referred herein as a data symbol) and a reference signal (referred herein as a reference symbol), such as a demodulation reference signal (DMRS), a sounding reference signal (SRS), and so on.

[0029] Given that the power amplifier circuit 28 needs to amplify the data symbols and the reference symbols to different power levels, the PMIC 24 may need to adapt (increase or decrease) the APT voltage V.sub.CC on a per-symbol basis. Moreover, as previously described in FIG. 1, the PMIC 24 must complete the APT voltage V.sub.CC within the respective cyclic prefix (CP) in each of the OFDM symbols 20(1)-20(N).

[0030] The PMIC 24 includes a voltage amplifier 32 (denoted as VA) and an offset circuit 34. The voltage amplifier 32 is coupled to an input 36 of the offset circuit 34 and the offset circuit 34 is coupled to the voltage output 26. In the context of the present disclosure, the power amplifier circuit 28 is assumed to have a much higher bandwidth than that of the offset circuit 34. As described in detail below, the offset circuit 34 is configured to change (increase or decrease) the APT voltage V.sub.CC from a present voltage level (denoted as V.sub.CC(N-1) in FIGS. 3 to 5) to a future voltage level (denoted as V.sub.CC(N) in FIGS. 3 to 5) between a pair of adjacent time intervals (denoted as S.sub.N-1 and S.sub.N in FIGS. 3 to 5). For the sake of distinction, the time intervals S.sub.N-1 and S.sub.N are also referred to as a present time interval and an upcoming time interval, respectively.

[0031] More specifically, the offset circuit 34 will cause the APT voltage V.sub.CC to change from the present voltage level V.sub.CC(N-1) in the present time interval S.sub.N-1 to the future voltage level V.sub.CC(N) in the upcoming time interval S.sub.N during a transition interval (denoted as TP in FIGS. 3 to 5). Depending on whether the APT voltage V.sub.CC is increasing or decreasing from the present time interval S.sub.N-1 to the upcoming time interval S.sub.N, the transition interval TP can be located either in the present time interval S.sub.N-1 or in the upcoming time interval S.sub.N to ensure that the APT voltage V.sub.CC can reach the future voltage level V.sub.CC(N) by the CP of the upcoming time interval S.sub.N.

[0032] As further illustrated in FIGS. 3 to 5, while the APT voltage V.sub.CC transitions from the present voltage level V.sub.CC(N-1) to the future voltage level V.sub.CC(N) during the transition interval TP, the voltage amplifier 32 is activated at a start of the transition interval TP (denoted as T.sub.1) and deactivated at an end of the transition interval TP (denoted as T.sub.2) to ensure proper operation of the power amplifier circuit 28. According to an embodiment of the present disclosure, the voltage amplifier 32 will provide a modulated voltage V.sub.AMP at an input 36 of the offset circuit 34. In a non-limiting example, the voltage amplifier 32 is configured to generate the modulated voltage V.sub.AMP based on an amplifier target voltage V.sub.TGT-AMP and one of a lower supply voltage V.sub.SUPL and a higher supply voltage V.sub.SUPH (V.sub.SUPH>V.sub.SUPL).

[0033] As discussed in detailed examples in FIGS. 3 to 5, the amplifier target voltage V.sub.TGT-AMP is so determined to ensure that the voltage amplifier 32 can maintain the modulated voltage V.sub.AMP at or above a headroom voltage (denoted as V.sub.NHEAD in FIGS. 3 to 5), which is greater than 0 V, at the end T.sub.2 of the transition interval TP. As a result, the voltage amplifier 32 can maintain the APT voltage V.sub.CC at the present voltage level V.sub.CC(N-1) and suppress ripple in the APT voltage V.sub.CC during the transition interval TP to thereby ensure the proper operation of the power amplifier circuit 28 during the transition interval TP.

[0034] According to an embodiment of the present disclosure, the PMIC 24 can include a control circuit 38, which can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In one aspect, the control circuit 38 may be configured to determine whether the transition interval TP should be within the present time interval S.sub.N-1 or the upcoming time interval S.sub.N based on a differential V.sub.CC between the present voltage level V.sub.CC(N-1) and the future voltage level V.sub.CC(N) (V.sub.CC=V.sub.CC(N-1)V.sub.CC(N). Understandably, the differential V.sub.CC will be positive when the present voltage level V.sub.CC(N-1) is higher than the future voltage level V.sub.CC(N) or negative when the present voltage level V.sub.CC(N-1) is lower than the future voltage level V.sub.CC(N). In a non-limiting example, the control circuit 38 can receive a modulated target voltage V.sub.TGT, which indicates the future voltage level V.sub.CC(N) in the upcoming time interval S.sub.N, from the transceiver circuit 31. Accordingly, the control circuit 38 may control the offset circuit 34 (e.g., via a control signal 40) to transition from the present voltage level V.sub.CC(N-1) to the future voltage level V.sub.CC(N) during the transition interval TP.

[0035] In another aspect, the control circuit 38 may also be configured to determine the amplifier target voltage V.sub.TGT-AMP based on the determined differential V.sub.CC. In a non-limiting example, when the future voltage level V.sub.CC(N) is higher than the present voltage level V.sub.CC(N-1), as illustrated in FIG. 3, the amplifier target voltage V.sub.TGT-AMP is equal to a sum of the future voltage level V.sub.CC(N) and a markup voltage (denoted as V.sub.DIFF), as shown in equation (Eq. 1) below. In another non-limiting example, when the future voltage level V.sub.CC(N) is lower than the present voltage level V.sub.CC(N-1), as illustrated in FIGS. 4 and 5, the amplifier target voltage V.sub.TGT-AMP is equal to a sum of the present voltage level V.sub.CC(N-1) and the markup voltage V.sub.DIFF, as shown in equation (Eq. 2) below.

[00001]$\begin{array}{cc}{V}_{\mathrm{TGT}-\mathrm{AMP}}=V_{\mathrm{CC}\left(N\right)}+V_{\mathrm{DIFF}}& \left(\mathrm{Eq}.1\right)\end{array}$$\begin{array}{cc}{V}_{\mathrm{TGT}-\mathrm{AMP}}=V_{\mathrm{CC}\left(N-1\right)}+V_{\mathrm{DIFF}}& \left(\mathrm{Eq}.2\right)\end{array}$

[0036] In the equations (Eq. 1 and Eq. 2), the markup voltage V.sub.DIFF can be of different values depending on how the APT voltage V.sub.CC will change from the present time interval S.sub.N-1 to the upcoming time interval S.sub.N. In this regard, by changing the amplifier target voltage V.sub.TGT-AMP and, more specifically the markup voltage V.sub.DIFF, the control circuit 38 can cause the voltage amplifier 32 to generate the modulated voltage V.sub.AMP at appropriate levels during the transition interval TP to maintain proper operation of the power amplifier circuit 28.

[0037] In yet another aspect, the control circuit 38 may be further configured to activate the voltage amplifier 32 at the start T.sub.1 of the transition interval TP and deactivate the voltage amplifier 32 at the end T.sub.2 of the transition interval TP. In a non-limiting example, the control circuit 38 can cause the voltage amplifier 32 to be deactivated in response to receiving the lower supply voltage V.sub.SUPL or activated in response to receiving the higher supply voltage V.sub.SUPH. By controlling the offset circuit 34 to change the APT voltage V.sub.CC and opportunistically activating/deactivating the voltage amplifier 32 to ensure proper operation of the power amplifier circuit 28 during the transition interval TP, the PMIC 24 can switch the APT voltage V.sub.CC efficiently under the increasingly stringent switching time requirements (e.g., <20 ns).

[0038] The PMIC 24 also includes a multi-level charge pump (MCP) 42. The MCP 42, which may be a direct current (DC)-DC buck-boost converter, is configured to generate a low-frequency voltage V.sub.DC (e.g., DC voltage) based on a battery voltage V.sub.BAT. Specifically, the MCP 42 may operate in a buck mode to generate the low-frequency voltage V.sub.DC at 0V.sub.BAT or 1V.sub.BAT, or in a boost mode to generate the low-frequency voltage V.sub.DC at 2V.sub.BAT. The MCP 42 may be configured to toggle between the buck mode and the boost mode based on a particular duty cycle (e.g., 20% @0V.sub.BAT, 30% @1V.sub.BAT, and 50% @2V.sub.BAT). As such, the MCP 42 may be controlled to generate the low-frequency voltage V.sub.DC at a desired level.

[0039] In an embodiment, the control circuit 38 may be further configured to generate an offset target voltage V.sub.TGT-OFF based on the modulated target voltage V.sub.TGT. The offset target voltage V.sub.TGT-OFF may indicate the future voltage level V.sub.CC(N) of the APT voltage V.sub.CC. Accordingly, the MCP 42 may determine and operate based on a corresponding duty cycle to generate the low-frequency voltage V.sub.DC at the desired level as indicated by the offset target voltage V.sub.TGT-OFF.

[0040] The PMIC 24 also includes a power inductor L.sub.P. The power inductor L.sub.P is coupled between the MCP 42 and the voltage output 26 and is configured to induce a low-frequency current I.sub.DC (e.g., a DC current) based on the low-frequency voltage V.sub.DC. Understandably, the low-frequency current I.sub.DC that may be induced is a function of the low-frequency voltage V.sub.DC and an inductance of the power inductor L.sub.P. Accordingly, the control circuit 38 may further change the low-frequency current I.sub.DC based on the offset target voltage V.sub.TGT-OFF. In an embodiment, the MCP 42 may receive feedback from the APT voltage V.sub.CC.

[0041] Herein, the offset circuit 34 includes an offset capacitor C.sub.OFF and a bypass switch S.sub.BYP. The offset capacitor C.sub.OFF is coupled between the input 36 and the voltage output 26, and the bypass switch S.sub.BYP is coupled between the input 36 and a ground (GND).

[0042] Under one operating scenario, the APT voltage V.sub.CC is set to increase from the present voltage level V.sub.CC(N-1) in the present time interval S.sub.N-1 to the future voltage level V.sub.CC(N) in the upcoming time interval S.sub.N (V.sub.CC(N-1)<V.sub.CC(N)). In this regard, the control circuit 38 will set the offset target voltage V.sub.TGT-OFF to the future voltage level V.sub.CC(N) of the APT voltage V.sub.CC to cause the low-frequency current I.sub.DC to be generated at a desired amount to thereby charge the offset capacitor C.sub.OFF to the future voltage level V.sub.CC(N).

[0043] The control circuit 38 will open the bypass switch S.sub.BYP and activate the voltage amplifier 32 at the start of the transition interval TP to generate the amplifier target voltage V.sub.TGT-AMP at a level higher than the future voltage level V.sub.CC(N) such that a current I.sub.TRAN can flow from the MCP 42 through the offset capacitor C.sub.OFF and sink in the voltage amplifier 32. In a non-limiting example, the PMIC 24 can include an auxiliary circuit 44, which can provide additional current to help maintain the modulated voltage V.sub.AMP in the presence of the current I.sub.TRAN. As a result, the current I.sub.TRAN will gradually charge the offset capacitor C.sub.OFF to the future voltage level V.sub.CC(N) during the transition interval TP. When the offset capacitor C.sub.OFF is charged up to the future voltage level V.sub.CC(N) at the end of the transition interval TP, the control circuit 38 deactivates the voltage amplifier 32 and closes the bypass switch S.sub.BYP. Thereafter, the offset capacitor C.sub.OFF and the MCP 42 will maintain the APT voltage V.sub.CC at the future voltage level V.sub.CC(N) in the remainder of the upcoming time interval S.sub.N.

[0044] The operating scenario described above can be graphically illustrated in FIG. 3. FIG. 3 is a timing diagram providing an exemplary illustration as to how the PMIC 24 of FIG. 2 operates under the above-described operating scenario to increase the APT voltage V.sub.CC. Elements in FIG. 2 are referenced in FIG. 3 and will not be re-described herein.

[0045] As illustrated, the transition interval TP falls completely within the upcoming time interval S.sub.N, wherein the start T.sub.1 of the transition interval TP is aligned with a boundary T.sub.0 (a.k.a. a starting time of the CP in the upcoming time interval S.sub.N) between the present time interval S.sub.N-1 and the upcoming time interval S.sub.N, and the end T.sub.2 of the transition interval TP comes after time T.sub.3 (a.k.a. an ending time of the CP in the upcoming time interval S.sub.N). Understandably, the CP is typically much shorter than the transition interval TP. Herein, the modulated target voltage V.sub.TGT indicates that the APT voltage V.sub.CC will increase from the present voltage level V.sub.CC(N-1) (e.g., 2.3 V) in the present time interval S.sub.N-1 to the future voltage level V.sub.CC(N) (e.g., 2.9 V) in the upcoming time interval S.sub.N. Accordingly, the control circuit 38 determines the offset target voltage V.sub.TGT-OFF to be equal to the future voltage level V.sub.CC(N).

[0046] As for the amplifier target voltage V.sub.TGT-AMP, the control circuit 38 is configured to set the markup voltage V.sub.DIFF in the equation (Eq. 1) to be equal to the headroom voltage V.sub.NHEAD (V.sub.TGT-AMP=V.sub.CC(N)+V.sub.NHEAD). At time T.sub.1, the control circuit 38 opens the bypass switch S.sub.BYP and activates the voltage amplifier 32 (e.g., by coupling the higher supply voltage V.sub.SUPH to the voltage amplifier 32). Accordingly, the voltage amplifier 32 will generate the modulated voltage V.sub.AMP at the input 36 in accordance with the amplifier target voltage V.sub.TGT-AMP. In a non-limiting example, the voltage amplifier 32, with assistance from the auxiliary circuit 44, can quickly drive the modulated voltage V.sub.AMP from a GND level to the differential V.sub.CC (V.sub.CC<0) at time T.sub.3 to help stabilize the APT voltage V.sub.CC during the transition interval TP. Thereafter, the voltage amplifier 32 gradually decreases the modulated voltage V.sub.AMP to the headroom voltage V.sub.NHEAD at time T.sub.2.

[0047] Starting at time T.sub.1, the offset capacitor C.sub.OFF is gradually charged up to reach the future voltage level V.sub.CC(N) at time T.sub.2. Accordingly, at time T.sub.2, the control circuit 38 closes the bypass switch S.sub.BYP and deactivates the voltage amplifier 32 to let the modulated voltage V.sub.AMP return to the GND level. The APT voltage V.sub.CC, which equals a sum of the modulated voltage V.sub.AMP and the offset voltage VOFF, will settle at the future voltage level V.sub.CC(N) at time T.sub.3. Notably, since the voltage amplifier 32 maintains the modulated voltage V.sub.AMP at or above the headroom voltage V.sub.NHEAD while the bypass switch S.sub.BYP is toggled, the APT voltage V.sub.CC will not drop below the headroom voltage V.sub.NHEAD, thus ensuring proper operation of the power amplifier circuit 28.

[0048] With reference back to FIG. 2, under another operating scenario, the APT voltage V.sub.CC is set to decrease from the present voltage level V.sub.CC(N-1) in the present time interval S.sub.N-1 to the future voltage level V.sub.CC(N) in the upcoming time interval S.sub.N (V.sub.CC(N-1)>V.sub.CC(N). In this regard, the control circuit 38 will set the offset target voltage V.sub.TGT-OFF to the future voltage level V.sub.CC(N) of the APT voltage V.sub.CC to cause the low-frequency current I.sub.DC to be generated at a desired amount to thereby cause the offset capacitor C.sub.OFF to be discharged to the future voltage level V.sub.CC(N).

[0049] The control circuit 38 will open the bypass switch S.sub.BYP and activate the voltage amplifier 32 at the start of the transition interval TP to generate the amplifier target voltage V.sub.TGT-AMP at the present voltage level V.sub.CC(N-1) such that the current I.sub.TRAN can flow from the voltage amplifier 32 through the offset capacitor C.sub.OFF and return to the MCP 42 and/or the power amplifier circuit 28. In a non-limiting example, the auxiliary circuit 44 can provide additional current to help maintain the modulated voltage V.sub.AMP in the presence of the current I.sub.TRAN. As a result, the offset capacitor C.sub.OFF will be gradually discharged to the future voltage level V.sub.CC(N) during the transition interval TP. When the offset capacitor C.sub.OFF is discharged to the future voltage level V.sub.CC(N) at the end of the transition interval TP, the control circuit 38 deactivates the voltage amplifier 32 and closes the bypass switch S.sub.BYP. Thereafter, the offset capacitor C.sub.OFF and the MCP 42 will maintain the APT voltage V.sub.CC at the future voltage level V.sub.CC(N) in the remainder of the upcoming time interval S.sub.N.

[0050] The operating scenario described above can be graphically illustrated in FIGS. 4 and 5. FIG. 4 is a timing diagram providing an exemplary illustration as to how the PMIC 24 of FIG. 2 operates under one possibility of the above-described operating scenario to decrease the APT voltage V.sub.CC. More specifically, FIG. 4 illustrates a situation where the headroom voltage V.sub.NHEAD (e.g., 0.4 V) is lower than the differential V.sub.CC (e.g., 0.6 V) between the present voltage level V.sub.CC(N-1) and the future voltage level V.sub.CC(N) (V.sub.NHEAD<V.sub.CC). Elements in FIG. 2 are referenced in FIG. 4 and will not be re-described herein.

[0051] As illustrated, the transition interval TP falls completely within the present time interval S.sub.N-1, wherein the start T.sub.1 of the transition interval TP begins prior to a boundary T.sub.0 between the present time interval S.sub.N-1 and the upcoming time interval S.sub.N, and the end T.sub.2 of the transition interval TP is aligned with the boundary T.sub.0 (a.k.a. a starting time of the CP in the upcoming time interval S.sub.N). Understandably, the CP is typically much shorter than the transition interval TP. Herein, the modulated target voltage V.sub.TGT indicates that the APT voltage V.sub.CC will decrease from the present voltage level V.sub.CC(N-1) (e.g., 2.9 V) in the present time interval S.sub.N-1 to the future voltage level V.sub.CC(N) (e.g., 2.3 V) in the upcoming time interval S.sub.N. Accordingly, the control circuit 38 determines the offset target voltage V.sub.TGT-OFF to be equal to the future voltage level V.sub.CC(N).

[0052] As for the amplifier target voltage V.sub.TGT-AMP, the control circuit 38 is configured to set the markup voltage V.sub.DIFF in the equation (Eq. 2) to 0 V (V.sub.TGT-AMP=V.sub.CC(N-1)+0). At time T.sub.1, the control circuit 38 opens the bypass switch S.sub.BYP and activates the voltage amplifier 32 (e.g., by coupling the higher supply voltage V.sub.SUPH to the voltage amplifier 32). Accordingly, the voltage amplifier 32 will generate the modulated voltage V.sub.AMP at the input 36 in accordance with the amplifier target voltage V.sub.TGT-AMP. In a non-limiting example, the voltage amplifier 32, with assistance from the auxiliary circuit 44, can instantly drive the modulated voltage V.sub.AMP from a GND level to the headroom voltage V.sub.NHEAD at time T.sub.1. Thereafter, the voltage amplifier 32 will continue to drive the modulated voltage V.sub.AMP up to the voltage differential V.sub.CC at time T.sub.2.

[0053] Starting at time T.sub.1, the offset capacitor C.sub.OFF is gradually discharged to reach the future voltage level V.sub.CC(N) at time T.sub.2. Accordingly, at time T.sub.2, the control circuit 38 closes the bypass switch S.sub.BYP and deactivates the voltage amplifier 32 to let the modulated voltage V.sub.AMP return to the GND level at time T.sub.3. The APT voltage V.sub.CC, which equals a sum of the modulated voltage V.sub.AMP and the offset voltage VOFF, will settle at the future voltage level V.sub.CC(N) at time T.sub.3. Notably, since the voltage amplifier 32 maintains the modulated voltage V.sub.AMP at or above the headroom voltage V.sub.NHEAD while the bypass switch S.sub.BYP is toggled, the APT voltage V.sub.CC will not drop below the headroom voltage V.sub.NHEAD, thus ensuring proper operation of the power amplifier circuit 28.

[0054] FIG. 5 is a timing diagram providing an exemplary illustration as to how the PMIC 24 of FIG. 2 operates under another possibility of the above-described operating scenario to decrease the APT voltage V.sub.CC. More specifically, FIG. 5 illustrates a situation where the headroom voltage V.sub.NHEAD (e.g., 0.4 V) is higher than or equal to the differential V.sub.CC (e.g., 0.1 V) between the present voltage level V.sub.CC(N-1) and the future voltage level V.sub.CC(N) (V.sub.NHEAD>V.sub.CC). Elements in FIG. 2 are referenced in FIG. 5 and will not be re-described herein.

[0055] As illustrated, the transition interval TP falls completely within the present time interval S.sub.N-1, wherein the start T.sub.1 of the transition interval TP begins prior to a boundary T.sub.0 between the present time interval S.sub.N-1 and the upcoming time interval S.sub.N, and the end T.sub.2 of the transition interval TP is aligned with the boundary T.sub.0 (a.k.a. a starting time of the CP in the upcoming time interval S.sub.N). Understandably, the CP is typically much shorter than the transition interval TP. Herein, the modulated target voltage V.sub.TGT indicates that the APT voltage V.sub.CC will decrease from the present voltage level V.sub.CC(N-1) (e.g., 2.9 V) in the present time interval S.sub.N-1 to the future voltage level V.sub.CC(N) (e.g., 2.8 V) in the upcoming time interval S.sub.N. Accordingly, the control circuit 38 determines the offset target voltage V.sub.TGT-OFF to be equal to the future voltage level V.sub.CC(N).

[0056] As for the amplifier target voltage V.sub.TGT-AMP, the control circuit 38 is configured to set the markup voltage V.sub.DIFF in the equation (Eq. 2) to equal the headroom voltage V.sub.NHEAD minus the differential V.sub.CC between the present voltage level V.sub.CC(N-1) and the future voltage level V.sub.CC(N) (V.sub.TGT-AMP=V.sub.CC(N-1)+V.sub.NHEADV.sub.CC). At time T.sub.1, the control circuit 38 opens the bypass switch S.sub.BYP and activates the voltage amplifier 32 (e.g., by coupling the higher supply voltage V.sub.SUPH to the voltage amplifier 32). Accordingly, the voltage amplifier 32 will generate the modulated voltage V.sub.AMP at the input 36 in accordance with the amplifier target voltage V.sub.TGT-AMP. In a non-limiting example, the voltage amplifier 32, with assistance from the auxiliary circuit 44, can instantly drive the modulated voltage V.sub.AMP from a GND level to the differential V.sub.CC at time T.sub.1. Thereafter, the voltage amplifier 32 will continue to drive the modulated voltage V.sub.AMP up to the headroom voltage V.sub.NHEAD at time T.sub.2.

[0057] Starting at time T.sub.1, the offset capacitor C.sub.OFF is gradually discharged to reach the future voltage level V.sub.CC(N) at time T.sub.2. Accordingly, at time T.sub.2, the control circuit 38 closes the bypass switch S.sub.BYP and deactivates the voltage amplifier 32 to let the modulated voltage V.sub.AMP return to the GND level at time T.sub.3. The APT voltage V.sub.CC, which equals a sum of the modulated voltage V.sub.AMP and the offset voltage VOFF, will settle at the future voltage level V.sub.CC(N) at time T.sub.3. Notably, since the voltage amplifier 32 maintains the modulated voltage V.sub.AMP at or above the headroom voltage V.sub.NHEAD while the bypass switch S.sub.BYP is toggled, the APT voltage V.sub.CC will not drop below the headroom voltage V.sub.NHEAD, thus ensuring proper operation of the power amplifier circuit 28.

[0058] With reference back to FIG. 2, in examples describe above, the control circuit 38 is configured to receive the modulated target voltage V.sub.TGT on a per time interval (a.k.a. per OFDM symbol) basis. In other words, the transceiver circuit 31 must communicate the future voltage level V.sub.CC(N) in the upcoming time interval S.sub.N during, or even before, the present time interval S.sub.N-1. As previously described in FIG. 1, in a time-division duplex (TDD) system, multiple time intervals (a.k.a. OFDM symbols) can be include in a modulation unit (a.k.a. TDD time slot or mini time slot). As such, it may be possible for the control circuit 38 to receive the modulated target voltage V.sub.TGT on a per modulation unit (a.k.a. TDD time slot or mini time slot) basis.

[0059] In this regard, the PMIC 24 may be preconfigured to include multiple power profiles 46(1)-46(N). In a non-limiting example, the power profiles 46(1)-46(N) can be organized into a profile lookup table (LUT) 48 and stored in a memory circuit 50. The power profiles 46(1)-46(N) may be stored in the memory circuit 50 by the transceiver circuit 31 via, for example, an RF front-end (RFFE) interface (not shown).

[0060] FIGS. 6A and 6B are block diagrams providing exemplary illustrations of the power profiles 46(1)-46(N) that may be employed by the PMIC 24 of FIG. 2 for enabling fast switching of the APT voltage V.sub.CC. Herein, each of the power profiles 46(1)-46(N) corresponds to a TDD time slot.

[0061] FIG. 6A shows an exemplary power profile 46A among the power profiles 46(1)-46(N). As shown, the power profile 46A may be determined to indicate the future voltage levels of one or more data symbols and one or more SRS symbols.

[0062] FIG. 6B shows an exemplary power profile 46B among the power profiles 46(1)-46(N). As shown, the power profile 46B may be determined to indicate the future voltage levels of one or more data symbols and one or more DMRS symbols.

[0063] With reference back to FIG. 2, in an embodiment, the transceiver circuit 31 may communicate a profile indication 52 to indicate a selected power profile among the power profiles 46(1)-46(N) to be used for an upcoming modulation unit (e.g., TDD time slot) during, or prior to, a present modulation unit (e.g., TDD time slot). Accordingly, the control circuit 38 may retrieve the selected power profile from the profile LUT 48 based on the received profile indication 52.

[0064] The PMIC 24 of FIG. 2 can be provided in a user element to enable fast voltage switching. FIG. 7 is a schematic diagram of an exemplary user element 100 wherein the PMIC of FIG. 2 can be provided.

[0065] Herein, the user element 100 can be any type of user elements, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user element 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more base stations. A low noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converter(s) (ADC).

[0066] The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application specific integrated circuits (ASICs).

[0067] For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission, and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 110. The multiple antennas 112 and the replicated transmit and receive circuitries 106, 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0068] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.