P-TYPE SPINEL STRUCTURES AS A P-N HETEROEPITAXIAL INTERFACE TO B-GA2O3

Abstract

Spinel and gallium oxide (Ga.sub.2O.sub.3) p-n heteroepitaxial interfaces and methods of making the same are presented. In embodiments, a method of manufacturing spinel structures includes depositing, via off-axis sputtering, an epitaxial layer of p-type spinel on a gallium oxide (Ga.sub.2O.sub.3) substrate, thereby creating a p-n heteroepitaxial interface between the p-type spinel and the Ga.sub.2O.sub.3 substrate. In implementations, a semiconductor device includes a Ga.sub.2O.sub.3 substrate; a p-type spinel epitaxial layer formed directly on a surface of the Ga.sub.2O.sub.3 substrate, thereby forming a p-n heteroepitaxial interface; and electrodes.

Claims

1. A method of manufacturing spinel structures comprising: depositing, via off-axis sputtering, an epitaxial layer of p-type spinel on a gallium oxide (Ga.sub.2O.sub.3) substrate, thereby creating a p-n heteroepitaxial interface between the p-type spinel and the Ga.sub.2O.sub.3 substrate.

2. The method of claim 1, wherein the p-type spinel is selected from the group consisting of: zinc gallate (ZnGa.sub.2O.sub.4), zinc cobalt oxide (ZnCo.sub.2O.sub.4), chromium manganese oxide (Cr.sub.2MnO.sub.4), magnesium aluminate (MgAl.sub.2O.sub.4), and zinc rhodium oxide (Zn Rh.sub.2O.sub.4).

3. The method of claim 1, wherein the p-type spinel is chromium manganese oxide (Cr.sub.2MnO.sub.4).

4. The method of claim 1, wherein the chromium manganese oxide (Cr.sub.2MnO.sub.4) is doped with lithium (Li) or chromium (Cr).

5. The method of claim 1, wherein the epitaxial layer has a thickness of between 5 nm and 500 nm.

6. The method of claim 1, wherein the gallium oxide (Ga.sub.2O.sub.3) substrate has a thickness between 100 m and 600 m.

7. The method of claim 1, wherein the off-axis sputtering is performed in an argon and oxygen atmosphere.

8. A spinel and gallium oxide (Ga.sub.2O.sub.3) p-n heteroepitaxial interface comprising: an epitaxial layer of p-type spinel growth directly on a surface of a gallium oxide (Ga.sub.2O.sub.3) substrate via off-axis sputtering.

9. The spinel and gallium oxide (Ga.sub.2O.sub.3) p-n heteroepitaxial interface of claim 8, wherein the p-type spinel is selected from the group consisting of: zinc gallate (ZnGa.sub.2O.sub.4), zinc cobalt oxide (ZnCo.sub.2O.sub.4), chromium manganese oxide (Cr.sub.2MnO.sub.4), magnesium aluminate (MgAl.sub.2O.sub.4), and zinc rhodium oxide (Zn Rh.sub.2O.sub.4).

10. The spinel and gallium oxide (Ga.sub.2O.sub.3) p-n heteroepitaxial interface of claim 9, wherein the p-type spinel is chromium manganese oxide (Cr.sub.2MnO.sub.4).

11. The spinel and gallium oxide (Ga.sub.2O.sub.3) p-n heteroepitaxial interface of claim 10, wherein the chromium manganese oxide (Cr.sub.2MnO.sub.4) is doped with lithium (Li) or chromium (Cr).

12. The spinel and gallium oxide (Ga.sub.2O.sub.3) p-n heteroepitaxial interface of claim 8, wherein the epitaxial layer has a thickness of between 5 nm and 500 nm.

13. The spinel and gallium oxide (Ga.sub.2O.sub.3) p-n heteroepitaxial interface of claim 8, wherein the gallium oxide (Ga.sub.2O.sub.3) substrate has a thickness between 100 m and 600 m.

14. A semiconductor device comprising: a gallium oxide (Ga.sub.2O.sub.3) substrate; a p-type spinel epitaxial layer formed directly on a surface of the Ga.sub.2O.sub.3 substrate, thereby forming a p-n heteroepitaxial interface; and electrodes.

15. The semiconductor device of claim 14, wherein the p-type spinel is selected from the group consisting of: zinc gallate (ZnGa.sub.204), zinc cobalt oxide (ZnCo.sub.2O.sub.4), chromium manganese oxide (Cr.sub.2MnO.sub.4), magnesium aluminate (MgAl.sub.2O.sub.4), and zinc rhodium oxide (Zn Rh.sub.2O.sub.4).

16. The semiconductor device of claim 15, wherein the p-type spinel is chromium manganese oxide (Cr.sub.2MnO.sub.4).

17. The semiconductor device of claim 16, wherein the chromium manganese oxide (Cr.sub.2MnO.sub.4) is doped with lithium (Li) or chromium (Cr).

18. The semiconductor device of claim 14, wherein the semiconductor device is a transistor.

19. The semiconductor device of claim 14, wherein the epitaxial layer has a thickness of between 5 nm and 500 nm.

20. The semiconductor device of claim 14, wherein the gallium oxide (Ga.sub.2O.sub.3) substrate has a thickness between 100 m and 600 m.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present invention are described in the detailed description which follows, in reference to the noted plurality of drawings by way of non-limiting examples of exemplary embodiments of the present invention.

[0009] FIG. 1A depicts a crystal lattice of Ga.sub.2O.sub.3 in a (2,0,1) plane compared to an (1,1,1) plane of a spinel structure.

[0010] FIG. 1B depicts hexagonal structures present in the crystal lattice of Ga.sub.2O.sub.3 and spinel structure of FIG. 1A.

[0011] FIG. 2A depicts an exemplary semiconductor device in accordance with embodiments of the invention.

[0012] FIG. 2B depicts another exemplary semiconductor device in accordance with embodiments of the invention.

[0013] FIG. 3 depicts an exemplary off-axis sputtering system utilized in accordance with embodiments of the invention.

[0014] FIG. 4 shows a flowchart of an exemplary method in accordance with aspects of the present invention.

DETAILED DESCRIPTION

[0015] Aspects of the present invention relate generally to gallium oxide (Ga.sub.2O.sub.3) semiconductor structures and, more particularly, to a method of making spinel/Ga.sub.2O.sub.3 p-n heterojunctions. In implementations, a semiconductor device (a diode, transistor, or other semiconductor device) is made including a p-n heteroepitaxial interface comprising a p-type spinel and a Ga.sub.2O.sub.3 layer (e.g., Ga.sub.2O.sub.3 substrate, or Ga.sub.2O.sub.3 layer on a substrate). In implementations, the spinel is deposited on the Ga.sub.2O.sub.3 utilizing off-axis sputtering (e.g., off-axis magnetron sputtering).

[0016] FIG. 1A depicts a crystal lattice 100 of Ga.sub.2O.sub.3 in a (2,0,1) plane compared to an (1,1,1) plane of a spinel structure 102. As noted above, the complex monoclinic structure of Ga.sub.2O.sub.3 makes it difficult to find materials for epitaxial growth that are well lattice-matched to Ga.sub.2O.sub.3. Examination of the (2,0,1) plane of Ga.sub.2O.sub.3 reveals a hexagon pattern of Ga atoms with a 3.04 side length. This matches well with the (1,1,1) plane of spinel structures having a hexagonal pattern. In embodiments, spinel materials are selected from zinc gallate (ZnGa.sub.2O.sub.4), zinc cobalt oxide (ZnCo.sub.2O.sub.4), chromium manganese oxide (Cr.sub.2MnO.sub.4), magnesium aluminate (MgAl.sub.2O.sub.4), and zinc rhodium oxide (Zn Rh.sub.2O.sub.4). Cr.sub.2MnO.sub.4, is of particular interest because doping the material with lithium (Li) or chromium (Cr) has demonstrated p-type behavior, allowing for control of doping. This allows for epitaxial growth to fabricate a p-n junction. These spinel materials can be used in the p-n junction, and the doping control of the p-layer can be controlled by adjusting the Li and/or Cr doping levels.

[0017] FIG. 1B depicts hexagonal structures present in the crystal lattice 100 of Ga.sub.2O.sub.3 and spinel structure 102 of FIG. 2A. Implementations of the invention utilize (2,0,1) -Ga2O.sub.3/(1,1,1) spinel growth, which may serve as the p-n junction in diodes, field effect transistors, and bipolar junction transistors, for example.

[0018] Spinel materials are complex oxides, and synthesis techniques are challenging. Implementations of the invention utilize a unique off-axis, ultra-high vacuum (110.sup.10 torr base pressure) magnetron combinatorial sputtering system to deposit the spinel onto a substrate. A specific demonstration resulting in epitaxial thin films of Cr.sub.2MnO.sub.4 fabricated by sputter beam epitaxy in an AJA International, Inc. thin film deposition system, with a base pressure of under ultra-high vacuum conditions, with beam-shaping shutter control and growth rate tuning via quartz crystal microbalance (QCM).

[0019] FIG. 2A depicts an exemplary semiconductor device 200A in accordance with embodiments of the invention. In implementations, the semiconductor device 200A is fabricated utilizing a method of the present invention, and includes a substrate of -Ga.sub.2O.sub.3 201, an epitaxial p-type spinel layer 202 grown on a surface of the -Ga.sub.2O.sub.3 201, an anode 203 formed on a surface of the epitaxial p-type spinel layer 202, and a cathode 204 formed on a surface of the -Ga.sub.2O.sub.3 201.

[0020] FIG. 2B depicts another exemplary semiconductor device 200B in accordance with embodiments of the invention. In implementations, the semiconductor device 200B is fabricated utilizing a method of the present invention, and includes a substrate of -Ga.sub.2O.sub.3 211, epitaxial p-type spinel layers 212A, 212B grown within respective trenches in the -Ga.sub.2O.sub.3 substrate 211, a source anode 213A and a drain anode 213B formed on a surface of respective epitaxial p-type spinel layers 212A, 212B, a cathode 214 formed on a surface of the -Ga.sub.2O.sub.3 substrate 211, and a gate electrode 215. In implementations, the gate electrode 215 comprises a gate oxide layer 216 formed over a portion of each of the epitaxial p-type spinel layers 212A, 212B and over an upper surface of the -Ga.sub.2O.sub.3 substrate 211, and a gate metal 217 formed over the gate oxide 216. The semiconductor device 200B of FIG. 2B thus comprises a transistor.

[0021] FIG. 3 depicts an exemplary off-axis sputtering system 300 utilized in accordance with embodiments of the invention. In implementations, the system 300 includes a sputtering chamber (vacuum chamber) 302, which provides a controlled epitaxial growth environment. A substrate holder (grounded sample holder) 303 within the sputter chamber 302 is configured to hold a substrate 304 to be coated with a target material represented by the spheres at 306. At least one gas supply line 308A supplies at least a first gas 310A from a gas source (not shown) into the sputtering chamber 302. In implementations, the gas 310A is an inert gas, such as argon, or a mix of an inert gas and oxygen. In embodiments, a second gas supply line 308B provides a second gas 310B from a gas source (not shown) into the sputtering chamber 302. In implementations, the second gas 310B is oxygen, and the first gas 310A is an inert gas. A sputtering gun 312 configured to supply the target material 306 is positioned within the sputtering chamber 302 at an angle (e.g., 90 degrees) with respect to a surface of the substrate 304 to be coated. A pressure control system 314 controls the pressure within the sputtering chamber 302. In use, power is applied to the target material, creating a glow discharge. Atoms of the target material 306 collide with each other and lose energy before reaching and coating the substrate 304 in a thin epitaxial film of the target material 306.

[0022] FIG. 4 shows a flowchart of an exemplary method in accordance with aspects of the present invention. FIG. 4 is discussed with reference to elements of FIGS. 2A and 2B, and may be implemented in the environment of FIG. 3.

[0023] At 401, a -Ga.sub.2O.sub.3 substrate (e.g., 201 or 211) is obtained or formed. In implementations, the -Ga.sub.2O.sub.3 substrate has a thickness of between 100 m and 600 m.

[0024] Optionally at 402, first and second spaced trenches are formed in the -Ga.sub.2O.sub.3 substrate (e.g., 211 of FIG. 2B). Existing trenching methods may be utilized at step 402.

[0025] At 403, an epitaxial layer of p-type spinel (e.g., 202) is formed on a surface of the Ga.sub.2O.sub.3 substrate (e.g., 201) via off-axis sputtering (e.g., sputter beam epitaxy), thereby creating a p-n heteroepitaxial interface between the p-type spinel and the Ga.sub.2O.sub.3 substrate. See FIG. 2A, for example. In some implementations, the epitaxial layer of p-type spinel comprises layers (e.g., 212A and 212B) deposited into respective trenches formed in the Ga.sub.2O.sub.3 substrate (e.g., 211). See FIG. 2B, for example. In implementations, the epitaxial layer of p-type spinel has a thickness of between 5 nm and 500 nm. In some embodiments, the epitaxial layer of p-type spinel has a thickness of up to 10 m. In other embodiments, the epitaxial layer of p-type spinel has a thickness of up to 50 m.

[0026] In general, off-axis sputtering is a deposition technique wherein a substrate to be coated with a target material is positioned off-axis with respect to the sputter gun providing the target material. In other words, the supply of target material (sputter gun) is not pointed directly at the center of the substrate or substrate holder. For example, a sputter gun supplying the target material may be positioned at an angle between 20-120 degrees with respect to the substrate. See the example in FIG. 3. In implementation, off-axis magnetron sputtering is used to deposit a spinel onto a Ga.sub.2O.sub.3 substrate.

[0027] In a typical sputtering deposition process, a chamber (e.g., 302) is first evacuated to high vacuum (e.g., 110.sup.10 torr base pressure) to minimize the partial pressures of background gases and potential contaminants. A sputtering gas comprising the plasma is flowed into the chamber and the total pressure is regulated using a pressure control system (e.g., 314). A high voltage is applied between a cathode (e.g., behind the sputtering target) and an anode (e.g., grounded to the chamber). Electrons in the sputtering gas are accelerated away from the cathode, causing collisions with nearby atoms of sputtering gas and resulting in an electrostatic repulsion which knock off electrons from the sputtering gas atoms, causing ionization. The positive sputter gas atoms accelerate towards the negatively charged cathode, leading to high energy collisions with the surface of the target material. Each collision causes atoms at the surface of the targe material to be ejected (e.g., as atoms 306) into the vacuum environment with enough energy to reach the surface of the substrate to be coated (e.g., 304).

[0028] In embodiments, the off-axis sputtering (e.g., sputter beam epitaxy) of step 403 comprises at least the following substeps.

[0029] At substep 403A, a Ga.sub.2O.sub.3 substrate (e.g., 304) is placed on a substrate holder (e.g., 303) within a sputtering chamber (e.g., 302) providing a controlled epitaxial growth environment.

[0030] At substep 403B, at least one supply line (e.g., 308A) provides at least one gas (e.g., 310A and/or 301B) from a gas source into the sputtering chamber (e.g., 302), and pressure within the chamber is controlled via a pressure control system (e.g., 314). In implementations, the gas is argon, or another inert gas. In implementations, oxygen is also fed into the sputtering chamber through a secondary supply line (e.g., 308B).

[0031] At substep 403C, a target material from a sputter gun is bombarded by energetic ions from a plasma via a radio frequency (RF) or direct current (DC) bias, causing the target material atoms (e.g., 306) to be ejected and deposited on the substrate (e.g., 304) for a period of time based on a desired thickness of the deposited target material. Existing off-axis sputtering techniques may be used to implement steps 403A-403C.

[0032] Optionally at 404, at least one anode (e.g., 203 or 213A, 213B) is formed on a surface of the epitaxial p-type spinel layer (e.g., 202 or 212A, 212B). See FIGS. 2A and 2B, for example.

[0033] Optionally, at 405, a cathode (e.g., 204 or 214) is formed on a surface of the Ga.sub.2O.sub.3 substrate (e.g., 201 or 211). See FIGS. 2A and 2B, for example. Existing electrode forming methods may be utilized at steps 404 and 405 in accordance with embodiments of the invention.

[0034] Optionally, at 406, a gate electrode (e.g., 215) is formed over the Ga.sub.2O.sub.3 substrate (e.g., 211) and the p-type spinel epitaxial layers (e.g., 212A, 212B). In implementations, the gate electrode 215 comprises a gate oxide layer (e.g., 216) in contact with the Ga.sub.2O.sub.3 substrate and the p-type spinel epitaxial layer (e.g., 212A, 212B), and a metal layer (e.g., 217) formed on a surface of the gate oxide layer. See FIG. 2B, for example.

[0035] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.